WO1988002928A1 - Remplissage des interconnexions entre couches dans une bande de ceramique a l'etat vert - Google Patents

Remplissage des interconnexions entre couches dans une bande de ceramique a l'etat vert Download PDF

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Publication number
WO1988002928A1
WO1988002928A1 PCT/US1987/002092 US8702092W WO8802928A1 WO 1988002928 A1 WO1988002928 A1 WO 1988002928A1 US 8702092 W US8702092 W US 8702092W WO 8802928 A1 WO8802928 A1 WO 8802928A1
Authority
WO
WIPO (PCT)
Prior art keywords
sheet
dielectric
dielectric tape
tape
filling
Prior art date
Application number
PCT/US1987/002092
Other languages
English (en)
Inventor
Patricia B. Opina
Original Assignee
Hughes Aircraft Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Company filed Critical Hughes Aircraft Company
Publication of WO1988002928A1 publication Critical patent/WO1988002928A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0147—Carriers and holders
    • H05K2203/016—Temporary inorganic, non-metallic carrier, e.g. for processing or transferring

Definitions

  • the disclosed invention generally relates to the . metallization of pyrplyzable dielectric tapes utilized in the fabrication of multilayer hybrid circuits and struc- tures, and more particularly is directed to a process for filling vias in such pyrolyzable dielectric tapes with metallization without the use of a screen printer.
  • Hybrid multilayer circuit structures may be made with layered sheets of dielectric tape known in the art as "green tape.” Generally, each layer of green tape is individually screen printed to fill preformed vias with metallization and to provide areas of metallization on its surface.
  • each layer of green tape is individually punched to form via holes, and then screen printed to provide conductor patterns and to fill via holes with metallization.
  • the individual layers of screen printed green tape are then stacked in the required order, and laminated together using a chosen temperature and pres ⁇ sure.
  • the laminated structure is then fired at a desired elevated temperature.
  • a layer of green tape having pre ⁇ formed vias is positioned on and registered to an insulat ⁇ ing substrate having, for example, a conductive pattern thereon.
  • the positioned green tape is laminated to the insulating substrate in a laminating press.
  • the laminated structure is then heated to a predetermined elevated temperature sufficient to drive off the organic binder material in the green tape and to securely fuse the inorganic filler material in the green tape to the under ⁇ lying substrate and the conductive pattern.
  • the conduc ⁇ tive pattern and the metallization in the via holes of the laminated green tape are then provided by screen printing.
  • the vias in a layer of green tape are filled with metallization by screen printing.
  • An important consideration with filling vias by screen printing is the importance of precise registration of the print screen with the vias. Changes in relative positions will result in misregistration of the via fill print screen.
  • a further consideration with screen printing via fill is the inability to use very small vias, which precludes denser packing of components. Screen printing via fill may also result in unfilled vias due to a clogged screen.
  • Still another advantage would be to provide a process for filling vias in dielectric tape which provides a uniform via fill.
  • FIG. 1 is a schematic illustration of dielectric tape which may be utilized with the process of the inven ⁇ tion.
  • FIG. 2 schematically illustrates a frame for secur- ing the dielectric tape in accordance with the invention.
  • FIG. 3 schematically illustrates a via filling fixture which may be utilized with the invention.
  • FIG. 4 schematically illustrates the use of the via filling fixture of FIG. 3 with the frame of FIG. 2.
  • FIG. 5 schematically depicts the filling of vias in the dielectric tape secured to the via filling fixture of FIG. 3 with the frame of FIG. 2.
  • FIGS. 6 and 7 schematically illustrate the use of the invention with dielectric tape that is laminated to an exposed surface of a substrate of a hybrid circuit or a previously fired layer of a hybrid circuit.
  • the sheet of dielectric tape 11 includes a dielectric layer 11a and an organic carrier layer lib.
  • the dielectric layer 11a is an alumina (aluminum oxide) filled glass with an organic binder, and is also referred to as a glass- ceramic. Other metal oxides such as beryllium oxide may also be used.
  • the organic carrier layer lib may be a sheet of Mylar brand film.
  • Dielectric tape for making the sheet of dielectric tape 11 may be may be obtained from E.I. DuPont de Nemours and Company of Wilmington, Delaware, under the generic references of "green tape” or “ceramic tape.” The "green” terminology does not refer to the color, but to the fact that it is an unfired ceramic tape.
  • the perimeter of the carrier side of the sheet of dielectric tape 11 is glued (e.g. , with a water soluble glue) or otherwise secured to the bottom of a flat frame 13.
  • the sheet of dielectric tape 11 is shown as being rectangular, and the frame 13 has a rectan ⁇ gular opening.
  • the side of the frame 13 secured to the sheet of dielectric tape 11 is substantially coplanar so that the sheet of dielectric tape 11 is secured in sub ⁇ stantially one plane.
  • the frame 13 may be made of machined aluminum.
  • the frame 13 further includes two registration holes 15 which are utilized with a via filling fixture 17 described below.
  • vias 19 are formed pursuant to the via pattern appropriate for the sheet of dielectric tape 11 being processed.
  • the vias 19 may be formed by mechanical punching, air or laser drilling, hydrostatic pressure, or photolithographic techniques.
  • the vias 19 may be formed prior to securing the sheet of dielectric tape 11 to the frame 13.
  • the via filling fixture 17 is basically a rigid panel which has a planar top surface and may be made of machined aluminum.
  • the fixture 17 includes on its top surface two registration pins 21 which correspond to the two registration holes 15 in the frame 13.
  • the frame 13 with the sheet of dielectric tape 11 secured thereto is placed on the via filling fixture 17 with the holes 15 securely engaged with the pins 21.
  • the bottom surface of the sheet of dielectric tape 11 is in intimate contact with the top surface of the via filling fixture, and the engaged holes 15 and pins 21 prevent lateral movement of the sheet of dielectric tape 11 relative to the via filling fixture 17.
  • a releaseable organic film such as a sheet of Mylar film may be interposed between the sheet of dielectric tape 11 and the top surface of the via filling fixture 17.
  • via fill paste 23 is placed on the top surface (the carrier side) of the sheet of dielec- trie tape 11 and is forced into the vias 19 with a squee ⁇ gee 25.
  • the squeegee 25 is illustrated schematically and may be implemented as a machine actuated device or a manually actuated device.
  • the excess paste is removed from the top surface of the sheet of dielectric tape, for example, with the squeegee 25.
  • the sheet of dielectric tape 11, including the organic carrier layer lib is peeled off the frame 13 and the glued perimeter portions are trimmed off.
  • the via-filled and trimmed sheet of dielectric tape 11 may then be stored or utilized as appropriate.
  • the invention further contemplates securing a dielectric tape having vias formed therein to the exposed surface of an insulating substrate of a hybrid circuit or to the exposed surface of a previously fired layer of a hybrid circuit.
  • the dielectric tape 11 with its organic carrier layer on top, is laminated to a substrate or previously fired layer 27 in a laminating press at an appropriate temperature with an appropriate pressure. After lamination, a squeegee is utilized to fill the via holes with via fill paste. After via filling, the organic carrier layer is removed for further processing, such as screen printing of conductor runs and passive circuit components, and firing.
  • the foregoing disclosed invention provides the advantages including the following.
  • the via holes in a sheet of dielectric tape are filled without the use of screen printing, thereby avoiding the necessity of prepar ⁇ ing via filling screens. Since via filling screens are not utilized, screen preparation is eliminated and the problems associated with screen printing via fill such as registration and clogging are avoided.
  • the organic carrier layer of the sheet of dielectric tape is in intimate contact with the dielectric layer during the formation of the via holes and during the via hole filling procedure, the organic carrier layer functions as a self-registered screen. Since the via holes are accurately filled without the use of screen printing, smaller vias are possible, which in turn facili ⁇ tate greater packing density.
  • the foregoing disclosed invention is readily incor ⁇ porated in known processes that utilize dielectric tape, including but not limited to the cofired ceramic process and the tape transfer process discussed previously in the Background of the Invention section hereof.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Procédé pour remplir les interconnexions entre couches dans une feuille de bande diélectrique destinée à être utilisée dans la fabrication de structures de circuit hybride multicouches. Le procédé consiste à assujettir sur un cadre (13) une feuille de ruban électrique (11) comportant une couche diélectrique et une couche porteuse, à former des trous d'interconnexions entre couches (19) dans la bande diélectrique, à fixer le cadre avec la bande diélectrique sur un dispositif (17) de remplissage d'interconnexions entre couches, à remplir des trous d'interconnexions avec un produit de métallisation approprié, et à enlever la bande diélectrique du dispositif de remplissage. L'invention concerne également le remplissage d'interconnexions entre couches d'une bande diélectrique fixée directement sur une surface exposée d'un circuit hybride pendant le processus de fabrication.
PCT/US1987/002092 1986-10-09 1987-08-24 Remplissage des interconnexions entre couches dans une bande de ceramique a l'etat vert WO1988002928A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US91732386A 1986-10-09 1986-10-09
US917,323 1986-10-09

Publications (1)

Publication Number Publication Date
WO1988002928A1 true WO1988002928A1 (fr) 1988-04-21

Family

ID=25438627

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1987/002092 WO1988002928A1 (fr) 1986-10-09 1987-08-24 Remplissage des interconnexions entre couches dans une bande de ceramique a l'etat vert

Country Status (2)

Country Link
IL (1) IL83843A0 (fr)
WO (1) WO1988002928A1 (fr)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0525497A1 (fr) * 1991-08-01 1993-02-03 E.I. Du Pont De Nemours And Company Procédé pour la formation de trous de contact dans des circuits multicouches
GB2262661A (en) * 1991-12-18 1993-06-23 Murata Manufacturing Co Manufacturing ceramic multilayer electronic components

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3956052A (en) * 1974-02-11 1976-05-11 International Business Machines Corporation Recessed metallurgy for dielectric substrates
EP0040905A1 (fr) * 1980-05-26 1981-12-02 Fujitsu Limited Fabrication de substrats en céramique pour circuits
WO1986003337A1 (fr) * 1984-11-19 1986-06-05 Hughes Aircraft Company Procede de fabrication de modules d'interconnexion dimensionnellement stables et produit obtenu par ce procede

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3956052A (en) * 1974-02-11 1976-05-11 International Business Machines Corporation Recessed metallurgy for dielectric substrates
EP0040905A1 (fr) * 1980-05-26 1981-12-02 Fujitsu Limited Fabrication de substrats en céramique pour circuits
WO1986003337A1 (fr) * 1984-11-19 1986-06-05 Hughes Aircraft Company Procede de fabrication de modules d'interconnexion dimensionnellement stables et produit obtenu par ce procede

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0525497A1 (fr) * 1991-08-01 1993-02-03 E.I. Du Pont De Nemours And Company Procédé pour la formation de trous de contact dans des circuits multicouches
US5293025A (en) * 1991-08-01 1994-03-08 E. I. Du Pont De Nemours And Company Method for forming vias in multilayer circuits
GB2262661A (en) * 1991-12-18 1993-06-23 Murata Manufacturing Co Manufacturing ceramic multilayer electronic components
DE4242843A1 (fr) * 1991-12-18 1993-06-24 Murata Manufacturing Co
US5274916A (en) * 1991-12-18 1994-01-04 Murata Manufacturing Co., Ltd. Method of manufacturing ceramic multilayer electronic component
GB2262661B (en) * 1991-12-18 1995-08-02 Murata Manufacturing Co A method of manufacturing ceramic multilayer electronic component
DE4242843B4 (de) * 1991-12-18 2005-09-08 Murata Mfg. Co., Ltd., Nagaokakyo Verfahren zur Herstellung von aus mehreren Keramikschichten aufgebauten Elektronikkomponenten

Also Published As

Publication number Publication date
IL83843A0 (en) 1988-02-29

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