WO1988001437A1 - Dispositifs a circuits integres - Google Patents

Dispositifs a circuits integres Download PDF

Info

Publication number
WO1988001437A1
WO1988001437A1 PCT/GB1987/000588 GB8700588W WO8801437A1 WO 1988001437 A1 WO1988001437 A1 WO 1988001437A1 GB 8700588 W GB8700588 W GB 8700588W WO 8801437 A1 WO8801437 A1 WO 8801437A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
devices
mounting structure
circuit devices
heat sink
Prior art date
Application number
PCT/GB1987/000588
Other languages
English (en)
Inventor
Peter Henry Saul
David John Pedder
Original Assignee
Plessey Overseas Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Limited filed Critical Plessey Overseas Limited
Publication of WO1988001437A1 publication Critical patent/WO1988001437A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3738—Semiconductor materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73207—Bump and wire connectors

Definitions

  • This invention relates to integrated circuit devices.
  • the present invention was devised to provide a silicon motherboard assembly suitable for connecting numbers of integrated circuit chips and in which heat transfer problems were able to be reduced.
  • a mounting structure for a plurality of integrated circuit devices comprising a semiconductor material heat sink body having a surface provided with recessed well areas capable of locating the said -la-
  • the circuit devices having electrical connection points which are located on a side of each device which is positioned away from said heat sink body, the said connection points being electrically connected by means of solder bump interconnectors to a common interconnect member so as to provide electrical interconnections between the said devices and external connection means for the devices in the structure.
  • the said heat sink body supports a slice of semiconductor material in which the recessed well areas are formed.
  • the integrated circuit devices may be thermally connected to said semiconductor material slice for effective heat transfer thereto.
  • the said common interconnect member may comprise a slice of semiconductor material.
  • the common interconnect member may comprise two or more secondary boards providing the electrical interconnections and external connection means.
  • At least one of the said secondary boards may carry an additional semiconductor device.
  • the additional device may comprise an input/output buffer for an integrated circuit device of the plurality carried on said substrate.
  • the mounting structure comprises a body 1 which incorporates means for heat sinking and which is made for example of a ceramic material with an external shape corresponding to that of a conventional integrated circuit package such as a dual-in-line, pin grid array, tape automatic bond or a leaded or leadless chip carrier.
  • a conventional integrated circuit package such as a dual-in-line, pin grid array, tape automatic bond or a leaded or leadless chip carrier.
  • the ceramic body 1 supports a silicon substrate slice 2 and in turn this supports three potentially active silicon devices 3.
  • the silicon devices 3 are located in shallow wells (not shown) formed in the surface of the slice 2. The wells help to correctly position the devices -3-
  • the bonding between the carrier body 1 and the substrate 2, and also between the substrate 2 and the silicon devices 3 is effected by an alloy or epoxy resin bonding material which has good heat transfer properties.
  • silicon 'jumper* chips 4 are positioned to the left and right hand ends of the substrate slice 2.
  • solder bump interconnectors 6 are electrically connected together to join the required circuit components by a silicon interconnect slice 7 which extends above all the devices 3 and chips 4 on the substrate slice 2. Additional connections may also be made between circuit terminations on the chips 4 and electrical points on the ceramic body 1 by bond wires 8.
  • the integrated circuit mounting structure of the invention has been found to be particularly suitable for mounting high power dissipation devices since it enables resulting heat transfer problems to be reduced and it thus has advantages over the currently available silicon motherboard systems. Since, the silicon devices 3 are connected to a first silicon motherboard constituted by the interconnect slice 7 for the electrical connections and additionally to a second silicon motherboard constituted by the silicon substrate 2 for heat transfer connections an extremely rigid structure can be provided. Because the structure is made of silicon throughout, thermal expansion mismatch problems are unlikely to occur. In addition, an electrical screening effect is provided by the presence of the electrically conducting motherboards on each side of the devices 3.
  • the said first silicon motherboard constituted by the interconnect slice 7 may be made up of a number of smaller boards.
  • the jumper chips 4 are intended to serve an interconnection function but they could be readily made alternatively to serve as active chips in their own right.
  • One advantageous configuration would be for the jumper chips to incorporate input/output buffer devices.
  • some manufacturing difficulty might be expected to occur in providing a number of chips for the mounting structure which are of identical thickness.
  • silicon slice thickness is now readily controllable and it is repeatable in manufacture so this is unlikely to cause any problem.
  • etching or polishing of the thickest slices down to a common thickness specification might be necessary.
  • An accurate location of the chips on the lower substrate is also important.
  • the required accuracy could be achieved, for example, by forming the receiving wells on the substrate by an etching operation which would exactly define the required chip positions.
  • the heat sink body should be formed of silicon monolithic material, in a different embodiment this could be of an alternative semiconductor such as gallium arsenide.
  • the integrated circuit devices could also be formed of alternative materials to silicon such as gallium arsenide, indium phosphide or gallium aluminium arsenide. Integrated circuit devices of dissimmilar materials could be mounted on the common heat sink body.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

Une structure de montage pour une pluralité de dispositifs à circuits intégrés comprend un corps dissipateur thermique (2) en matériau semi-conducteur présentant une surface pourvue de zones de puits évidées pouvant positionner les dispositifs à circuits intégrés (3) les uns par rapport aux autres, les dispositifs à circuits intégrés (3) possédant des points de connexion électrique situés sur un côté de chaque dispositif positionné à une certaine distance du corps dissipateur thermique (2), lesdits points de connexion étant reliés électriquement à l'aide d'éléments d'interconnexion (6) à perles de soudure à un organe d'interconnexion commun (7), de manière à établir des connexions électriques entre lesdits dispositifs (3) et les organes de connexion externes des dispositifs (3) de la structure. Cet agencement permet d'obtenir une bonne dissipation thermique et est particulièrement utile dans des dissipateurs de grande puissance.
PCT/GB1987/000588 1986-08-20 1987-08-20 Dispositifs a circuits integres WO1988001437A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8620291A GB2194388A (en) 1986-08-20 1986-08-20 Integrated circuit devices
GB8620291 1986-08-20

Publications (1)

Publication Number Publication Date
WO1988001437A1 true WO1988001437A1 (fr) 1988-02-25

Family

ID=10602999

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/GB1987/000588 WO1988001437A1 (fr) 1986-08-20 1987-08-20 Dispositifs a circuits integres

Country Status (2)

Country Link
GB (1) GB2194388A (fr)
WO (1) WO1988001437A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0331245A2 (fr) * 1988-03-01 1989-09-06 Lsi Logic Corporation Conteneur de puces à circuit intégré et procédé de fabrication
EP0372108A1 (fr) * 1988-12-05 1990-06-13 Heinz Karl Diedrich Récipient à vide pour le refroidissement cryogénique d'un empaquetage pour dispositif électronique
EP0460785A1 (fr) * 1990-06-05 1991-12-11 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur comprenant un refroidisseur

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2312172A1 (fr) * 1975-05-22 1976-12-17 Ibm Procede de fabrication d'ensembles de circuits integres
JPS58143556A (ja) * 1982-02-22 1983-08-26 Fujitsu Ltd 高密度集積回路用パツケ−ジ
GB2144907A (en) * 1983-08-09 1985-03-13 Standard Telephones Cables Ltd Mounting integrated circuit devices

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0007993A1 (fr) * 1978-07-12 1980-02-20 Siemens Aktiengesellschaft Plaque de conducteurs pour le montage et la connexion électrique de pastilles semiconductrices
US4246597A (en) * 1979-06-29 1981-01-20 International Business Machines Corporation Air cooled multi-chip module having a heat conductive piston spring loaded against the chips
US4561011A (en) * 1982-10-05 1985-12-24 Mitsubishi Denki Kabushiki Kaisha Dimensionally stable semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2312172A1 (fr) * 1975-05-22 1976-12-17 Ibm Procede de fabrication d'ensembles de circuits integres
JPS58143556A (ja) * 1982-02-22 1983-08-26 Fujitsu Ltd 高密度集積回路用パツケ−ジ
GB2144907A (en) * 1983-08-09 1985-03-13 Standard Telephones Cables Ltd Mounting integrated circuit devices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, Volume 27, No. 1B, June 1984, (New York, US), M.J. BRADY et al.: "Etched Silicon Integrated Circuit Heat Sink", see page 627 *
PATENT ABSTRACTS OF JAPAN, Volume 7, No. 258 (E-211) (1403), 17 November 1983, & JP, A, 58143556 (Fujitsu K.K.) 26 August 1983 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0331245A2 (fr) * 1988-03-01 1989-09-06 Lsi Logic Corporation Conteneur de puces à circuit intégré et procédé de fabrication
EP0331245A3 (fr) * 1988-03-01 1991-05-08 Lsi Logic Corporation Conteneur de puces à circuit intégré et procédé de fabrication
EP0372108A1 (fr) * 1988-12-05 1990-06-13 Heinz Karl Diedrich Récipient à vide pour le refroidissement cryogénique d'un empaquetage pour dispositif électronique
EP0460785A1 (fr) * 1990-06-05 1991-12-11 Mitsubishi Denki Kabushiki Kaisha Dispositif semi-conducteur comprenant un refroidisseur
US5247203A (en) * 1990-06-05 1993-09-21 Mitsubishi Denki Kabushiki Kaisha Semiconductor device mounted on a heat sink with an intervening amorphous semiconductor material
US5332695A (en) * 1990-06-05 1994-07-26 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semi conductor device mounted on a heat sink

Also Published As

Publication number Publication date
GB2194388A (en) 1988-03-02
GB8620291D0 (en) 1986-10-01

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