WO1986005323A1 - Dispositif de memoire remanente a porte flottante a effet de champ - Google Patents

Dispositif de memoire remanente a porte flottante a effet de champ Download PDF

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Publication number
WO1986005323A1
WO1986005323A1 PCT/US1986/000372 US8600372W WO8605323A1 WO 1986005323 A1 WO1986005323 A1 WO 1986005323A1 US 8600372 W US8600372 W US 8600372W WO 8605323 A1 WO8605323 A1 WO 8605323A1
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Prior art keywords
layer
floating gate
silicon
memory device
charge
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PCT/US1986/000372
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English (en)
Inventor
Roberto Romano-Moran
James Anthony Topich
Thomas Edward Cynkar
Raymond Alexander Turi
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Ncr Corporation
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Publication date
Application filed by Ncr Corporation filed Critical Ncr Corporation
Priority to DE1986901679 priority Critical patent/DE215064T1/de
Publication of WO1986005323A1 publication Critical patent/WO1986005323A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7882—Programmable transistors with only two possible levels of programmation charging by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction

Definitions

  • This invention relates to floating gate nonvolatile memory devices of the kind including a first electrically conductive layer adapted to provide electrical charge, and an electrically conductive floating gate layer situated within a region over said first conductive layer and separated from the first conductive layer by a dielectric layer for charging and discharging the floating layer.
  • Floating gate type nonvolatile memories are well-known in the prior art. They operate by transferring charge of prescribed polarity to an electrically isolated gate electrode, the "floating gate", which thereafter serves to retain the charge over an extended period of time and control the operation of a field effect type sense transistor in response to the polarity and magnitude of the charge then residing on the floating gate.
  • the conventional floating gate type memory cell is first subjected to an erase cycle and only then written to the new binary state.
  • conventionally configured floating gate devices those using silicon dioxide (oxide) as the dielectric between the substrate and the floating gate, deteriorate with repetitive write/erase cycles.
  • the preferred configuration is an ultra thin composite dielectric of a thermal oxide layer, a thermal oxynitride from oxide layer, and a thermal oxide from oxynitride layer.
  • the charge transfer mechanism is Fowler- Nordheim tunneling through the very thin composite dielectric
  • a further variation as to the composition of the dielectric used in a floating gate structure to improve performance is described in the paper entitled "Electrically Alterable Read-only Memory Cell with Graded Energy Band-Gap Insulator", by Hijiya et al., which appeared as paper 23.4 in IEDM 1980, p. 590-593.
  • the floating gate is isolated from the substrate by a composite of dielectric layers made up of either graded silicon oxynitride (oxynitride) and oxide, or in the alternative, graded silicon nitride (nitride), oxynitride and oxide, where the nitride is thermally formed.
  • charge transfer to and from the floating gate is performed by avalanche injection.
  • the dielectric is composed of a very thin (approximately 10 nm) thermally formed nitride layer. Being thermally formed, the nitride layer is relatively thin. The transfer of charge to and from the floating gate is performed by avalanche injection.
  • a floating gate nonvolatile memory device of the kind specified, characterized in that said dielectric layer includes a layer of silicon nitride based dielectric having a thickness in the range of from about 5 to about 30 nanometers and having charge trapping sites which provide a Poole-Frenkel charge transport mechanism therethrough.
  • a floating gate nonvolatile memory device can be written and erased with voltage pulses of relatively low amplitude and short duration, yet exhibits excellent endurance and retention characteristics.
  • a floating gate nonvolatile memory device includes a ' conductively doped polycrystalline silicon (poly) floating gate electrode, one portion of which is situated over a conductive region in a substrate and separated from the substrate by a thin thermally formed oxide layer and a thin low pressure chemical vapor deposited (LPCVD) nitride based layer.
  • LPCVD thin low pressure chemical vapor deposited
  • the transfer of charge through the nitride based layer relies upon a Poole-Frenkel conduction mechanism. Long term leakage of charge from the floating gate through the nitride based layer is further inhibited by the presence of the oxide dielectric layer.
  • Write/erase mode transfer of charge is by Fowler- ordheim tunneling through the oxide and Poole-Frenkel conduction through the nitride based layer.
  • a floating gate nonvolatile memory device includes a conductively doped polycrystalline silicon (poly) floating gate electrode, one portion of which is situated over a conductive region in a substrate and separated from the substrate by a very thin thermally formed silicon dioxide layer, an overlying relatively thicker low pressure chemical vapor deposited (LPCVD) silicon nitride layer, and a relatively thin LPCVD oxide or oxynitride based layer.
  • the oxide and oxynitride layers are amenable to Fowler-Nordheim tunneling of charge, while charge movement through the relatively thicker nitride employs a Poole-Frenkel conduction mechanism.
  • Fig. 1 is an enlarged schematic top view of a memory cell layout configured in accordance with the principles of the present invention
  • Fig. 2 is a cross section of Fig. 1 taken along line 2-2;
  • Fig. 3 is a cross section of Fig. 1 taken along line 3-3;
  • Fig. 3A is a cross section of an alternate embodiment for the charge transfer region
  • Fig. 4 is an electronic circuit equivalent of the memory cell depicted in Fig. 1;
  • Fig. 5 presents representative write/erase characteristics for a memory cell of the form in Fig. 1;
  • Fig. 6 presents representative retention/ endurance characteristics for the memory cell depicted in Fig. 1;
  • Fig. 7 is a magnified schematic showing the photolithographic masking pattern of an alternative embodiment of a cell embodying the present invention
  • Fig. 8 is a schematic electronic circuit representation of the memory cell pattern depicted in Fig. 7.
  • Fig. 9 is a cross sectional schematic of the cell depicted in Fig. 7 taken at location 9-9;
  • Fig. 10 depicts the linear transfer characteristics of the sensing field effect transistor, showing its intrinsic characteristics and operation when in written and erased states;
  • Fig. 10A shows the test circuit used to derive the results plotted in Fig. 10;
  • Fig. 11 depicts the write/erase characteristics of the memory cell shown in Fig. 7; and Fig. 12 shows the decay of the memory window with time at elevated temperature after multiple write/erase cycles.
  • FIG. 1 A representative floating gate type nonvolatile memory cell embodying the features of the present invention is depicted schematically in Fig. 1, generally at 1. It should be understood that memory cell 1 is normally used in integrated circuit memory arrays comprised of multiple interconnected cells addressable individually or in groups for purposes of writing, erasing or reading the binary data stored therein. Furthermore, it should be appreciated that the memory cell structures depicted and described are merely representative of the configurations by which the principles of the present invention may be practiced.
  • Memory cell 1 as depicted in Figs. 1, 2 and 3 is formed in a lightly doped p-type monocrystalline silicon substrate 2 using n-type diffused regions to form electrically conductive layers and dielectrically isolated doped polycrystalline silicon electrode and interconnect layers.
  • bit line 3 begins as a diffusion, is connected by channel 4 of field effect transistor (FET) Ql to further diffusion 6 and through channel 7 of sense FET Q2 to grounded diffusion 8 by way of diffusion 5, a diffused region beneath poly II layer 18, and diffusion 10. It may be of assistance to refer to Fig. 4 where the equivalent electronic circuit schematic is depicted.
  • FET field effect transistor
  • Write line 9 of the memory cell 1 is also a diffusion within semiconductor substrate 2, being separated by channel 11 of FET Q3 from further diffusions 12 and 13, where diffusion 13 lies beneath poly II layer 18 and further extends beneath poly I layer 17. Note that diffusion 13 extends from diffusion 12, under charge transfer region 14 and to the edge of field oxide 15 (Fig. 3).
  • diffused regions 3, 6, 8, 9, 10 and 12 are heavily doped n +
  • regions 5 and 13 are doped with n type impurity but to a lesser extent.
  • the heavily doped n-f regions can be formed by ion implantation using ions of phosphorus or arsenic, phosphorus diffused from a POCI3 source, or furnace diffused from another source of impurity.
  • the lightly doped regions are formed by ion implantation of phosphorus or arsenic prior to deposition of the first polysilicon layer.
  • a first level of doped polycrystalline silicon forms floating gate electrode 17, which overlaps diffused region 13, charge transfer region 14, and channel 7 to form sense FET Q2.
  • poly I doped polycrystalline silicon
  • the presence of charge on floating gate electrode 17 will affect the conduction characteristic of channel 7.
  • poly II level control line electrode 18 Overlying floating gate 17, but dielectrically isolated therefrom, is poly II level control line electrode 18. Note that the size and proximity of floating gate electrode 17 to control line electrode 18 provides significant capacitive coupling therebetween.
  • the poly II level also forms word line 16 and defines channel regions 4 at Ql and 11 at Q3.
  • the greater length of channel 11 is consistent with the higher punch-through voltage requirements of FET Q3.
  • regions 5 and 13 contain sufficient dopant to ensure that potentials on control line 18 have substantially no effect on conduction in such diffused regions.
  • the focus of the present invention is directed toward the structure and composition of the dielectric in charge transfer region 14 of cell 1.
  • the present invention contemplates that charge transfer dielectric layer 19 (Fig. '3), situated between diffused channel 13 and poly I floating gate 17, be comprised of a layer of silicon nitride based dielectric which is formed or treated to facilitate as a primary charge transfer mechanism bidirectional Poole-Frenkel conduction of charge between diffusion 13 and floating gate electrode 17.
  • charge trap sites in such nitride based layer facilitates the desired Poole- Frenkel conduction, while the band gap energy barriers between nitride based layer 19 and polysilicon floating gate 17 on one side and monocrystalline silicon diffused region 13 on the other side limit the leakage of charge off floating gate 17.
  • nitride based dielectric layer encompasses nitride alone, oxynitride or graded oxynitride layers.
  • nitride based dielectric 19 which facilitates Poole-Frenkel conduction bidirectionally therethrough creates a floating gate memory cell with improved endurance characteristics in comparison to memory cells employing oxide based dielectrics. Whereas charge transfer through oxide based dielectrics degrades measurably with multiple write/erase cycles, due to dielectric damage mechanisms and hot electron charge trapping, charge trap sites in LPCVD or APCVD nitride based dielectrics readily facilitate charge transfer without significant permanent degradation.
  • dielectric 19 in charge transfer region 14 as shown in Fig. 3 is depicted in Fig. 3A.
  • the dielectric is a composite including a very thin oxide lower layer 21 immediately adjacent diffused region 13 covered by a thicker nitride based dielectric layer 22, which top layer is itself in contact with floating gate 17.
  • Layer 21 is preferably a thermally grown silicon dioxide. Layer 21 is made sufficiently thin that any Fowler-Nordheim tunneling therethrough is accomplished with a minimum electric field, while nitride based layer 22 serves to limit the current density of the charge tunneling through layer 21. As was true for the embodiment depicted in Fig. 3, the relative proximity of poly II level control line 18 to poly I level floating gate 17 creates significant capacitive coupling therebetween. The two electrodes are separated by dielectric layer 23 which is preferably 50 to 100 nanometers thick of oxide or 30 to 60 nanometers thick of nitride. Present experience suggests that the thickness of nitride layer 19 shown in Fig. 3 be in the range of 5-30 nanometers. For the composite dielectric depicted in Fig. 3A, present experience suggests that oxide layer 21 have a thickness of approximately 1-4 nanometers, and that nitride based layer 22 have a thickness of approximately 5-30 nanometers.
  • Figs. 5 and 6 of the drawings show that the write/erase characteristic plots depicted in Fig. 5 are merely representative of nitride based dielectric memory cell devices, they do clearly show that the dielectric creates a floating gate type memory cell which is responsive to relatively low voltage pulses of relatively short duration.
  • a nitride layer 19 FIG. 3
  • the memory cell exhibits a Q2 sense FET write/erase window of approximately 8 volts using write/erase pulses of no more than 15 volts amplitude and 1 millisecond duration.
  • Fig. 6 of the drawings The excellent endurance characteristics of such memory cells are depicted in Fig. 6 of the drawings.
  • the storage time of nonvolatile nitride dielectric memory cells written with 19 volt and 20 microsecond pulses are extrapolated with time for both new cells and cells which have undergone lO'* write/erase cycles.
  • plot lines 26, defining the window for memory cells after application of 10 write/erase cycles are degraded only to a moderate extent when compared to plot lines 24, which define the window for new memory cells.
  • the plots depicted in Fig. 6, as with those depicted in Fig. 5, are merely representative of the improved retention and endurance characteristics which can be obtained from memory cells utilizing nitride based dielectric layers formed so as to provide bidirectional Poole-Frenkel conduction of floating gate charge.
  • TABLE 1 provides for purposes of comparison breakdown field data and field intensity data in relation to levels of current density, with a summary in the form of a figure of merit.
  • floating gate devices which employ oxide alone as the charge transfer dielectric provide significantly less margin between the field intensity required to conduct and the field intensity which causes dielectric breakdown and potentially irreversible damage to the dielectric.
  • the first three materials proposed as dielectrics, silicon nitride alone, thin silicon dioxide combined with silicon nitride, and silicon oxynitride are consistently better than oxides alone.
  • TABLE 1 lends further support for the preference of nitride as the charge transfer dielectric. Note in this regard that the electric field required to create a given current density is less for nitride based materials, adding weight to the proposition that the use of a nitride dielectric allows lower programming voltages as well as faster programming times, or the use of thicker nitride layers while retaining the same levels of programming voltages.
  • the writing of memory cell 1 is accomplished by placing control line 18 and bit line 3 at ground potential while applying the program voltage Vpp on word line 16 and write line 9. With those conditions, the capacitive coupling between control line 18 and floating gate 17 essentially brings floating gate 17 to ground potential, while the voltage combination on write line 9 and word line 16 ensures conduction through FET Q3 to provide a voltage of approximately Vp -Vru at diffusions 12 and 13. V-pjj is the threshold voltage of transistor Q3. Thereby, nitride based dielectric 14 is subjected to an electric field corresponding to a relative voltage of approximately Vpp-V-p-g. By following this procedure electrons are removed from floating gate 17 ' . The formation of the opposite, erased, state in memory cell 1 involves the application of the opposite voltage states on control line 18 and write line 9, so that electrons are moved onto floating gate 17. Refer to the conditions set forth in TABLE 2.
  • a reading of the binary state on floating gate 17 is performed by placing control line 18 and write line 9 at ground potential, addressing word line 16 using a nominal Ql enabling potential (e.g. 5 volts), and applying a sense amplifier voltage, for instance a 2 volt precharge, on bit line 3. Since FET Ql is conductively biased, the sense amplifier connected to bit line 3 will detect whether the floating gate potential makes sense FET Q2 conductive or not.
  • a nominal Ql enabling potential e.g. 5 volts
  • the erase inhibit mode set forth in TABLE 2 provides additional flexibility in the use of the embodying memory cell, in that it allows bank or word selection during the operation of the erase mode.
  • memory cell 1 constitutes but one of a multiplicity of matrix arranged cells within an integrated circuit structure.
  • the erase inhibit mode provides the feature by which this can be accomplished. According to that mode, erasure of memory cells is inhibited for those cells which have a voltage of Vpp on write line 9 during the erase mode.
  • the erase inhibit signal prevents the formation of a relative potential across nitride dielectric 14.
  • erase inhibit allows the use of a common control line 18 for the memory array, while utilizing write lines 9 which are already arranged by banks or other groups of memory cells. It should also be understood that the arrangement of the disclosed memory cell allows a reading of the cell state -while control line 18 and write line 9 are at ground potential. Thereby, the disturbance of the charge on floating gate 17 is minimized for each read cycle.
  • the fabrication of memory cell 1 employs to a large extent technology which is commonly known by those routinely practicing in the art. In all cases the important objective is to ensure that the nitride based dielectric layer is formed in such a way that it is conducive to Poole-Frenkel conduction, while any supplemental oxide layer is sufficiently thin that tunneling therethrough can be accomplished with the use of relatively low electric field intensities, corresponding to relatively low write/erase voltages.
  • Representative charge transfer dielectric layers can be formed by using the following, exemplary fabrication conditions.
  • the silicon dioxide dielectric layer 21 (Fig. 3A) is grown from monocrystalline silicon substrate 2 by subjecting the wafer to a 1:1 mixture of N2 and O2 gas at atmospheric pressure and 750°C.
  • the formation of the nitride based dielectric 22, whether it be silicon nitride, silicon oxynitride or graded silicon oxynitride, preferably follows in the immediately succeeding furnace operation.
  • silicon nitride layer this involves an LPCVD. deposition process performed at approximately 600 mtorr and 750°C using a 3.5:1 mixture of dichlorosilane to ammonia.
  • a silicon oxynitride version of the nitride based layer is preferably formed in an LPCVD process at approximately 600 mtorr and 750°C using a 3.5:1:2 mixture of dichlorosilane to ammonia to nitrous oxide. If a graded oxynitride layer is to be deposited, the mixture would be varied to adjust the gas composition over the duration of the deposition cycle in proportion to the desired formation.
  • a nonvolatile floating gate type memory cell which cell incorporates the use of a deposited silicon nitride based dielectric as the charge transfer medium and uses Poole-Frenkel conduction as the charge transfer mechanism.
  • the nitride based dielectric memory cell exhibits excellent endurance and acceptable retention characteristics, while being responsive to write/erase voltages having relatively low amplitudes and short pulse durations.
  • the nitride based dielectric itself is characterized by its ability to conduct charge bidirectionally using nitride trap sites formed during nitride deposition.
  • the dielectric is composed of a thin silicon dioxide layer formed directly over a conductively doped ' region in a silicon substrate, which layer is itself * covered by a relatively thick layer of LPCVD silicon nitride, and further has a thin oxynitride layer between the nitride and the overlying floating gate electrode.
  • charge is bidirectionally tunneled through the oxide and oxynitride layers by a Fowler- Nordheim mechanism, while bidirectional movement of charge through the relatively thick nitride is accomplished by Poole-Frenkel conduction using charge traps present in LPCVD nitrides.
  • the oxynitride prevents movement of charge from the floating gate back into the nitride layer, while the composite oxide and oxynitride on either side of the nitride ensures that any charge held by the nitride traps remains and as such serves to electrostatically shield the charged floating gate from the substrate.
  • the embodying memory cell 101 * is composed of a field effect sense transistor 102 having source/drain connections 104 and 106 and floating gate electrode 107, which gate electrode constitutes a portion of the memory cell floating gate. Charge is transferred to and from floating gate 107 by the capacitive coupling from control gate 108 using as a cha-rge source injector 109, which according to the embodiment is a diffusion region in the substrate 111.
  • floating gate 107 is a first layer of doped polycrystalline silicon (poly I) while control gate 108 is formed from a second layer of doped polycrystalline silicon (poly II). As is commonly practiced, the various regions are isolated by field oxide 112.
  • the focus of the present invention is at region 113, where according to this invention an im ⁇ proved composite dielectric structure 115 provides for bidirectional movement of charge to and from floating gate 107 using a relatively low voltage and pulse duration while providing improved endurance and reten- tion characteristics.
  • the capacitive coupling between floating gate 107 and control gate 108 is, as shown in Fig. 9, provided through silicon dioxide dielectric layer 114, nominally 100 nanometers thick.
  • floating gate 107 is separated from n + diffusion 9 in p-type substrate 111 by a composite dielectric structure 115 of thin silicon dioxide layer 16, a relatively thick silicon nitride layer 117 and a relatively thin silicon oxynitride layer 118.
  • the lateral oxide 119 corresponds to the gate oxide formed for sense FET 102, which for purposes of charge transfer in region 113 has been cut away to allow the formation of composite dielectric 115.
  • gate oxide 119 would be approxi ⁇ mately 30-50 nanometers thick
  • tunneling oxide 116 would be thermally grown silicon dioxide having an overall thickness of approximately 2 nanometers
  • layer 117 would be approximately 10-20 nanometers of LPCVD silicon nitride
  • layer 118 would be approximately 4-6 nanometers .of LPCVD oxynitride.
  • nitride layer 117 and oxynitride layer 118 are shown in Fig. 9 as patterned local to region 113, it is equally feasi ⁇ ble to retain nitride and oxynitride in an extended pattern coextensive with floating gate 107.
  • ni ⁇ tride within the gate structure of standard FETs, such as sense FET 102, can lead to long term instabilities in the threshold voltage of such FETs.
  • nitride layer 117 and oxynitride layer 118 do extend onto residuals of gate oxide 119. Nevertheless, by virtue of the gradient in the electric field between diffused region 109 and floating gate 107 during the write/erase operations, the tunneling and nitride conduction charge transfer is effectuated through the region centered within the cut in gate oxide 119.
  • FIG. 9 An alternate structural embodiment to that depicted in Fig. 9 would replace oxynitride 118 with a thin silicon dioxide layer having a thickness compara ⁇ ble to or slightly greater than that of oxide layer 116.
  • the operation of the nonvolatile cell depicted in Figs. 6-9 is best understood by recogniz ⁇ ing that floating gate 107 also serves as the gate electrode for sense FET 102. Thereby, the conduction between drain diffusion 106 and source diffusion 106 is dictated by the charge retained on floating gate 107. With this configuration, the transfer of charge from diffusion 109 onto floating gate 107 biases the threshold voltage of sense FET 102.
  • floating gate 107 is itself capacitively coupled to control gate 108 by the proximity between floating gate 107, formed as a poly I electrode layer, and control gate 108, formed as a poly II electrode layer, as depicted in Figs. 7 and 9.
  • An exemplary set of conduction characteristics is set forth in Fig. 10, where the drain current is shown to have a response, when tested in accordance with the circuit depicted' in Fig. 10A, according to plot 121 for an intrinsic sense FET, and is shifted between blocks 122 and 123 depending on the polarity of the charge transferred onto floating gate 107 upon the application of write or erase pulses.
  • the pulses were 16 volts in amplitude and 1 millisecond in duration.
  • floating gate 107 will be negatively charged by grounding injector diffusion 109 while applying a positive voltage of appropriate amplitude and pulse duration, using the information set forth in Fig. 11, to control gate 108.
  • the capacitive coupling between poly I level floating gate 107 and poly II level control gate 108 couples substantially all the positive potential of the control gate to floating gate 107.
  • a read operation of the nonvolatile cell by way of sense FET 102 is accomplished by grounding control gate 108 while sensing the conduction state through sense FET 102 by appropriately biasing source diffusion 104 and drain diffusion 106.
  • source diffusion 104 connected to ground and drain diffusion 106 connected to VQD
  • t i- 3 well known that numerous other means exist for sensing the conductive state of sense FET 102.
  • the V-QD voltage associated with diffusion 106 could be a precharge potential retained on the drain connection line by the intrinsic distributed capacitance of the line.
  • Equally possible is the connection of other transistors or like devices in series with sense FET 102 as a means by which to detect the conductive state of the FET.
  • Fig. 11 depicts the changes in threshold voltage of sense FET 102 with variations in the write/erase pulse amplitude and duration. Clearly, the longer the duration and the higher the amplitude, the greater the window created between the opposite binary states of the memory cell.
  • the excellent performance of the nonvolatile memory cell configured with a composite dielectric according to the present invention is clearly evident from the plots, particu- larly taking into account that the threshold voltage is measured at the relatively large 10 microamp con ⁇ duction level. It should be noted that these results are derived from tests on an embodiment in which the composite dielectric layers 116, 117 and 118 are pat- terned to be coextensive with poly I level floating gate 107.
  • Fig. 12 is for a 5 microamp current flow in sense FET 102 with a structural arrangement for memory cell 101 in which the composite dielectric is coextensive with the floating gate. It should be understood that the retention characteristics after 10 million write/erase cycles, as depicted in Fig. 12, is degraded from that originally exhibited by memory cell 101 with few 'write/erase cycles, in which case the decay was in the range of 0.1 volts per decade.
  • the memory cell to which this invention pertains can be fabricated in a number of different ways, as long as the composite dielectric region 107 (Figs.
  • the structure 7 and 9 provides a zone in which the electric field during writing and erasing is directed through the composite dielectric layers in a substantially orthagonal direction to the disposition of the layers between a source of charge and the floating gate.
  • the embodiments to which the various performance characteristics described hereinbefore pertain involved a structure in which the composite dielectric was coextensive with the floating gate.
  • the structure would take the form depicted in Fig. 9, where the composite dielectric is situated within a cut through a gate oxide layer 119. To create the structure depicted in Fig.
  • silicon substrate 111 would be subjected to normal processing until such time that gate oxide 119 of approximately 30-50 nanometers is formed at the loca ⁇ tion of sense FET 2 and over n + injector diffusion 109 at location 113. Thereafter, a photoresist mask would be patterned to expose the cut at region 124-124. Oxide etching would follow, until the upper surface of n + doped injector diffusion region 109 is exposed. Thereafter, a thin layer of silicon dioxide would be grown from region 109 by thermal oxidation in any one of numerous commonly known methods to form a oxide layer approximately 2 nanometers thick.
  • silicon nitride layer 117 would be formed by low pressure chemical vapor deposition, e.g., using silane and ammonia in a ratio of one part silane to 3.5 parts ammonia at a pressure of approximately 400-600 mtorr and temperature of approximately 750°C. According to the embodiment, silicon nitride layer 117 would be formed to a thickness of 10 to 20 nanometers. As noted earlier, the following layer,. 118, can be either silicon oxynitride or silicon dioxide.
  • the oxynitride could be chemical vapor deposited by using a mixture of silane, ammonia and nitrous oxide in the ratio of 1:2.5:2 at a nominally low pressure and a temperature of approxi ⁇ mately 750°C until the thickness of the oxynitride is in the range of 4-6 nanometers.
  • silicon dioxide is selected as the material for dielectric layer 118
  • the layer could be either conventionally chemical vapor deposited or thermally grown by oxida ⁇ tion of underlying nitride layer 117.
  • oxide layer 118 would also be slightly thicker than oxide layer 116.
  • oxide layer 116, nitride layer 117 and oxide or oxyni ⁇ tride layer 118 is preferably performed in a hot wall furnace tube which allows direct continuity of the fabrication cycle from the formation of oxide 116 through the formation of oxynitride 118 without exposing the device to the external ambients.
  • the composite dielectric at 113 is to be retained coexten- sively with poly I level floating gate 107, the doped polysilicon for floating gate 107 is deposited and after selective photoresist masking subjected to etchants which in sequence remove exposed polysilicon, oxide or oxynitride, and nitride.
  • etchants which in sequence remove exposed polysilicon, oxide or oxynitride, and nitride.
  • a photolithographic mask is situated over the region at 113 and the wafer is subjected to an etch removing oxynitride or oxide and nitride. Thereafter, the poly I level is deposited and patterned to form floating gate 107. Deposition of isolation oxide 114 and the deposition and patterning of the poly II- level control gate 108 follows in a manner commonly known to those routinely practicing in the art.
  • a composite dielectric which consists of a very thin oxide layer covered by a relatively thicker nitride layer and further covered by a thin oxide or oxynitride layer, where the last layer is thicker than the first-named oxide layer and is immediately adjacent the floating gate, provides a semiconductor dielectric configuration which is be ⁇ lieved to have unique attributes.
  • the composite structure exhibits exceptional endurance, is programmable with relatively low voltages and pulse durations, and exhibits uncycled retention characteristics comparable to those of other floating gate devices.
  • the properties of the structure are due to the combination of the nitride layer sandwiched by the two thin oxide based layers. At low or zero control gate bias, the oxide films prevent charge flow from or to the floating gate.
  • the oxide films prevent charge flow from or to the floating gate.
  • the energy barriers of the oxides is lowered, initiating Fowler-Nordheim tunneling through both oxides and Poole-Frenkel conduction through the nitride to charge or discharge the floating gate. Conduction in the nitride is limited by the nitride traps density. This limitation in the flow rate or charge transport by the nitride traps aids in minimiz ⁇ ing the damage that would occur if only an oxide film were used as the sole dielectric for charge transport.
  • Oxynitride or oxide composed dielectric layer 118 is slightly thicker than thermally grown oxide layer 116 to offset the effects of asperities created by deposited polysilicon floating gate layer 107.

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Abstract

Un dispositif de mémoire rémanente du type à porte flottante comprend une zone conductrice de substrat (13) séparée d'une porte flottante (17) par un diélectrique composé d'une couche (19, 22) de nitrure de silicium ou d'oxynitrure de silicium dans laquelle se produit une conduction de Poole-Frenkel. Dans un autre mode de réalisation, une couche (21) très fine de dioxyde de silicium est formée entre le substrat de la couche (19, 22) de nitrure de silicium ou d'oxynitrure de silicium. Dans un autre mode de réalisation, une deuxième couche (118) de dioxyde de silicium ou d'oxynitrure de silicium est placée entre la porte flottante (107) et la couche (117) de nitrure de silicium. Des inscriptions peuvent être effectuées ou effacées dans ces dispositifs à porte flottante avec des impulsions de tension d'amplitude relativement faible et de courte durée, ces dispositifs présentant toutefois d'excellentes caractéristiques de résistance et de rétention.
PCT/US1986/000372 1985-03-08 1986-02-24 Dispositif de memoire remanente a porte flottante a effet de champ WO1986005323A1 (fr)

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US70963085A 1985-03-08 1985-03-08
US709,630 1985-03-08
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Cited By (7)

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Publication number Priority date Publication date Assignee Title
US4935648A (en) * 1988-06-15 1990-06-19 Advance Micro Devices, Inc. Optimized E2 pal cell for minimum read disturb
US5005155A (en) * 1988-06-15 1991-04-02 Advanced Micro Devices, Inc. Optimized electrically erasable PLA cell for minimum read disturb
US5101378A (en) * 1988-06-15 1992-03-31 Advanced Micro Devices, Inc. Optimized electrically erasable cell for minimum read disturb and associated method of sensing
US5397720A (en) * 1994-01-07 1995-03-14 The Regents Of The University Of Texas System Method of making MOS transistor having improved oxynitride dielectric
US5478765A (en) * 1994-05-04 1995-12-26 Regents Of The University Of Texas System Method of making an ultra thin dielectric for electronic devices
US5739569A (en) * 1991-05-15 1998-04-14 Texas Instruments Incorporated Non-volatile memory cell with oxide and nitride tunneling layers
US8040728B2 (en) 2008-06-12 2011-10-18 Seiko Epson Corporation Semiconductor integrated circuit

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US4037242A (en) * 1975-12-29 1977-07-19 Texas Instruments Incorporated Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device
WO1983002199A1 (fr) * 1981-12-14 1983-06-23 Ncr Co Dispositif de memoire non-volatile a semiconducteur et son procede de fabrication
EP0085551A2 (fr) * 1982-01-29 1983-08-10 Seeq Technology, Incorporated Procédé de fabrication d'une matrice de mémoires du type MOS comprenant des éléments de stockage électriquement programmables et électriquement effaçables
GB2129611A (en) * 1982-09-24 1984-05-16 Hitachi Ltd A nonvolatile memory

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US4037242A (en) * 1975-12-29 1977-07-19 Texas Instruments Incorporated Dual injector, floating gate MOS electrically alterable, non-volatile semiconductor memory device
WO1983002199A1 (fr) * 1981-12-14 1983-06-23 Ncr Co Dispositif de memoire non-volatile a semiconducteur et son procede de fabrication
EP0085551A2 (fr) * 1982-01-29 1983-08-10 Seeq Technology, Incorporated Procédé de fabrication d'une matrice de mémoires du type MOS comprenant des éléments de stockage électriquement programmables et électriquement effaçables
GB2129611A (en) * 1982-09-24 1984-05-16 Hitachi Ltd A nonvolatile memory

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Journal of Applied Physics, Volume 44, No. 5, May 1973, New York, (US) H.C. CARD et al.: "Reversible Floating gate Memory", pages 2326-2330, see page 2326, left-hand column, paragraph 3; right-hand column paragraph 3; page 2329, "Conclusions"; figure 1 *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4935648A (en) * 1988-06-15 1990-06-19 Advance Micro Devices, Inc. Optimized E2 pal cell for minimum read disturb
US5005155A (en) * 1988-06-15 1991-04-02 Advanced Micro Devices, Inc. Optimized electrically erasable PLA cell for minimum read disturb
US5101378A (en) * 1988-06-15 1992-03-31 Advanced Micro Devices, Inc. Optimized electrically erasable cell for minimum read disturb and associated method of sensing
US5739569A (en) * 1991-05-15 1998-04-14 Texas Instruments Incorporated Non-volatile memory cell with oxide and nitride tunneling layers
US5397720A (en) * 1994-01-07 1995-03-14 The Regents Of The University Of Texas System Method of making MOS transistor having improved oxynitride dielectric
US5541436A (en) * 1994-01-07 1996-07-30 The Regents Of The University Of Texas System MOS transistor having improved oxynitride dielectric
US5478765A (en) * 1994-05-04 1995-12-26 Regents Of The University Of Texas System Method of making an ultra thin dielectric for electronic devices
US8040728B2 (en) 2008-06-12 2011-10-18 Seiko Epson Corporation Semiconductor integrated circuit

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