WO1986002216A1

WO1986002216A1 - Counter apparatus

Info

Publication number: WO1986002216A1
Application number: PCT/JP1984/000475
Authority: WO
Inventors: Yuichi Goto
Original assignee: Koyo Denshi Kogyo Kabushiki Kaisha
Priority date: 1984-10-08
Filing date: 1984-10-08
Publication date: 1986-04-10
Also published as: JPH0744444B1

Abstract

A counter apparatus which counts the number of pulse signals and outputs on ON/OFF state previously stored at an address corresponding to the count thereof. When a signal corresponding to a set mode is output from a mode changeover device (18), an ON/OFF state set by an output state setting device (20) is stored at an address in an output state storing memory (21) which is represented by the contents of an addition-subtraction counter (16). When a signal corresponding to an operating mode is output from the mode changeover device (18), an ON/OFF state stored at an address in the output state storing memory (21) represented by the contents of an addition-subtraction counter (8) which counts the number of pulse signals is output to an output circuit (22). A pulse signal is output, together with an up/down signal, from either a phase difference signal input circuit (4) or an addition-subtraction signal input circuit (6), and either the pulse or up/down signal is selected by a pulse selector (5). Further, the addition-subtraction counter (8) effects a periodic counting operation regardless of the direction of the counting mode, that is, whether it is addition or subtraction.

Description

Specification

Counter device

Technical field

The present invention relates to a multi-stage setting type power center device, and more specifically, counts pulse signals output from encoders and the like according to a rotation angle and a moving distance of a shaft, and the like. Power control device that outputs a control signal when a preset numerical value is reached Background technology

Conventionally, this type of power center device has been configured using a cam switch, a limit switch, and the like, so that the overall configuration is complicated and large. It was something. In addition, the counting speed and output response speed are slow, and there is a limit in accuracy.In addition, when changing processes, handling is troublesome, such as exchanging force switches. Disclosure of inventions that had various problems

An object of the present invention is to solve the above-mentioned problem. An on / off state to be output to an output circuit is previously stored in an output state storage means, and the output state storage means is stored by a counter. High-speed output response is possible by adopting a method of sequentially specifying and outputting the contents, and high-speed counting operation is enabled by having a hardware-based counter. A power counter means for performing a counting operation is provided to enable period control, and a phase difference signal is input to a counting signal input circuit.

O PI- There is also provided a counter device provided with input circuit means capable of performing a counting operation with any of the signals, addition and subtraction signals.

Therefore, in the present invention, based on the setting mode of the mode switching means, a predetermined error of the output state storage means corresponding to the count value of the address counter means is transmitted from the output state setting means to the predetermined error. The output on / off state is stored, and a predetermined error of the output state storage means corresponding to the count value of the counter means based on the operation mode of the mode switching means. One stored from. Read off-state and output to output circuit.

Further, in the present invention, an up-Z down signal is output which counts signals having different phases as count signals, and outputs whether the count signal should be counted up or down. A phase difference signal input circuit, an addition / subtraction circuit that counts addition and / or subtraction signals and outputs an up / down signal indicating whether the counted signal should be counted in the addition direction or the subtraction direction. Selects the signal input circuit and the phase difference signal input circuit or the counting signal output from the addition / subtraction signal input circuit to which the counting signal from the circuit should be added or subtracted. It is connected to the counter means via a pulse selector as a counting method selection means for outputting the data.

Further, in the present invention, an addition / subtraction counter is used as counter means for counting signals from the detector, and the number of pulse signals is added and counted according to the up / down signal. Or subtraction counting

CMF ■ I By doing so, if the count value becomes equal to the cycle set value in the case of incremental counting, the count value is reset to 0, and whether the count value is in the subtraction direction by subtraction counting. When the signal has passed through the cycle, that is, when the count value is… 3, 2, 1, 0, and then a signal to be further subtracted is input, (period value n — 1) is written to the counter means. Perform the period counting operation so that

Thus, a counter having a hard configuration is provided in the counting section, so that a high-speed counting operation is possible, and the counter is turned on in advance by the bracket counter. By specifying the address of the output state storage memory where the off state is stored], high-speed response of the output can be realized.

In addition, in the present invention, a counter means for performing a period counting operation is provided.] 9 It is also necessary to provide an external terminal and to input a signal indicating the period position from the outside. Also, there is no need for an arithmetic circuit for calculating the operation value of the subtraction count and a memory circuit for storing the value, and although the circuit configuration is simple, Accurate period counting operation can be performed.

Furthermore, by providing a two-phase signal input circuit, an addition / subtraction signal input circuit, and a counting method selection means, it is possible to perform a counting process for any of the jP two-phase signal and the addition / subtraction signal. ] 9, Detection devices that can be used as an external clock input are not limited, and many types of detection devices can be connected.

BRIEF DESCRIPTION OF THE DRAWINGS

OVFI FIG. 1 is a block circuit diagram of a power counter device according to the present invention, and FIGS. 2 and 3 are two-phase signals and addition / subtraction signals input to the power counter device according to the present invention. FIGS. 4 and 5 are timing charts of addition and subtraction by the addition / subtraction counter of the counter device according to the present invention, and FIGS. FIG. 3 is a diagram showing the storage contents of the output state storage memory of FIG.

1, 2, 3… Terminal, 4… Phase difference signal input circuit, 5… Pulse selector,…… Addition / subtraction signal input circuit, 7, 9… AND circuit, 8, 1…… Cover subtraction counter , 10… Setter, 11… On-delay circuit, 12… Differential circuit, 13… Τ0 Τ circuit, 14… Comparison circuit, 15… Selector, 17… Pulse generation circuit, 18 ... mode switcher, 19 ... control bus, 20 ... output state setting device, 21 ... output state memory, 22 ... output Circuit, 23 ... Address bus, 24, 2… Drive circuit, 27… 7-segment type numeric display, 28… Output form, 出力 1

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block circuit diagram of a counter device according to the present invention. In FIG. 1, terminals 1 and 2 are connected to the terminals 1 and 2, for example, an encoder (not shown) serving as a pulse signal generating means. Or 5th A phase signal from input signal A and input signal B or an addition / subtraction signal from an addition signal and a subtraction signal shown in the figure is input.Terminal 5 is a phase signal that is input to terminals 1 and 2. Or 9) a signal for selecting either the phase difference signal input circuit 4 or the addition / subtraction signal input circuit. Phase difference signal input circuit 4 is a terminal

When the input signal A as shown in Fig. 2 (a) and the input signal B 90 degrees behind the input signal A as shown in Fig. A pulse signal CP (counting signal) corresponding to the rotation angle of the encoder is output to a pulse selector (counting method selection means) 5, and the number of the pulse signals CP should be added and counted. The up / down signal UDP indicating “1” is set to “1” and output to the pulse selector (pulse selection means) 5. The phase difference signal input circuit 4 receives an input signal A as shown in FIG. 2 (b) and an input signal B which is 90 degrees ahead of the input signal A. Output the pulse-signal CP to the pulse selector (pulse selection means) 5 and indicate that the number of the pulse signals CP should be subtracted and counted. The down signal UDP is set to '' 0 'and output to the pulse selector (pulse selection means) 5. Here, the input signal A is also the input signal B]? The case where input signal A is input signal B and the case where input signal A is also delayed is regarded as subtraction counting.However, in some cases, the definitions of addition counting and subtraction counting are reversed. Is also good.

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When the addition signal and the subtraction signal as shown in FIG. 3 (a) are input, the addition / subtraction signal input circuit を outputs the pulse signal CP to the pulse selector (pulse selector). Means to output to 5 and the pulse signal. The up / down signal UDP indicating that the number of CPs should be added and counted is set to "1", and the pulse is selected. (Pulse selection means) 5 When the addition signal and the subtraction signal are input as shown in Fig. 5 (b), the pulse signal CP is output to the pulse selector (pulse selection means) 5. Further, the pulse Z down signal UDP indicating that the number of the pulse signals CP should be subtracted and counted is set to "0", and a pulse selector (pulse selecting means) Output to 5. According to the signal input to the terminal 3, the pulse selector 5 outputs the pulse signal c P and the up-Z down signal .UDP or the addition / subtraction signal input circuit which are output from the two-phase signal input circuit 4. Pulse signal CΡ and the up / down signal UDP that are output from the controller, and the selected pulse signal CΡ is added to and subtracted from the selected pulse signal CΡ via an AND circuit 7. Adds or subtracts the selected up / down signal UDP to the clock pulse and input terminal CT of the C counter means), and inputs the up / down signal of the counter 8 to the counter Z Input to the reset terminal R of the addition / subtraction counter 8 via the terminal 端子 t) and the AND circuit 9 respectively. The addition / subtraction counter 8 is a counter for counting the count signal from the input circuit.

Next, the addition / subtraction counter 8 adds and counts the number of pulse signals CP when the up Z down signal UDP is "1", and

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When the Z-down signal UDP is "0", the number of the pulse signals CP is subtracted and counted, and the count value is output.]), And the count value C is set in the setting unit 1 by the addition count. When the count value C becomes equal to the cycle set value n set at 0, the count value C is reset to 0, and when the count value is reduced, the count value C is set when the count value C passes the cycle. The set value n of the unit 10 is set, and the value n — 1 obtained by subtracting 1 from the set value is set.

FIG. 4 is a timing chart of the addition and counting of the addition / subtraction counter 8. First, when the count value C is 0 or more, the addition / subtraction counter 8 is "0" without output from the minus output terminal SGN. This signal is input to the AND circuit 7 via the on-lay circuit 11, the differentiator circuit 12, and the NOT circuit 15 (see FIG. 4 (b)). The AND circuit 7 takes the AND condition between the input pulse CP and the state of the above-mentioned minus output terminal SGN, but usually the minus output terminal of the addition / subtraction counter 8. Since the state of the SGN signal is "0", the output of the NOT circuit 15 is "1"]), and therefore, the pulse signal CP passes through the AND circuit 7 to the pulse signal input terminal CT. It is applied as it is (see Fig. 4 (c)). On the other hand, since the up-down signal UDP "1" is added to the up-down terminal U / t of the addition / subtraction counter 8, the addition / subtraction counter 8 is a pulse signal. When CP is input, it is added and counted, and the count C is output from the count output terminal CNT to the comparison circuit 14 and the selector 15 (see FIG. 4 (d)). 8

In here, the time t _a count value C is the Do that rather then like the set value n that is set by the setting device 1 0, is output match output "1" to the comparison circuit 1 4 or al AND circuit 9, AND In the circuit 9, the up / down signal UDP "1" and the match condition of the match output "Ί" are set, and the reset signal R is added to the reset terminal R of the addition / subtraction counter 8 " Since 1 "is added (see Fig. 4 (e)), the addition / subtraction counter

The count value C of 8 will be reset to 0 (see Fig. 4 (f)). FIG. 5 is a timing chart of the subtraction count of the addition / subtraction counter 8. First, since the output of the minus output terminal SGN of the addition / subtraction counter 8 is “0” (see FIG. 5 (a)), the minus output “Ί” is output to the AND circuit 7. (Refer to Fig. 5 (b).) On the other hand, the up-down terminal UZD of the addition / subtraction counter 8 has an up-down signal "UDP" indicating that a down-count should be performed. When the pulse signal CP is input (see Fig. 5 (e)), the addition / subtraction counter 8 subtracts the number of pulse signals CP and outputs the count value C to the count output terminal. Output from CNT (See Fig. 5 (d).) Then, the addition / subtraction counter 8 subtracts and counts, and the count value becomes 3, 2, 1, 1, 0! If the signal CP is applied, i.e. the count value at time t _b is output set value write command signals and that one 1 from microstrip Na scan output terminal SGN, set Nesho Input to the command terminal LD, so that the count value of the addition / subtraction counter 8 is set to the cycle set value n from the setting device 10 input to the set value input terminal SET (No. 5 WI O (See Figure (d)). When the set value n is set, the minus output terminal SGN becomes "0" (see Fig. 5 (a)). At the same time, the signal from the minus output terminal SGN is input to the on-lay circuit 11, and the output power of the on-lay circuit 11 is differentiated with a certain time delay. A signal is sent to circuit 12. This signal is input to the differentiating circuit 12 and differentiated and input to the NOT circuit 13. The output of the NOT circuit 1 S is inverted by the differentiation time, that is, set to “0”. Therefore, the pulse signal input terminal CT of the addition / subtraction counter 8 is forcibly applied to the ONLY circuit 11, the differentiating circuit 12, and the NOT circuit 13). The same as when the signal was input to the input terminal CT, and the pulse was forcibly input to the addition / subtraction counter 8 after the time t _{c and} before the next pulse signal CP was input. (See Fig. 5 (c)), the count value C is n-1 (see Fig. 5 (d)). As a result, n is set as the count value of the addition / subtraction counter 8, and Since the pulse signal is forcibly applied to the power counter by one pulse before the pulse signal is input, the count value C eventually becomes'. Perform the period counting operation of counting 3, 2, 1, 0, η — 1, η — 2,…. As described above, the obtained count value of the addition / subtraction counter 8 is output to the selector 15. Next, the pulse generation circuit 17 is operated by the operation of the button 17a and the button 17b to send the subtraction direction setting value. The counter 1 を outputs the pulse signal from the pulse generation circuit 17 ゝ.

OMPI, A signal indicating whether to count in the subtraction direction or the addition direction is output. Based on this signal, the address counter 1 1 adds or subtracts the pulse signal C の from the pulse generation circuit 17 and counts the result, and outputs the counted value to the selector 1. Output to 5 c, address counter 1 ό is a counter indicating the address of the output state storage memory 21 described later.

Next, the mode switching device (mode switching means) 18 has at least means (not shown) for selecting either the setting mode or the operation mode. A mode signal corresponding to the set mode is supplied to a selector 15, an output state setting unit (output state setting means) 20, which will be described later, via a control bus 19, Output state storage memory (output state storage means) 21 and output to output circuit 22 to control these appropriately.

If the mode switcher 18 has a setting mode and a readout mode is set to the operation mode, the output status storage memory specified by the addition / subtraction counter 16 is used. Re 2 The stored contents can be viewed in the blinking state of the output status indicator 28 via the drive circuit 2, which will be described later, so that the stored contents can be easily confirmed.

When a mode signal corresponding to the setting mode is output from the mode selector 18, the selector 15 is an adder / subtractor (adjustment counter). 1) Select the count value output from the output, and when the mode signal corresponding to the operation mode is output, select the count value output from the addition / subtraction counter 8. The

The selected count value is output via the address bus 23 to the output state storage memory 27 and a drive circuit 24 composed of, for example, an amplifier and a driver. The drive circuit 24 switches the count value from the counter means 8 or the set value from the address counter 1 by the selector 15. The 7-segment type numeric display 27 can be displayed according to the mode.

Next, the output state setting unit 20 stores eight ON states or eight states in the areas of the output state storage memory 21 designated by the respective count values of the addition / subtraction counter 10. There is a means to set the off state, and only when the mode signal corresponding to the setting mode is output from the mode switch 18, the set 8 ON states The off state is parallelized to the output state storage memory 21 via the data bus 25 and to the drive circuit 20 composed of the BCD converter and the display driver. Output to. In the setting mode, the driving circuit 2ό sets the on / off state set by the output state setting unit 20 and stored in the output state storage memory 2, and the operation mode. At this time, the on / off state read from the output state storage memory 21 and output to the output circuit is displayed on the output state indicator 28.

Next, the output state storage memory 21 is a RAM having a storage capacity of m bytes corresponding to the maximum value m that can be counted by the addition / subtraction counter 1]], and the addition / subtraction counter 1 ό The address from address 0 to m — 1 corresponding to each count value of 1 to 1 is- In this embodiment, the storage area of each address has an 8-bit configuration. This output state storage memory 21 is used when the mode signal corresponding to the set mode is output from the mode switch 18, and the addition / subtraction power is output from the counter 1 output. The count value input through the selector 15 and the address bus 23, that is, the address indicated by the addition / subtraction counter 1 ό, is output from the output status setting unit 20 to the address indicated by the addition / subtraction counter 1 ό. The ON state or OFF state input via Tab 25 is written and stored. Also, the mode signal corresponding to the operation mode is transmitted to the mode switch.

18 When output from 8, the count value input from the addition / subtraction counter 8, that is, the add-subtraction force is indicated by the counter 8. The ON state stored from the address Alternatively, the off state is read, and this is output to the output circuit 22 and the drive circuit 2 via the data bus 25. As shown in FIG. 5, the ON state or the OFF state is stored in correspondence with the ON state of "1" and the OFF state of "0". In addition, the number of ON states or OFF states is not limited to eight for one address, but may be set to a desired number by increasing the output state storage memory 21. No.

Next, the output circuit 22 is read out from the output state storage memory 21 only when the mode signal corresponding to the operation mode is output from the mode switch 18. Eight on-states or off-states are paralleled to output terminals 22a, 22b, 22c, 22d22e, 22i, 22g and 22h. Output

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The 7-segment type numeric display 27 is driven by the drive circuit 24, and the mode corresponding to the setting mode from the mode switch 18 The count value output from the addition / subtraction counter 10 when a signal is output, or the addition / subtraction counter when a mode signal corresponding to the operation mode is output. Displays the count value output from the data 8, that is, the address at which the output status storage memory 21 is accessed ο

The output status indicator 28 is driven by the drive circuit 20. When the mode is switched off, when the mode signal corresponding to the set mode is output from 18 the output status indicator 28 is output. Displays the ON state or OFF state that is set by the setting unit 20 and is stored in the address of the output state storage memory 21 indicated by the addition / subtraction counter 1 ό. When a mode signal corresponding to the operation mode is output from the mode switch 18, the key of the output state storage memory 21 indicated by the addition / subtraction counter 8 is used. It indicates the ON state or OFF state read from the dress! ? The ON state corresponds to lighting of, for example, the light emitting diode 28L as a display, and the OFF state corresponds to turning off of the light emitting diode 28L, for example, as a display.

Next, the overall operation of the counter device according to the present invention will be described. First, the operation of the mode switcher 18]? When the setting mode is selected, the count value of the addition / subtraction counter 1 、 That is, the on-state or off-state set by the output state setting unit 20 is set in the address of the output state memory 21 designated by the addition / subtraction counter 1 ό. Will be remembered. For example, assuming that the set value of the addition / subtraction counter 1 で is 0, the on state and the off state are “0” and “0” at address 0 of the output state storage memory 21, respectively. "," 1 "," 1 "," 0 "," 0 "," 0 "," 0 "are stored (see Fig. 5). Similarly, the on / off state is stored at address m-1 from address 1 corresponding to the counting range as shown in FIG.

Next, when the operation mode is selected by operating the mode switch 18, the count value of the addition / subtraction force counter 8, that is, the output specified by the calorie subtraction counter 8 is selected. The ON state and the OFF state are read from the address force of the state storage memory 21. For example, assuming that the count value of the addition / subtraction force counter 8 is 2, the output state is as follows: address 2, address 2 of memory 21; ^ on, off

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Τ, Τ, and "0" are output from the output terminals 22 a to 22 h of the output circuit 22 to the printer. Similarly, in accordance with a change in the count value of the addition / subtraction force counter 8, the contents of the output state storage memory 21 of the address indicated by the count value are sequentially read, and the output circuit 22] ? It is output.

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Claims

The scope of the claims

(1) An input circuit for inputting a count signal from the detector, a counter means for counting the count signal from the input circuit and outputting the count value, or a pulse signal generating means for the other hand A pulse for counting the pulses output from the memory and storing the counted value in a predetermined area of the output state storage means to store the ON state or the OFF state to be output to the output means. It has address counter means for outputting as a signal, and at least an operation mode and a setting mode, and selects and outputs one of those modes. Mode switching means to be activated, and either of the counter means or the address counter means is selected based on a mode signal from the mode switching means. Selector means for selecting whether or not to output the data, and the address card based on the setting mode. J? The output state setting means for pre-writing the on / off state of the signal to be output in a predetermined area of the output state storage means specified by the data output means, and the output state setting means] 9 Turns on the written output circuit. An off state is stored. A predetermined address of the state storage means corresponding to the count value of the counter means based on the operation mode of the mode switching means and the output state storage means. ON of the output stored in the error corresponding to. A counter device having an output circuit for outputting an off state.

(2) An input circuit that inputs and outputs a counting signal from the detector and outputs an addition or subtraction command signal. Of the input circuit of the addition or subtraction count command signal Based on counting ^signal: ^ addition or counts subtracted and sent to the comparison means also when sends the count value to the Selector Address means At the time of addition counting, when the count value and the set value satisfy a predetermined condition, the count value and the set value are transmitted as a reset signal to the power counter circuit. A circuit that sets the set value of the setting device to the counter when the set conditions are met, and forcibly applies a count signal to the counter circuit based on the matching status almost simultaneously. The pulses output from the counter means for performing the cyclic operation and the pulse signal generating means are counted, and the counted value is stored in a predetermined area of the output state storage means. Address signal for storing the ON state or OFF state to be output to the output means. Mode, which has an address counter means for output as a signal, and at least an operation mode and a setting mode, and selects and outputs one of those modes. Means for selecting either the counter means or the address counter means based on the mode signal of the mode switching means and the mode switching means. On / off of a signal output from an output circuit to a predetermined means of the output state storage means designated by the address counter based on the setting mode. The output state setting means for preliminarily storing the state; and the on / off state of the written predetermined output circuit is stored. Power center means based on the operation mode of the mode switching means

"¾υ —4 Characterized by having an output circuit for outputting an on / off state of an output stored in an area corresponding to a predetermined address of the state storage means corresponding to the count value. Counter equipment

(3) counting method selecting means for selecting any one of the counting signal of the detector based on whether the counting signal is a phase difference signal or an addition or subtraction signal; and A phase difference signal input circuit for transmitting a counting signal and an up / down signal for specifying whether to count up or down the signal, and when the counting signal is an addition / subtraction signal. Is an addition / subtraction signal input circuit that sends out count signals and up Z down signals! ) Input circuit means, a counting means for counting the count signal from the input circuit and outputting the count value, and a pulse signal output means for counting the pulses output from the pulse signal generating means. The count value is output to a predetermined area of the output state storage means as an address signal for storing the ON state or the OFF state to be output to the output means. A mode switching means for selecting at least one of the modes and outputting the selected mode; and a mode switching means having at least an operation mode and a setting mode. A selector for selecting which mode of the counter means or the address counter means to select and output based on the mode signal of the mode switching means. And an output state specified by the address counter based on the setting mode. Output circuit at a predetermined E Li § of 憶 means ) Output state setting means for pre-writing the on / off state of the signal to be output, and on to the specified output circuit written by the output state setting means. An output state storage means for storing an off state, and a predetermined address of the state storage means corresponding to the count value of the power center means based on the operation mode of the mode switching means. The output power stored in the error corresponding to the lesson. A counter device having an output circuit for outputting an off state.