Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F71/00—Manufacture or treatment of devices covered by this subclass
  • H10F71/121—The active layers comprising only Group IV materials
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F10/00—Individual photovoltaic cells, e.g. solar cells
  • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
  • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
  • H10F77/00—Constructional details of devices covered by this subclass
  • H10F77/20—Electrodes
  • H10F77/206—Electrodes for devices having potential barriers
  • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/547—Monocrystalline silicon PV cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• This invention pertains to the manufacture of photovoltaic cells and more particularly to an improved low-cost method of fabricating polycrystalline silicon solar cells wherein the damaged surface layer generated during hydrogen passi ⁇ vation is used as a plating mask, for the metallization of the front surface electrodes.
• a common method of fabricating silicon solar cells has included the steps of forming a PN junction by diffusing a suitable dopant into the front side of a silicon wafer or ribbon, etching a grid electrode pattern in a protective dielectric masking layer formed on that front surface, depositing a nickel plating on all silicon exposed by the etching, overplating the nickel with copper and tin, removing the remainder of the dielectric masking layer from the front surface, and providing an anti-reflection coating on the newly exposed portions of the front surface.
• the efficien ⁇ cies achieved with polycrystalline silicon solar cells are generally poorer than those of monocrystalline cells. This circumstance has been improved upon by introducing a monovalent element, such as hydrogen, into the structure to combine with the dangling bonds associated with the structural defects, thereby- minimizing the minority carrier recombination loss.
• a monovalent element such as hydrogen
• any "positive" plating mask used to define the front surface grid electrode pattern by covering the inter- electrode area of the front surface should not be in place during passivation.
• the altered surface layer produced in hydrogen ion beam passivation may be used as a plating mask for subsequent metallization steps involving immersion plating of a selected metal.
• 563061 as applied to the manufacture of silicon solar cells involves, inter alia, the following steps: (1) forming a plating mask of a dielectric material on- the front surface of a shallow-junction silicon ribbon so as to leave exposed those areas of the silicon to be later covered by the front surface electrode, (2) depositing a thin layer of nickel (or similar material) on the exposed sili ⁇ con, (3) removing the plating mask, (4) hydrogen passivating the junction side of the cell, (5) sin ⁇ tering the nickel to form in part a nickel suicide, (6) immersion plating additional nickel onto the metal-covered portions of the cell, (7) electroplating a layer of copper onto the nickel, and (8) applying an anti-reflection coating over the exposed surface of the silicon.
• the sili ⁇ con may be further processed, e.g. to prepare it for connection to electrical circuits.
• the heating of the sample during passivation supplies at least part of the energy for the nickel sintering step. While it will be appreciated that such a procedure (1) permits the removal of the initial plating mask prior to passivation (permitting better passivation) and (2) allows passivation prior to the application of base metals without the requirement of an additional masking step prior to metallization (both eliminating the danger of spoiled cells caused by migration of the base metal during passivation and simplifying the pro ⁇ duction process by eliminating the need either for close thermal control.of the substrate during passiva ⁇ tion or for a photolithographic step following passi ⁇ vation) , the process may still be improved.
• the method just outlined requires the formation of a plating mask, as an additional layer on the substrate, prior to the initial metallization, and to this extent requires additional processing and materials.
• a process which, in a preferred embodiment as applied to the manufacture of silicon solar cells involves, inter alia, the following steps: (1) diffusing phosphorus into P-type silicon ribbon so as to form a shallow junction, the diffusion process simultaneously forming a layer of phosphosilicate glass on the surface of the ribbon adjacent the junction, (2) forming a grid electrode pattern of the phosphosilicate glass layer by photolithography (using a suitable photoresist composition and etching) in the form of a "negative" plating mask (i.e., leaving phosphosilicate glass only on those regions of the substrate where it is desired to subsequently attach the front surface electrodes) , (3) coating the other side of the silicon ribbon with an aluminum paste, (4) heating the silicon so as to alloy the aluminum, (5) hydrogen passivating the junction side of the cell while simultaneously forming an altered layer in the uncovered silicon substrate between the phosphosilicate glass electrode pattern, (6) etching off the remaining phophosilicate glass, and (7) metallizing both the non-
• immersion plating means a process wherein an object is plated with a metal without the use of an externally applied electric field by immersing that object in a plating bath that does not contain a reducing agent, and the plating involves a displacement reaction. Immersion plating is distinguished from electroless plating in that the latter involves a plating bath that contains a reducing agent.
• This fabrication sequence has several key advantages. By delaying the deposition of the front surface electrodes until after passivation, all danger of the cell's being spoiled by migration of the electrode's material to the junction during subsequent processing steps is greatly reduced. As thermal control during passivation is less critical, heat sinking may be avoided. Therefore, the present pro ⁇ cess permits high throughput ion beam passivation. Additionally, the preferred method, by making use of the glass layer formed as a consequence of the method of forming the junction as the body of a negative - a -
• plating mask eliminates both an etching step (to ini ⁇ tially remove the glass) and a coating step (to pro ⁇ vide material for a plating mask) , the glass instead being removed in two stages.
• the preferred embo ⁇ diment of the invention relates to the production of solar cells from EFG grown P-type silicon ribbon.
• one side hereafter the "front side"
• a phosphorus dif ⁇ fusion process calculated to produce a relatively shallow junction 4 (i.e., a junction of between about 3,000 and about 7,000 Angstrom units deep)
• an N-type conductivity region 6 and a reasonably thick (e.g., on the order of at least 1500 Angstrom units) layer of phosphosilicate glass 8.
• a silicon ribbon of P-type conductivity made by the edge-defined film-fed growth (EFG) process and having a resistivity of about 5 ohm-cm is cleaned by etching in a solution of HNO3(70%) :HF(49%) in a ratio of between about 4:1 and 9:1 for about one to three minutes at about 25 * C. Thereafter, the ribbon is subjected to phosphorus dif ⁇ fusion in an oxygen-rich atmosphere.
• silicon and oxygen react to form silicon dioxide
• phosphorus and oxygen react to form phos phorus pentoxide
• phosphorus pentoxide and silicon oxide react to form a phosphosilicate glass
• phosphorus pentoxide and silicon react to form phosphorus and silicon dixode.
• a phosphosilicate glass formed as detailed ' in U.S. Patent 4,152,824, may be used as the source for the phosphorus.
• the next step involves coating the front side of - mo ⁇
• the resist may be applied in a suitable manner, e.g., as by spraying, and then baked to drive off the organic solvents & ⁇ d cause the resist to adhere firmly to the phosphosilicate glass.
• this baking is achieved by heating the photoresist to between about 80 * C and 110 * C for between about 35 and about 60 minutes.
• the photoresist layer is then covered with a nega ⁇ tive mask in the pattern of a multi-fingered grid electrode, e.g., a mask having transparent areas corresponding to the fingers of the desired electrode and opaque elsewhere.
• a nega ⁇ tive mask in the pattern of a multi-fingered grid electrode, e.g., a mask having transparent areas corresponding to the fingers of the desired electrode and opaque elsewhere.
• a suitable electrode pattern reference may be had to U.S. Patent 3,686,036.
• the grid mask is then irradiated with ultraviolet light of a sufficient intensity and for sufficient time so as to cause the illuminated portion of the photoresist to polymerize.
• the photore ⁇ sist is developed by treatment with one or more suitable developing agents, as for instance by contact with toluene and propanol or other suitable solvents.
• the assembly is subjected to a buffered oxide etch consisting, e.g., of a solu ⁇ tion of HF and NH4F, whereby the exposed layer of phosphosilicate glass 8 is removed.
• a buffered oxide etch consisting, e.g., of a solu ⁇ tion of HF and NH4F, whereby the exposed layer of phosphosilicate glass 8 is removed.
• (P2O5) x (Si ⁇ 2)y a phosphosilicate glass
• 10NH4F(40%) :1HF at a temperature of about 25*C for a period between about 15 seconds and 2 minutes. This leaves intact a layer 12 of phosphosilicate glass, in the pattern of the grid-electrode configuration, under the polymerized, unremoved portion 10A of the photo ⁇ resist.
• the aluminum paste used to form layer 14 preferably comprises alu ⁇ minum powder in a volatile organic vehicle, such as terpineol, that can be removed by evaporation.
• This step is then followed by an alloying step in which the substrate is heated for about 0.25 to 2.0 minutes to a temperature greater than 575* to remove any volatile or pyrolyzable organic components of the paste and to alloy the aluminum.! in the paste to the silicon substrate.
• the aluminum coating 14 alloys with the back side of the substrate to provide - a P + region 16 having a depth of from about 1 to about . 5 microns.
• the alloying step also serves to remove the remaining resist portion 10A by pyrolysis. -f Z-
• a pre ⁇ ferred method is to expose the front surface of substrate 2 to the hydrogen ion beam of a Kaufman-type (broad beam) ion source situated about 15 cm from the substrate.
• This ion source is preferably operated at a pressure of between about 20 and 50 millitorr (of hydrogen) , with a hydrogen flow rate on the order of about 25 to 40 s.c.c. per minute, with a potential of about 1700 volts d.c. between source and substrate, and with a beam current of between about 1 and 3 miHiampere/cm 2 at the substrate.
• An exposure time of between about 1 and about 4 minutes has been found adequate both to minimize the minority carrier recom bination losses typically experienced with EFG-type silicon cells (providing a passivation zone some 20 to 80 microns deep, or about 100 times as deep as junc ⁇ tion 4) while simultaneously providing an altered surface layer 18 approximately 200 Angstrom units deep on the exposed portions of substrate 2.
• altered surface layer 18 is not known. However, it is believed to be a damaged zone wherein the crystal structure has been somewhat disrupted, the silicon in part forming SiH or SiH2 with hydrogen from the ion beam, yet wherein the material is possibly- amorphous. A small amount of carbon or one or more hydrocarbons appear to be necessary for the formation of the desired altered surface layer.
• the Kaufman ion source used was equipped with a graphite mounting - 1 S-
• an altered surface layer 18 produced in accordance with this procedure with accelerating voltages between about 1400 and about 1700 volts and exposure times as short as 1 minute is sufficient to prevent subsequent metallization of the exposed altered surface layer 18 where the metallization involves immersion plating of a material such as nickel.
• the remaining phosphosili ⁇ cate glass layer 12 is removed by immersing the substrate in a buffered solution of IONH4F(40%) :1HF at a temperature of between about 25'C and about 40*C.
• IONH4F(40%) :1HF at a temperature of between about 25'C and about 40*C.
• altered surface layer 18 delimits a pattern of, in this case, unaltered N + conductivity silicon having the con ⁇ figuration of the desired front'electrode structure.
• the substrate is immersion plated with nickel, an adhesive deposition of nickel forming a nickel layer 22 on the back side over the entire area of the alumi ⁇ num coating 14, while the adhesive deposition of nickel on the front side forms a layer 20 directly on the surface of substrate 2 only over those areas from which phosphosilicate glass layer 12 was removed following passivation.
• the altered surface layer 18 of the silicon forms a plating mask to which the nickel does not adhere.
• Plating of the nickel layers may be done according to various immersion plating methods. Preferably it is accomplished in accordance with an immersion plating process like or similar to the process described in U.S. Patent No. 4,321,283 of Kirit Patel, et al.
• the cleaned silicon substrate sur ⁇ face is pre-activated with a suitable agent.
• a suitable agent e.g. platinum chloride, stannous chloride - palladium chloride, or other well known activators may be used, as described, for instance, in U. S. Patent No. 3,489,603.
• both sides of the silicon ribbon are coated with a layer of nickel, preferably by immersing the ribbon in an aqueous bath as disclosed in said U.S. Patent No. 4321283, or an aqueous bath of nickel sulfamate and ammonium fluoride at a pH of about 2.9 and at approxi ⁇ mately room temperature for a period of about 2 to 6 minutes.
• the substrate is heated in an inert or a nitrogen atmosphere to a temperature and for a time sufficient to sinter the nickel layers and cause the nickel layer 20 on the front side of the substrate to react with the adjacent silicon to form a nickel suicide ohmic contact.
• the substrate is preferably heated to a temperature of about 300*C for between about 15 and about 40 minutes. This provides a nickel silicide layer with a depth .of about 300 Angstrom units at the interface between nickel layer 20 and substrate 2.
• the nickel layer 18 on the rear side forms an alloy with aluminum layer 12.
• the temperature of this sin- step should not greatly exceed 300 * C, as higher tem ⁇ peratures lead to excessive penetration into the silicon of nickel layer 20.
• the deposi ⁇ tion and sintering of the nickel is controlled such that nickel layer 20 on the front side of the substrate has a thickness of about 1000 Angstrom units.
• the nickel of layers 18 and 20- are preferably subjected to etching, as with nitric acid, and to further metallization, as with a second layer of nickel by immersion plating and one or more layers of copper by immersion plating and/or electroplating, by techniques well known in the art. No masking of the altered layer is required for the copper plating since the copper will not adhere to the damaged layer.
• anti-reflection coating 24 is applied to the front surface of the cell. This may be accomplished by any of a number of known methods, such as by chemical vapor deposition or evaporation of, for instance, Ti ⁇ 2 « Alternatively, anti- reflection coating 24 may be formed by the plasma deposition of silicon nitride at a temperature of about 150*C, as is well known in the art.
• the preferred method of practicing the present invention comprises performing the individual steps set forth hereinabove in the preferred mode described in detail for each step and in the sequence set forth.
• the present process has a number of advantages. Primarily, it eliminates the possiblity of junction 4 being spoiled by migration of nickel or nickel suicide during passivation, as might occur in shallow junction cells if an initial nickel coating were deposited on the front surface prior to passivation. Aside from reducing the possibility of spoiled cells, this relaxes the requirements for close thermal control (as by heat sinking) during passivation. It therefore make possible a high-throughput ion-beam passivation step in the manufacturing process.
• the present invention is capable of modification while remaining within the scope of the disclosure.
• the front electrode grid pattern is formed in the plating mask by photolithography, it will be understood that it might equally well be formed by other processes commonly employed in chemical milling (e.g., silk screen printing).
• the preferred method makes use of the phosphosilicate glass formed during N + diffusion to form the ion beam mask to define the damage layer pattern
• other materials or processes could be used for the front surface layer.
• an N-type substrate might be used as the starting material, the junction being formed for instance by diffusion with boron, thereby providing a borosilicate glass layer.
• an appropriate layer would have to be provided. It will be appreciated that the layer provided may either be capable of being etched to form a suitable plating mask or might itself be deposited in the appropriate configuration.
• the method of the present invention makes use of the altered layer formed by hydrogen passivation to mask subsequent plating except on earlier plated nickel
• the method may be used with other metals than nickel.
• the initial layer of the front surface electrodes on a shallow junction silicon device may be deposited by plating any of a number of low reactivity materials capable of forming (preferably at a low temperature) an ohmic contact and serving as a barrier to the diffusion of copper or any other base metal deposited at a later stage.
• Suitable metals for use with copper include palladium, platinum, cobalt, and rhodium, as well as nickel. While all of these materials form suicides, a suicide layer is not essential.
• the initial metal layer adhere properly, serve as an ohmic con ⁇ tact, and act as a barrier to the migration of any metal deposited later, as well as not significantly migrating to the junction itself.
• These materials may be applied by immersion plating techniques in the same manner as nickel.
• the method might be employed in the fabrication of Schottky barrier devices, the altered surface layer serving as a mask for the metallization.
• the metal-substrate interface is the junction, and the substrate consequently would not be provided with a junction by diffusion of phosphorus or the like.

Landscapes

• Photovoltaic Devices (AREA)
• Chemically Coating (AREA)
• Electroplating And Plating Baths Therefor (AREA)
• Electroplating Methods And Accessories (AREA)

Priority Applications (2)

Applications Claiming Priority (6)

Publications (1)

Family

ID=27415916

Family Applications (1)

Country Status (8)

Cited By (1)

Families Citing this family (3)

Citations (5)

Family Cites Families (4)

• 1984
  • 1984-12-14 DE DE19843490600 patent/DE3490600T1/de not_active Withdrawn
  • 1984-12-14 WO PCT/US1984/002064 patent/WO1985002942A1/en not_active Application Discontinuation
  • 1984-12-14 EP EP19850900534 patent/EP0168431A4/en not_active Withdrawn
  • 1984-12-14 AU AU38899/85A patent/AU574431B2/en not_active Ceased
  • 1984-12-14 NL NL8420336A patent/NL8420336A/nl unknown
  • 1984-12-14 GB GB08515900A patent/GB2160360B/en not_active Expired
• 1985
  • 1985-08-16 SE SE8503834A patent/SE456625B/sv not_active IP Right Cessation
  • 1985-12-14 CH CH3599/85A patent/CH670335A5/de not_active IP Right Cessation

Patent Citations (5)

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events