Classifications

• • G—PHYSICS
  • G04—HOROLOGY
  • G04C—ELECTROMECHANICAL CLOCKS OR WATCHES
  • G04C3/00—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means
  • G04C3/14—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor
  • G04C3/146—Electromechanical clocks or watches independent of other time-pieces and in which the movement is maintained by electric means incorporating a stepping motor incorporating two or more stepping motors or rotors
• • G—PHYSICS
  • G04—HOROLOGY
  • G04F—TIME-INTERVAL MEASURING
  • G04F8/00—Apparatus for measuring unknown time intervals by electromechanical means
  • G04F8/006—Apparatus for measuring unknown time intervals by electromechanical means running only during the time interval to be measured, e.g. stop-watch
• • G—PHYSICS
  • G04—HOROLOGY
  • G04G—ELECTRONIC TIME-PIECES
  • G04G9/00—Visual time or date indication means
  • G04G9/0082—Visual time or date indication means by building-up characters using a combination of indicating elements and by selecting desired characters out of a number of characters or by selecting indicating elements the positions of which represents the time, i.e. combinations of G04G9/02 and G04G9/08

Definitions

• Electronic chronograph in particular electronic, analog chronograph watch, chronograph time counter ''": • • • • '
• the present invention relates to an electronic chronograph, in particular an electronic, analog ⁇ o- ⁇ tre-c_hr ⁇ ograph, timed time counter comprising at least one hand of timed time minutes, a hand of timed time seconds and a hand of hundredths of a second of timed timers, stepping motors moving the minutes and seconds hands of timed time during the counting of time and, on the other hand, the hundredths of a second hand of timed time after taking the time, function of a stored value.
• timed time counter comprising at least one hand of timed time minutes, a hand of timed time seconds and a hand of hundredths of a second of timed timers
• stepping motors moving the minutes and seconds hands of timed time during the counting of time and, on the other hand, the hundredths of a second hand of timed time after taking the time, function of a stored value.
• WIPO are of practical use for the timing of competitions or training for competitions.
• An interesting performance would be the presence of a certain number of memories making it possible to memorize different times, combining in different ways, and which can if necessary be recalled afterwards for re-registration or control. It would be particularly interesting to be able to control, with a single digital electronic chronograph, the arrival times of ten, or even several dozen runners, who sometimes follow each other very closely.
• a piece that can be produced in a wristwatch format which makes it easy to "split" (that is to say, “take the exact time”) of a very rapid succession of runners' passages, then to read all these times successively afterwards , in analog form, would certainly be of interest to timekeepers, typically for sports timekeeping, but also for other types of timekeeping.
• the object of the present invention is to provide an analog electronic chronograph, in particular in the form of an analog electronic chronograph watch, making it possible to achieve the desirable performance previously mentioned, while avoiding the drawbacks of the prior art which often resided in too great a complication either in manufacturing or in use, or in a lack of flexibility and adaptability to the different types of timing that may arise.
• FIG. 1 is a front view of a chronograph watch according to the invention in the format of a wristwatch
• FIGS. 2A, 2B, 2C and 2D form together, as illustrated in FIG. 2E, the logic and electronic diagram of the chronograph watch in question
• FIGS. 3 and 4 are detailed diagrams respectively, of a counter-comparator block represented by a frame in FIG. 2B, and memories similarly shown in FIG. 2C.
• the chronograph watch comprises a housing 1, containing an electronic assembly for actuating the hands for measuring the current time and the hands of the different chronograph function variants.
• the current time is displayed, in a conventional manner, by an hour hand 2, central, a minute hand 3, also central, a minute hand 3, also central, and a second hand 4, in the "six" position. hours ", as has often been done.
• the hands of the chronograph function consist of a timed time hour hand 8, a timed time minute hand 7, located respectively at "twelve o'clock" and "nine o'clock".
• the most important hands for timing that is to say needle 6 of the seconds of timed time and hand 5 of the hundredths of a second of timed time are also central hands, the hand of hundredths of seconds of timed time working on an entirely external scale of a circled dial cular on which a unit of a hundredth of a turn can easily be read.
• the watch includes a series of timed time memories, and the contents of these memories can be selectively displayed, a digital display field 13, typically with liquid crystal, providing the indication of that of the memories.
• the hands of the chronograph function indicate the content.
• the hundredths of a second hand is not moved continuously but it is brought afterwards on the desired value, electronically recorded, once the time to be measured has been grasped. In operation, the hundredths of a second hand 5 remains stationary as long as the time is being counted and that the display of a timed time has not been called up.
• the SPLIT function is the typical, most common function, which allows intermediate time scores throughout a course or Q crossing scores of different runners during the same basic timing.
• a press on a push-button 10 started counting the chronograph, and one or more further presses on this button will make it possible to note intermediate times, or even a final time.
• the counting of time bases will continue until there is terminated by a STOP function using a push button 11.
• a first press on this push button has stopped counting, that is to say stopped the seconds hands, minutes and hours of timed time and caused the passage of the hundredths of a second hand, in the blink of an eye, on the desired value, a new press on this push button 11 returns all these hands to the zero position.
• each press by which we take the time of a passage does not interrupt the operation of the basic counter but instantly resets it to zero, which means that a new count begins.
• This LAP system is used for example for automobile racing circuits when it is desired each time to know the time taken by a racer to cover a lap. Thus, the timing of the end of the previous lap coincides with the start of timing of the next lap.
• the number of memories that such a watch can contain can be relatively high, relatively simple pieces can have six to eight memories, other pieces, more professional, can count twenty, thirty, even fifty or vantage.
• a two-digit display has been provided, which at most would correspond to ninety-nine memories.
• Pressing push-button 10 starts the time counter, hands 6, 7 and 8 rotate.
• Q Pressing the pusher 11 stops the time counter, the hands 6, 7 and 8 stop, the needle 5 receives a number of pulses corresponding to the number of hundredths of a second measured.
• a second press on push button 11 5 resets the counter to zero, i.e. the four WIPO hands 5, 6, 7 and 8 are brought to zero.
• the digital display 13 representative of the rank of the memory whose content is displayed, remains at zero. 5 2 ⁇ START-STOP-START-STOP-RESET (RALLYE) function
• the function is the same as above, except for the fact that, after the first pressure on the push-button 11, a new pressure is exerted on the push-button 10 so that the hands 6, 7 and 8 restart, 0 while the hundredths of a second hand stays where it was. Then, the next pressure on the pusher 11 again stops the needles, and the process can be repeated as much as desired. At the end, when the push-button 11 has been pressed twice in succession, the second press on it pushes all the needles to zero. The digital display 13 also remains at zero in this function.
• Pressing push-button 10 starts counting the time, hands 6, 7 and 8 turn. Pressing the pusher 10 again performs a "SPLIT", that is to say that the time counter does not stop, but the first memory stores the time of the SPLIT. At the same time, the device determining which memory is read, causes the reading of the first memory, so that the hands 6, 7 and 8 stop at the time corresponding to the instant when one has pressing button 10, and at the same time hand 5, hundredths of a second, returns to the memorized value. The digital display then indicates "1", which means that the contents of the first memory are displayed.
• the pins 6, 7 and 8 join the time value of the time counter, more precisely they join the value 5 of the following memory, which is itself synchronized
• the corresponding time values are successively memorized, each time in a later memory.
• the digital display still indicates the value "1", and the hands remain positioned on the indications of the first time in the Q register.
• pressing the push-button 12 switches the display to the second memory, the digital display 13 indicates "2", and the pins 5, 6, 7 and 8 are quickly brought to the value stored in the second memory, that is to say that they indicate the time of the second "SPLIT".
• a new pressure on the push-button 12 similarly displays the time recorded in the third memory, while the digital display 13 indicates "3". It is thus possible to continue calling up the times successively stored in the various memories.
• RATTRAPANTE or more precisely a function of resynchronization of all memories.
• This "RATTRAPANTE” or RESYNCHRONIZATION function is useful mainly when, after having loaded all the memories, there are still times to be taken, that is to say that the number of runners is greater than the number of memories.
• SPLITS take times
• a first press on push-button 10 starts the counter, hands 6, 7 and 8 rotate. Then, a first time-taking pressure again on the pusher 10 causes the display of the first time thus memorized in the first memory, the digital display
• WIPO tal 13 indicates "1". We can then continue the whole process as explained above, under 4, by stopping the counting using push button 11 (stop), when all the times have been apprehended. In these circumstances, all times remain in memory and their successive exploration is done using push-button 12. To reset the entire chronograph to zero, a second press on push-button 11 must be made.
• the RATTRAPANTE, RESYNCHRONISA ⁇ TION function may either be possible only when the counter is running, or be also possible when the counter is stopped. To carry out this function, it is always necessary first of all to press the push-button 12, which prepares the action, then the push-button 11, which resynchronizes all the memories on the basic counter. If this is stopped, all the memories will resynchronize to the value at which the basic counter is stopped. By cons, because the pusher 11 is pressed while the pusher 12 is also pressed, this pressure on the pusher 11 does not cause a reset (or RESET). 6 “Function 'START- ' LAP- (RATTRAPANTE ⁇ -LAP or n LAP, etc.
• LAP function or LAP-RESET
• the times are apprehended using the pusher 10, as has been seen previously, but, prior to the actuation of the pusher 10, the pusher 12 is pressed which prepares the LAP function or place of the SPLIT function.
• the time is memorized and the counter does not stop but is instantly reset to zero to start from zero.
• Hands 6, 7 and 8 stop and the hundredths of a second hand is positioned correctly; digital display 13 indicates "1".
• the first memory will store the time of the first round, the second memory the time of the second round, the third memory the time of the third round, etc. If one has to memorize a number of lap times greater than the number of available memories, one can use the RATTRAPANTE, RESYNCHRONIZATION function exactly as previously seen; naturally times
• the digital display field 13 displays the rank of the memory whose content is displayed. When the chronograph is not in use, this display field shows the date. However, it may happen that, during timing, one wishes to quickly ascertain the date, without however abandoning the timing. This can be done by pressing "long duration" on the push-button 12. In fact, if, while the field 13 displays the rank of a memory, the push-button 12 is pressed for more than about 3 sec, a timed circuit means that, after approximately 3 sec, the control of display 13 changes and the date appears in this field. This appearance of the date remains as long as the pusher 12 is pressed; as soon as it is released, the memory rank read is displayed again. Such pressure on the pusher 12, in order to make the date appear temporarily, does not cause the otherwise usual action of pressing on the pusher 12, that is to say advancing one step of the rank of memory whose
• FIG. 2E is a diagram of the comparator-comparator 51 of FIG. 2B, whose rather particular structure deserved to be represented in more detail.
• Fig. 4 is a detailed diagram of a memory such as memories 66, 67, 68 ' of FIG. 2C.
• reference marks situated between 20 and 39 have been taken for FIG. 2A, between 40 and 59 for fig. 2B, between 60 and 79 for fig. 2C and between 80 and 110 for fig. 2D.
• the reference signs of fig. 3 are between HO and 120, those of FIG. 4 between 130 and 140.
• An oscillator 21, controlled by quartz, provides a high frequency which is divided up to 100 Hz in a frequency divider 22. Since then, there is, for the function of displaying the current time, a second frequency divider 23 providing a frequency of 1 Hz. This is applied to an AND gate 24, the other input of which is applied. Apply a level "1", unless an SO switch (second to zero) is operated and applies a level zero on this other entry. This switch is closed (passing) when the crown 9 for resetting the mechanical time of the hands 2, 3 and 4 indicating the current time is operated. In this case, the pulses at 1 Hz can no longer pass through gate 24 and the stepping motor which actuates the seconds hand of the current time is stopped.
• pulses at 1 Hz exit from the door 24 and are applied to a circuit 25 which proceeds to the desired shaping of the pulses intended to advance a motor 36 one step every second.
• This motor 36 actuates, as seen in 37a, a second hand, which, by a conventional gear mechanism, drives a minute hand which itself drives the hour hand.
• a contact H (see fig. 2B lower left) is actuated twice a day by the hour hand of the current time, for counting the date.
• the output at 100 Hz of the frequency divider 22 is also applied to a gate 30 which constitutes the control gate of the basic time counter for the chronograph function.
• a gate 30 which constitutes the control gate of the basic time counter for the chronograph function.
• the push button 10 acts first of all on a shaping stage 26, the output signal of which
• this push-button 11 is actuated and its pulse is shaped by a circuit 27.
• This pulse is applied to an AND gate 37 whose other input receives the signal from the output Q of the flip-flop 28, and of which yet another input receives a signal C which is at level "1" when the push-button 12 is not pressed and which passes at level "0", when this last one is in a hurry.
• O PI formatting 29 is also applied to the second input of the REVERSE OR gate 32, the return tilting of the flip-flop 28 follows that of the flip-flop 29 only when the push button 11 has been released.
• a second manipulation of the push-button 11 causes a reset function (RESET) via an AND gate 38, one input of which receives the signal from the pulse generator 27 and of which another input receives the signal from the output Q of the 0 flip-flop 28.
• RESET reset function
• AND gate 38 one input of which receives the signal from the pulse generator 27 and of which another input receives the signal from the output Q of the 0 flip-flop 28.
• resetting to zero necessarily requires two manipulations of the pusher 11, which must first have been released to toggle the re-turn flip-flop 28, before a new manipulation can cause the reset function through the door 38.
• the latter also receives the signal C, which has the same effect as explained above concerning the door 37 .
• the output signal from gate 30, via a line CT is applied first to a pulse formatter 51 which delivers an impulse every hundredths of a second.
• This pulse 5 is applied to the clock input of a memory counter 65 which counts according to a cycle of 100, (preferably two quartetts BCD in series) and which provides the information of hundredths of a second of chronograph.
• a memory counter 65 which counts according to a cycle of 100, (preferably two quartetts BCD in series) and which provides the information of hundredths of a second of chronograph.
• This information is provided on a line formed by a plurality of conductors, which is why the connection is drawn in thick lines.
• the driver with the highest weighting switches once per cycle and is taken from the output information of the memory counter 65 to be applied to a pulse former 62 which delivers a signal at one pulse per second.
• this signal activates a memory counter 66, which counts to 60 and which provides the indication of seconds on a line comprising a plurality of conductors.
• an impulse trainer 63 which delivers one pulse per minute, which is applied as clock pulse to a counter-me oi re 67 which counts the minutes.
• the latter delivers the minute information on a multi-conductor line, and the highest weighting signal is taken to be applied to a pulse-forming stage 64 which delivers one pulse per hour on a memory counter 68 delivering the time information on a multi-conductor line.
• the four multiple pieces of information output from these counters namely the information of the hundredths of a second of the chronograph, the information of the seconds of the chronograph the information of the chronograph minutes, and the information of the chronograph hours, are delivered on bus lines which are applied respectively to the setting position e inputs of a series of memories 65.- 65 hundredths of a second, 66.-66 for secon ⁇ of 671 ..- 67n p e our minutes and e p 68.1-68n our times.
• Each (partial) memory shown in fig. 2C can advantageously have the structure shown in FIG. 4.
• it consists of a memory element proper 135, the input of which is controlled by a multiple door 134, which lets or does not pass the multiple information located on the input E.
• the output of the memory element 135 is applied to an output circuit 136 which comprises a multiple AND gate circuit 136a, and a group of output stages 136b. Again the information leaving the memory element 135 can be transmitted or stopped according to the command supplied to the multiple door 136a.
• the output stages In fig. 4, only one of the output stages has been shown, and it can be seen that it is formed by a transistor 137 working on a resistor 138.
• Such a configuration of output stages makes it possible to easily parallel the stages homologous output of all memories of the same weighting, this direct galvanic connection of all the outputs on a conductor automatically establishing an OR function. It is noted that the resistance 138 can be extremely high, taking into account the fact that there will be a large number of them in parallel. One can also provide for having a resistor 138 only for example on the outputs of the last memories, of rank n, the others being simply deleted.
• An input Ts controls the multiple output gate 136a, and there is only one memory, the first, the second or the nth, or the nth, whose output is on. Indeed, as we will see, there is only one of the memories (complete ranging from hundredths of a second to an hour) which receives a signal of level "1" on its input Ts.
• the inputs Ts of the different memories are supplied by the lines A - A, which correspond to the different outputs of the counter-comparator 51 which will be considered below.
• the metering counters moires 65 -68 include the same output circuit 136a, oo which makes it possible to control their output exactly like that of simple memories, also by a TS input.
• these memory counters include two outputs, one (MCO, MSO, MMO, MHO) to permanently supply the corresponding information, for the subordinate jaws and another output S, controlled by a circuit similar to circuit 136 in FIG. 4, and which delivers information only when it is desired to display the information even contained in the memory counters, that is to say the basic counter of the chronograph function.
• the opening or closing of the multiple door 134, at the entry of each (partial) memory is controlled by a flip-flop 132 which is put in the working position on reception of a BL pulse (blocking), passing through a shaping stage 130, and which is put in the rest position by an impulse on an input Sy (Synchronization) via the shaping stage 131.
• This is the information from the output Q of the flip-flop 132 which controls the multiple door 134, however passing through an OR gate 133. Indeed, the blocking pulse, coming from the stage 130, puts the flip-flop 132 at the working state and therefore establishes a zero level at the output Q.
• the level applied to multiple door 134 is always level "1".
• the BL pulse makes it non-passing, but only from the moment of its disappearance.
• a BL pulse is applied while the flip-flop 132 is already in the working state, that is to say that the door 134 is already non-passing, a level "1" appears at the entry of this gate 134 only during the very short duration of the pulse delivered by the pulse-forming stage 130, which means that, for a brief instant, the information present on the input E can pass over the memory element 135.
• both the memory memories (“basic counter” or “zero counter”) and the various memories (memories no 1, memory no 2 ... memory no n) include the input Ts which allows the delivery of output information for display.
• a door 35 is made passable and delivers a SPLIT pulse.
• This pulse is applied to the clock input of a counter 39 having n positions, plus a zero position. On departure, this counter was reset to zero by a pulse on its input r. It is a counter of the type either online or in ring. In the zero position, none of the outputs B-. at B carries no signal.
• SPLIT pulse is applied, this counter advances by one row and its output B, carries a level "1". As can be seen in fig. 2C, this level is applied to the BL input of the partial memories of memory no 1. This memory is then blocked
• comparator counter 51 In fig. 2B, there is a comparator counter 51, the details of which are shown in FIG. 3 and will be considered later.
• This counter has n positions, plus a zero position. It advances by one step each time it receives, on its clock input, a pulse which comes from a pulse former 44. The latter is controlled by the push-button 12, in such a way that it s now is to consider.
• the push-button 12 can have either its intrinsic function, which of advancing the counter 51 by one step, or an auxiliary function, which is to modify the effects of a pressure on the push-buttons 10 or 11. In this case, its intrinsic function is inhibited.
• the pusher 12 After passing through a pulse-forming stage 41, the pusher 12 places a flip-flop 50 in the working position. The output of the latter is applied to an input of an AND gate 43, the other of which input receives the output of an inverter 42, itself also controlled by the push-button 12.
• the door 43 does not pass through when the output Q of the flip-flop 50 passes to level "1".
• the output Q of the flip-flop 50 activates a uni-vibrator which establishes between its input and its output, a delay of approximately 3 sec for the transition to the state "! 1 , the transmission of the transition to the state" O "being instantaneous.
• a signal appears at the output of this uni-vibrator 52, and a flip-flop 53 is put in the working position, its output Q goes to level "0", and blocks an AND gate 47, which controls a selector 57 of the analog display In one position, this selector causes the display in field 13 of the chronograph 0 graph, represented at 59 in Fig.
• this display indicates the date.
• pressing the switch C for more than 3 sec causes, during the time it remains pressed beyond these 3 sec, a temporary switching selector 57, which 5 shows the indication of the date instead of the indication of the rank of the memory whose content is displayed, this which can be useful for timekeepers.
• the output Q of the flip-flop 53 is applied to an input of the OR gate 45, so that it returns the flip-flop 50 to the rest state before the switch 12 is released, which results in the intrinsic function of the latter (advancing one step of the counter-comparator 51) is inhibited.
• This counter 51 is shown in more detail in FIG. 3. It is seen in particular it comprises a converter "0-n / BCD" 120 that outputs information to the aforementioned selector 57, which actuates the digital display 59 via a converter "BCD / 7. SEGM” 58.
• the other input of the selector 57 Q receives a BCD signal which comes from a cycle counter of "3.! *, 55, itself receiving a signal from a divider by two 54 which receives, by a switch H, an impulse at each revolution of the hour hand of current time (in 37 fig. 2A).
• the selector 57 is controlled permanently by a flip-flop 56 which is put in the working position each time either the switch 10 operates (START or SPLIT) or each time the switch 12 operates so as to perform its intrinsic function (output from circuit 44). Furthermore, the flip-flop 56 is reset to the rest state either by the RESET function, resetting all the chronograph circuits to zero, or by the STOP function, provided that at that time the counter- comparator 51 is in the zero position, that is to say controls the display of the basic time counter of the chronograph function and not the display of one of the memories. This reset function of the flip-flop 56 is carried out via an AND gate 40 and an OR gate 40a.
• the comparator counter 51 also receives the pulses from SPLIT, just as it receives reset pulses (RESET) or also the pulses from the RESYNCHRONIZATION of the memory, coming from the AND gate 46. Furthermore, this counter receives the information from the state of the counter 39, previously considered and used to direct the SPLITS to the various memories.
• RESET reset pulses
• RESYNCHRONIZATION the pulses from the RESYNCHRONIZATION of the memory
• n + 1 outputs of the counter-comparator 51 are applied to the n + 1 groups of inputs TS of the basic memory-counters (zero memories " ) and of the various memories 1, 2, ... n-1, n It is therefore this counter 51 which determines which counter-memory or memory; the display will display the content. It is time to examine, in Fig. 3, the constitution of this counter-comparator 51.
• the input register 111 which simply stores the information received from the counter 39. It also includes an output register 112, which provides the outputs A ... A of the counter 51.
• the input ⁇ l of clock pulses each time this counter 112 advances, while the reset input (RZ), as well as the resynchronization input (RM). cause by means of an OR gate 113, the resetting of this counter 112.
• This latter comprises a zero position plus n positions, from 1 to n.
• the input register 111 also includes n positions, p-read a zero position, although its zero position is only rarely used.
• the comparator counter 51 of FIG. 3 includes various doors having different functions.
• an AND gate 119 receives the SPLIT pulses, just as it receives, delayed by a timer stage 118, the output signal from the zero stage of the counter 112.
• a SPLIT appears, a signal of level "1" appears at the exit of door 119.
• This via a series of doors 114 to 114 has the effect of causing the setting of the register counter 112 at the position where the input counter 111. is located.
• the counter 51 makes it possible to repeat a cycle in order to check recorded timed time values.
• v WIPO WIPO refer to other functions, for example the function of memorizing n arrivals and if it resulted from a simple manipulation of switch 12. In fact, this function erases the contents of the memories. However> it is done here in a way that eliminates this danger.
• the switch 12 is previously pressed and that the switch 11 is subsequently pressed, the door 46 may become passable, provided that the output of a comparator 48 which will be studied later provides a level "1" .
• an input of gate 46 still receives the signal Q, coming from output Q of flip-flop 28, which means that then the function of "resynchronization memoi ⁇ res" can only take place if the counter is working.
• the comparator 48 compares the state of the memory display control counter 51 and the state of the counter 39 for controlling the entry of .SPLITS in the memories (or of addressing SPLITS in the memories). If the state of the counter 51 is at least as high as the state of the counter 39, this means that all of the stored information has been read at least once and it is possible to therefore allow resynchronization of memories. If the state of the counter 51 is lower than the state of the counter 39 (if, for example, six SPLITS have been stored while only four memories have been read), the comparator 48 will not 5 delivers no signal of level "1" at its output, which prevents the operation of door 46 and therefore prohibits the function of "memory resynchronization".
• TM time division multiplexing
• TH time division multiplexing
• the three pieces of information of seconds, minutes and hours are directly applied respectively to each of three comparators, 82, 83, 84.
• the information of hundredths of a second is first applied to a circuit inhibitor 106, at the same time as it is applied, by a differentiator 108, to a delay circuit, of the uni-vibrator type, which, for returning to the rest state, exhibits a delay of at least 0, 04 sec from the output relative to the input. This means that as long as the information of hundredths of a second
• TC will be "in motion", that is to say will change at its rate of one pulse per hundredth of a second
• the output of delay circuit 105 will be permanently at level "1", and this level, applied to the circuit inhibitor 106, will make 0 that the information of the hundredths of a second will not be transmitted to the corresponding comparator 81.
• circuit 105 will return to rest state 5 after 0.04 sec, and the inhibitor circuit 106 will cease to act so that the information of hundredths of a second will be applied to comparator 81.
• comparator 81 does not receive a signal, while it receives the signal of hundredths of 5 seconds when the latter is permanent.
• the comparators 82, 83, 84 compare the setpoint information that i_Is receive (TS, TM, TH) with real situation information that they receive d * a counter respectively 93, 94, 95.
• This counter receives a reset pulse when the corresponding needle goes through zero, by mechanical means, by means of contacts ? , R_, R. They then receive as many pulses as the motor, which means that their state will be representative of the position of the corresponding needle.
• the comparators thus compare the actual position of the needle with the position that the needle should take, and as long as there is no identity, they give a signal of level "1" on their output.
• Q which makes a gate 85, 86, 87 pass respectively, receiving in addition on another input a clocked signal coming from a timing divider 33 fed by the frequency divider 22.
• the frequency of the timing divider will be adapted to the possibilities of the motors, also taking into account the inertia of the needles; a frequency of the order of 30 to 50 Hz should be suitable.
• the setpoint information for Q only advances by one unit at a time, i.e. only one pulse is sent by the corresponding gate, 85, 86, 87, after which compares it ⁇ tor is already seeing the reestablishment of coincidence.
• the gates 85, 86, 87 send a series of pulses. sions.
• the shaping circuits 97, 98 and 99 put the signals into the desired shape for the actuation of the motors, respectively 102, for the seconds, 103 for the minutes and 104 for the hours.
• This counter 39 can be an “online” counter which, starting from zero, goes step by step to its last position "n", then stops, new pulses on its input c / then remaining without effect .
• this counter could be of the "ring” type, in the sense that a new pulse appearing on the input c while the counter is already in its last position "n” causes the counter to return to position "1" (but in no case to position "O").
• a number of SPLITS equal to the capacity "n" of the counter can be recorded, after which the SPLITS (or LAPS) are no longer recorded, unless in the meantime performed a function of "resynchronization of memories, erasing the content of all memories and bringing the counter back to" O ".
• the recording of a number of SPLITS ( or LAPS) greater than the capacity of the counter (corresponding to the number of memoi ⁇ res) is possible; assuming for example that there are twenty-five memories and that the 25th memory is already loaded, the next SPLIT (or LAP ) will return to memory no 1, the old content of which will be erased, so the timed times n + l, n + 2, n + 3, etc., will automatically take the place of the old timed contents 1, 2, 3, etc. , without it being necessary to carry out a manipulation d "resynchronization".
• Both variants have their advantages and disadvantages, the choice between them will be a question of opportunity.
• the chronograph or the chronograph watch according to the proposed design can also advantageously be produced in the format of a pocket watch.
• the dial is larger and the various small inner dials, on which the second time hand 4, the timed minute hand work
• the watch could very well be produced in the format of a pocket watch or another format.

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Citations (7)

• 1983
  • 1983-06-23 CH CH343583A patent/CH654717GA3/fr unknown
• 1984
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