Classifications

• • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
  • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
  • F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
  • F02P3/00—Other installations
  • F02P3/02—Other installations having inductive energy storage, e.g. arrangements of induction coils
  • F02P3/04—Layout of circuits
  • F02P3/045—Layout of circuits for control of the dwell or anti dwell time
  • F02P3/0453—Opening or closing the primary coil circuit with semiconductor devices
  • F02P3/0456—Opening or closing the primary coil circuit with semiconductor devices using digital techniques
• • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
  • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
  • F02P—IGNITION, OTHER THAN COMPRESSION IGNITION, FOR INTERNAL-COMBUSTION ENGINES; TESTING OF IGNITION TIMING IN COMPRESSION-IGNITION ENGINES
  • F02P5/00—Advancing or retarding ignition; Control therefor
  • F02P5/04—Advancing or retarding ignition; Control therefor automatically, as a function of the working conditions of the engine or vehicle or of the atmospheric conditions

Definitions

• the present invention relates generally to the field of digital signal processing circuitry, and more particu- larly to the field of digital electronic dwell circuits used in ignition control systems which control spark and dwell occurrence.
• OMPI evidently produce accurate digital dwell control signals, generally they are not economically adaptable to operate in conjunction with digital spark timing circuits in which the spark timing is to be a function of engine speed and other additional engine variables. This is because generally prior art dwell circuits utilize cir ⁇ cuitry which is separate from the spark timing calcula ⁇ tion circuitry. Thus the dwell calculation is accom ⁇ plished without the utilization of the majority of the spark calculation circuitry, thus increasing the cost of the total ignition control system.
• prior art dwell circuits such as U.S. Patent 4,018,202 utilize a complex and costly cam struc ⁇ ture having an extremely large number of individual teeth projections in order to produce a series of high resolu ⁇ tion crankshaft position pulses, typically one pulse being produced for every one degree of crankshaft rota ⁇ tion...
• the construction of these cams is costly and their utilization would tend to inhibit utilization of the same cam to produce other crankshaft position pulses which would occur at other than one degree increments of crank ⁇ shaft rotation.
• this deficiency can be over ⁇ come by utilizing additional cams and additional crank ⁇ shaft position sensors, but then the cost of the ignition control system would be increased. While the one degree pulses can be electronically realized by dividing up large angular crankshaft pulses, this would also add to the cost of an ignition control system.
• the one ⁇ egree crankshaft position pulses produced by the prior art dwell circuits represent speed dependent crankshaft position pulses and enable the prior art circuits to readily calculate ignition dwell as a fixed number of degrees of crankshaft rotation.
• these circuits have prouie s in realizing a constant dwell time, rather tnan constant; awe11 angle, which is desired for some engine operative conditions.
• prior dwell circuits such as U.S. Patent 4,018,202 require complex feedback circuits having marginal stability.
• Some dwell circuits suqh as those in U.S. Patent 3,908,616 utilize speed independent pulses in order to calculate ignition dwell. While these circuits have eliminated the need for a multi-tooth crankshaft cam or its electronic equivalent for producing high resolution crankshaft position pulses, the disclosed circuit designs cannot produce large dwell angles which are required at high engine speeds.
• the dwell circuit in patent 3,908,616 contemplates adjusting count thresholds in order to adjust the dwell occurrence and/or contem ⁇ plates adjusting the rate at which pulse counting takes place. In order to implement either of these two func ⁇ tions, relatively complex and costly control structures are required.
• An object of the present invention is to provide an improved and simplified digital sign'al processing circuit which overcomes the aforementioned deficiencies and initiates a signal at a predetermined time prior to the occurrence of periodic variable rate signal transitions.
• a more particular object of the present invention is to provide an improved digital dwell circuit for an igni ⁇ tion control system which overcomes the aforementioned deficiencies .
• improved circuitry for receiving a signal comprising periodic pulse transitions and producing indicative signals com ⁇ mencing at predetermined times prior to the occurrence of the periodic pulse transitions.
• the cir ⁇ cuitry comprises: means for producing a periodic signal comprising periodic signal transitions occurring at a predetermined variable rate; means for receiving said periodic signal and for periodically developing a running count by counting pulses occurring at a predetermined rate, independent of said variable rate, between first and second predetermined time occurrences directly corre ⁇ sponding to the occurrence of sequential first and second pulse transitions of said periodic signal, and for pro- viding at said second time occurrences maximum running counts related to the time duration between said first and second pulse transitions; means for periodically receiving said maximum counts and effectively subtracting a predetermined number of counts therefrom to obtain a resultant subtracted count, said subtraction being com ⁇ pleted at substantially said second time occurrences; and means for periodically using said resultant subtracted counts to initiate an indicative signal after said second time occurrences
• an improved digital dv/ell circuit is provided whicn utilizes the circuitry recited in the pre ⁇ ceding paragraph.
• the dv/ell circuit utilizes crankshaft position sensor means to create said periodic signal (S j _) having periodic pulse transitions.
• Tn is corresponds to the periodic signal producing means providing signal transitions occurring at a variable (engine speed deter- mined) rate.
• SSp spark occurrence signal
• a counter means essentially receives the periodic signal and at a first predetermined time occurrence (tiD) directly relat- ed to a first pulse transition, the counter commences counting signal pulses (Ci) which occur at a speed inde ⁇ pendent rate.
• tiD predetermined time occurrence
• t]_ second subsequent predetermined time occurrences directly related to a second subsequent pulse transition a maximum running count is obtained which is related to the time duration that exists between the first and second pulse transitions.
• a subtraction means then effectively subtracts a predetermined number of pulses from this maximum pulse count, wherein the sub ⁇ traction is essentially instantaneously accomplished at the second time occurrences.
• This subtracted count is then utilized to initiate a signal at a predetermined time prior to the next pulse transition of said periodic signal which occurs after the transitions directly relat ⁇ ed second time occurrences t ⁇ .
• the present invention contemplates utilizing a down counter to accomplish the subtraction, and a count com ⁇ parator is utilized to compare the resultant subtracted count with tne next subsequently created running count such that when the subtracted count equals the subsequent running count dwell will be initiated at a predetermined number of counts prior to the occurrence of the maximum running count.
• the present invention is capable of producing up to almost 100% dwell if necessary since tne nu ⁇ ;.oer of subtracted counts can De any arDi- trarily large number and thus dwell can be initiated at any time after the second transition and before the next transition. It is contemplated that preferably the pulse transitions all have the same polarity.
• the present invention also readily enables initiating dwell at a fixed speed independent time prior to the pulse transi ⁇ tions of the periodic signal, since the initiation of dwell will occur at a time prior to a pulse transition equal to a predetermined number of the counts of the speed independent signal C- .
• improved digital circuitry for receiving a signal com ⁇ prising periodic pulse transitions and producing indica ⁇ tive signals commencing at predetermined times prior to the occurrence of the periodic pulse transitions.
• the circuitry comprises: means for producing a periodic signal comprising periodic signal pulse transi ⁇ tions occurring at a predetermined variable rate; means for receiving said periodic signal and for periodically developing a running count by counting pulses occurring at a predetermined rate, independent of said variable rate, between first and second predetermined time occur ⁇ rences directly corresponding to the occurrence of sequential first and second pulse transitions of said periodic signal, and for providing at said second time occurrences maximum running counts related to the time duration between said first and second pulse transitions; means for periodically receiving said maximum counts and effectively subtracting a predetermined number of counts therefrom to obtain a resultant subtracted count, said subtraction being completed at substantially said second time occurrences; wherein the improvement comprises means counting down from said resultant subtracted count at a rate which is independent of said variable rate and no more than the
• This embodiment contemplates utilizing a down counter to accomplish the subtraction, and the same down counter receives the next subsequently created running count such that when a zero count is obtained a signal is produced at the counter overflow terminal and dwell will be initiated at a predetermined number of counts prior to the occurrence of the maximum running count.
• the dwell circuit of the present invention is contemplated as being utilized in an ignition dwell and spark control system in which the cir ⁇ cuitry which produced the running count also is utilized to determine spark occurrence. This double utilization of the running count by both the dwell and spark timing circuits of an ignition control system reduces the cost of the ignition control system.
• Figure 1 is a combination block and schematic diagram illustrating an engine ignition control system for an internal combustion engine
• Figure 2 is a schematic diagram illustrating a typi ⁇ cal configuration for a dwell circuit illustrated in Figure 1;
• Figure 3 is a schematic diagram illustrating a typi cal configuration for a pulse width modulator circuit shown in Figure 1;
• Figure 4 is a schematic diagram illustrating typica circuit configurations for several of the block compon ⁇ ents shown in Figure 1;
• Figure 5 is a schematic diagram illustrating a typi cal configuration for a select decoder illustrated in Figure 1;
• Figure 6 is a schematic diagram illustrating a typi cal configuration for a slow speed decoder shown in Figure 1;
• Figure 7 is a schematic diagram illustrating a typi cal configuration for a spark logic circuit shown in Figure 1;
• Figure 8 is a schematic diagram of another typical embodiment for a dwell circuit shown in Figure 1;
• Figure 9 is a graph which shows the desired spark timing versus engine speed characteristic provided by th circuit in Figure 1;
• Figures 10A tnrough 10Q are a series of graphs which illustrate electrical signals and pulse count accumulations as functions of time for the system shown in Figure 1.
• FIG. 1 illustrates an electronic ignition control system 10 for a two cylinder internal combustion engine (not shown) .
• the control system 10 receives sensor input signals and develops control signals that determine the spark timing and dwell (coil excitation time) for a distributorless inductive ignition system.
• Tne term "distributorless" contemplates the fact that no rotating mechanical distributor will be utilized, and that instead sparks will be created in each of the two cylinders simultaneously but at different times with respect to the compression cycle of each cylinder.
• the control system 10 includes a rotating cam 11 synchronously rotatable with a crankshaft of a two cylin ⁇ der engine, the crankshaft being shown schematically as an axis of rotation 12.
• the cam 11 has a peripheral projection 13 spaced from the axis 12 and the cam 11 is contemplated as rotating in a clockwise direction.
• An advance sensor 15 is contemplated as having a sensing probe 16 positioned at a fixed location with respect to the rotating cam 11, and a reference sensor 17 is contemplated as having a sensing probe 18 similarly positioned with the probes 16 and 18 being spaced apart by 35 degrees of angular rotation of the cam 11 (which corresponds to 35 degrees of engine crankshaft rotation) .
• the probes 16 and 18 produce crankshaft angular position pulses as the projection 13 rotates by these probes with the produced position sensing pulses initially occurring in response to the passage of a leading edge 13a of the projection passing by the sensing probes and the position pulses terminating after a trailing edge 13b has pass ⁇ ed by the probes 16 and 18.
• Ti e advance sensors 15 and 17 receive input signals from tneir corresponding sensing probes and produce digital pulse outputs in correspond ⁇ ence thereto at output terminals 19 and 20, respectively.
• the positioning of the sens ⁇ ing probes 16 and 18 with respect to the rotating cam 11 and its projection 13 is not totally arbitrary and that it is contemplated that the probe 16 is positioned such that it defines the maximum possible advance (earliest possible spark ignition occurrence for a cylinder com ⁇ pression cycle) fbr the ignition system 10 while the probe 18 defines the minimum possible advance (generally corresponding to top dead center of cylinder position which is generally termed zero or reference advance).
• the positioning of the probes 16 and 18 define the earliest and latest possible occurrences of spark igni ⁇ tion, respectively, for the ignition control system 10. The significance of this will be demonstrated subse- quently.
• the advance and reference output terminals 19 and 20 are eoupled as inputs to advance and reference buffers 21 and 22, respectively, which impedance isolate the sensors from subsequently circuitry and insure the production of precise-, uniform magnitude corresponding digital pulses at the output terminals 23 and 24, respectively.
• Figures 10A and 10B illustrate the sensing pulses produced at the terminals 23 and 24, respectively, and illustrate that these pulses occur periodically at times t ⁇ and .t ⁇ corre- sponding to the passage of the leading edge 13a past the sensing probes 16 and 18.
• the control system 10 includes a master clock oscil ⁇ lator 25 which produces clock timing pulses C p at an output terminal 26 wherein the frequency of the clock oscillator is preferably 149.25 KHz.
• the clock pulses Cp are illustrated schematically in Figure IOC on a greatly expanded horizontal time scale and are continuously pro ⁇ quizd by the oscillator 25 regardless of the angular position of the crankshaft of the engine.
• a prescaler 27 is shown as being integral with the clock oscillator 25 and producing output signals C_ through C4 at the output terminals 28 through 31, respectively.
• the prescaler essentially comprises a series of counters which receive the clock signals C p and produce related lower frequency signals by essentially counting and thereby frequency dividing down the oscillator signal pulses C p .
• the c ⁇ signal produced at the terminal 28 has an operative frequency of 1.16 KHz, C2 has a frequency of 9.33 KHz, the frequency for C3 is 49.75 KHz and the frequency of C4 is 74.6 KHz. All of the signals Cp and C -C4 have repetition rates independent of the speed of crankshaft rotation.
• the prescaler 27 has a reset terminal 32 which causes resetting of the counters internal to the prescal ⁇ er 27.
• the signals developed by the clock oscillator 25 and prescaler 27 at the terminals 26 and 28 through 31 essentially determine the operation of the ignition con- trol system 10 in conjunction with the pulses sensed by tne advance and reference probes 16 and 18.
• the signals produced at the terminals 28 through 31 are essentially used in various counters included in the ignition control system 10 and therefore tne provision for resetting the internal counters in tne prescaler 27 via the reset term- inal 32 is required to insure that the counters receiving their inputs in accordance with the signals at the term- inals 28- through 31 will be synchronized with the advance sensor signal S ⁇ described below.
• a pulse synchronizer 33 receives an advance signal input from " Sine ⁇ terminal 23 and the clock pulse signal C p from the terminal 26.
• the pulse synchronizer produces a synchronized advance pulse Si at an output terminal 34.
• the synchronizer 33 insures that a . pulse Si is produced at the terminal 34 at a time ti which corre ⁇ sponds to the first clock pulse C p that occurs after the time t ⁇ .
• the signal Sj_ (shown in Figure 10D) represents an advance pulse which is synchronized with the occurrence of the clock pulses C p .
• the pulse synchronizer 33 also receives an input at a terminal D from an output terminal 35 of an inhibit circuit 36.
• the inhibit circuit 36 produces a 4 millisecond delay pulse at the terminal 35 in response to the occurrence of the spark ignition and this delay or inhibit signal at the terminal 35 prevents the pulse synchronizer from producing an output at the term ⁇ inal 34 for 4 milliseconds after the occurrence of spark ignition.
• the reason for this is to quiet the output of the synchronizer 33 such that additional sparks will not be initiated by the synchronizer 33 until at least 4 mil ⁇ liseconds has elapsed since the last spark occurrence.
• a pulse synchronizer 37 is similar to the synchron ⁇ izer 33 and receives inputs from the reference sensor terminal 24 and the clock pulse terminal 26 and produces a synchronized reference pulse signal S2 at an output terminal 38.
• the synchronizer 37 merely insures that a reference signal S2 has an initial time occurrence which precisely corresponds to the occurrence of one of the clock pulses C p . Since it is contemplated that the
• the reference signal S2 is illustrated in Figure 10E as comprising periodic pulses which occur at the times t2 « It should be remembered that the duration of time between the occurrence of the advance pulses Sj_ at t _ and the reference pulses S2 at the times t2 corresponds to 35 degrees of engine crankshaft rotation. Of course the actual time duration between ti and t2 will vary directly as a function of engine speed.
• a delay circuit 39 receives the signal S along with the clock pulses C p and produces a delayed output signal
• the delay circuit 39 receives the synchronized signal S , delays this signal by one full period of the clock pulse signal C p and produces this delayed signal Sj_D at the terminal 40.
• Figure 10F illustrates this delay advance signal SiD which has a time occurrence at tiD that is one clock pulse period later than tne time occurrence t ] _ .
• the rea ⁇ son for creating the delayed advance signal SiD is that in many cases the control system 10 will transfer accumu ⁇ lated counts at the times t]_ in response to the pulses ⁇ , and subsequently the accumulated counts are to be reset. Obviously the transference and resetting cannot occur simultaneously, thus tne present system provides for delaying the resetting until after transference.
• the ignition control system 10 essentially utilizes a main up-counter 41 to linearly count up C pulses occurring at the terminal 28 in between the occurrence of
• O PI WiPO delayed advance signal pulses S ⁇ D This is accomplished by having the main up-counter 41 receive its counter input from the terminal 28 while its reset terminal is directly connected to the terminal 40.
• the counter 41 therefore periodically linearly accumulates a speed inde ⁇ pendent running count which has a maximum value directly related to engine speed since the counting occurs during the times tiD which occur every 360 degrees of crankshaft rotation.
• Figure 10H illustrates a waveform representative of the linearly incremented running count of the counter 41. It should be noted that individual counting steps have not been illustrated in Figure 10H since these steps occur at the relatively high frequency of the signal Ci produced by the prescaler 27.
• Figure ION does illustrate the count in the main counter 41 on a very expanded horizontal time scale, and this figure clearly illustrates the incremental nature of the accumulated count in the counter 41.
• the accumulated count of counter 41 is produced at 6 output terminals 42 through 47 with terminal 42 corre ⁇ sponding to the least significant bit and terminal 47 corresponding to the most significant bit.
• the main up-counte.r 41 represents a 6 bit binary counter. Such counters are well known and readily available.
• the electronic ignition control sys ⁇ tem 10 utilizes the maximum accumulated count obtained by the counter 41 as an indication of engine speed
• the ignition system 10 also utilizes each incremental count produced ⁇ the counter 41 at its output terminals 43 through 47 as control signal inputs to spark time occur ⁇ rence circuitry within the system 10, and these incre ⁇ mental counts are utilized to produce a desired non ⁇ linear spark occurrence versus engine speed characteris- tic. The manner m which this is accomplished will now be discussed.
• Each of the output terminals 43 through 47 of the main up-counter 41 are coupled as inputs to a read only memory (ROM) device 48 which has 4 output terminals 49 through 52 which are coupled as control signal inputs to a rate multiplier device 53.
• the rate multiplier 53 receives a continuous stream of input clock pulses C2 via a direct connection to the terminal 29 and produces a corresponding output pulse stream at an output terminal 54 in accordance with the control signals received from the terminals 49 through 52.
• the rate multiplier device 53 is set by the pulse S which is received via a direct connection from the terminal 34, and this reinitiates the operation of the rate multiplier 53.
• the rate multiplier essentially functions as a controllable frequency divider which multiplies (actual divides) the frequency of the input pulse stream by predetermined integers which are determined by the control signals received from the ROM. Rate multipliers are well known and are readily avail ⁇ able.
• the pulse stream produced at the output terminal 54 is subsequently accumulated in an accumulator means which develops a count related to the number of pulses produced at the terminal 54.
• This total accumulated count, which occurs between the pulses Si is then subsequently utilized by the ignition control system 10 to determine the occurrence of spark ignition.
• the above described spark timing technique of utilizing a rate multiplier which is controlled by a read only memory circuit that receives incrementally controlled inputs related to engine speed is essentially described in copending U.S. Patent application Serial No. 779,974, filed March 22, 1977, and assigned to the same assignee as the present invention, now U.S. Patent 4,168,682.
• the ROM 48 functions as a table look-up device which produces different control signals at the terminals 49 through 52 that control the frequency multi ⁇ plication (division) provided by the rate multiplier 53.
• the end result is that the output pulse count produced at the terminal 54 is a non-linear function of engine speed such that a desired spark ignition occurrence versus engine speed characteristic can be obtained.
• the accumu ⁇ lator means effectively integrates or accumulates the pulse count at the terminal 54 and determines, between S pulses, a maximum pulse count non-linearly related to engine speed. This maximum pulse count is then utilized to determine spark ignition.
• U.S. Patent 4,104,997 illustrates an analog system in which a desired non-linear spark occurrence versus engine speed characteristic is produced by con ⁇ trolling the rates of charging and discharging a capaci ⁇ tor.
• the ROM 48 and rate multi ⁇ plier 53 digitally implement an equivalent function for controlling the rate of pulses produced at the terminal 54, and an accumulator means integrates these pulses to produce the desired result.
• Figure 9 illustrates the desired advance angle (spark timing occurrence) versus engine speed characteristic which is desired by issued ' U.S. Patent. 4,104,997 and which is a typical characteris ⁇ tic also desired by the present system.
• Patent 4,168,682 explains how the slope changes of the cnaracteristics snown in Figure 9 can be digitally imple- mented by use of a rate multiplier and ROM without having the ROM store every individual point of the composite characteristics shown in Figure 9.
• the curve N.V represents the desired spark occurrence characteristic for no vacuum being sensed by an ignition control system whereas the curve V represents the desired characteristic for a predetermined amount of vacuum being sensed by an engine control system.
• the present system contemplates providing the-read only memory 48 with an additional input signal at an input terminal 55 wherein this additional signal repre ⁇ sents the output of a pulse width modulator circuit 56 having its output terminal 57 directly connected ' to the terminal 55.
• the pulse -width modulator 56 receives an analog signal at an input terminal 58 wherein the magni ⁇ tude of this analog signal is related " to a predetermined engine condition, in the present case related to the magnitude of sensed engine vacuum pressure.
• the pulse width modulator 56 will then produce a periodic digital two state signal which has a duty cycle (ratio of one logic state to the other during one cycle period) which is related to the magnitude of this analog signal.
• the control signals at the terminals 49 through 52 determine the rate multiplication of the rate multiplier 53, and since the output of the rate multiplier is effectively integrated by a following accumulator means r the effect of applying a pulse width modulation signal as an input at the terminal 55 of the read only memory 48 results in providing a continuous interpolation capability between the two extreme control output produced at the terminals 49 through 52 in response to the terminal 55 having a high or low logic state.
• the ROM 48 need only store a maximum and minimum output corresponding to whether the signal at the terminal 55 is either high or low.
• these maximum and minimum outputs correspond to the sensed vacuum pressure being above or below a predeter ⁇ mined vacuum pressure.
• the actual outputs produced at the terminals 49 through 52 are then made to represent a value more directly indicative of the magnitude of the analog voltage at the terminal 58 by first producing a digital two stage signal whose duty cycle varies in accordance with the analog signal magnitude and then by applying this signal to the input terminal 55.
• the read only memory output will be switched back and forth between these two extreme outputs such that the average output of the read only memory will represent any output value in between these two extreme outputs which are stored in the read only memory.
• the read only memory of the present system need only store two output limits in response to any desired engine condition and an average ROM output corre ⁇ sponding to any magnitude between these two output limits can be obtained merely by using a duty cycle pulse width modulated input signal to the read only memory.
• the vacuum sensor 59 is contemplated as comprising a two position vacuum sensing switch 60 with a wiper arm terminal coupled to ground and the wiper varying between a first terminal 61 when sensed engine vacuum pressure is below a predetermined threshold value and a second terminal 62 when the sensed vacuum pressure is above this predetermined value.
• the terminal 62 is coupled to a B+ terminal through a resistor 63 and is coupled to the terminal 58 through a resistor 64.
• a capacitor 65 is coupled from the terminal 58 to ground.
• the switch 60 will short the terminal 62 to ground resulting in slowly changing the voltage at the terminal 58 from a high voltage to a low voltage. Preferably this voltage change occurs at a relatively slow 0.5 second time con ⁇ stant.
• the signal at the terminal 58 represents an analog signal which has a magnitude related to the sensed engine vacuum pressure.
• the pulse width modulator circuit 56 comprises a DC level comparator 66 having a negative input terminal coupled to the input terminal 58 through a resistor 67. Limiting diodes 68 and 69 are also connected to the nega ⁇ tive input terminal of the comparator 66 and essentially limit the signals received by the comparator to magni ⁇ tudes either one diode drop above B+ or one diode drop below ground.
• the terminals 42 through 44 are received as inputs to a NAND gate 70 whose output is coupled through an inverter 71 to a control terminal 76 of an FET gate 72.
• An output terminal of the gate 72 is coupled to a positive input terminal 75 of the comparator 66 which is also coupled to B+ through a resistor 73 and to ground through a capacitor 74.
• the output of the comparator 66 is directly coupled to the output terminal 57 of the pulse width modulator 56.
• the signals at the terminals 42 through - 44 are converted by the NAND gate 70 into a relatively slow periodically occurring pulse signal which is used as the control siynal for the FET gate 72.
• This control ' signal is illustrated in Figure 10K.
• the positive input terminal (terminal 75) of the comparator 66 is shorted to. a positive reference voltage just above ground potential by the gate 72.
• the FET gate 72 is open circuited until the next occurrence of a control pulse at its control terminal 76.
• Figure 10K illustrates the control signals at the terminal 76 and Figure 10L illustrates the signal waveforms produced in response thereto at the positive input terminal 75 of the comparator 66.
• Superimposed on the waveform shown in Figure 10L is a high first dashe ⁇ voltage level 77 corre- sponding to low vacuum pressure is being sensed by the sensor 59, a low second voltage level 78 corresponding to the low voltage eventually produced at the terminal 58 upon closure of the switch 60 in response to a high vacuum pressure being sensed, and an interim voltage level 79 corresponding to the voltage at the terminal 58 which would occur at some time after the closure of the switch 60 but before the attainment of the limit level 78.
• Figure 10M shows the output signal of the comparator 66 produced in response to the signal shown in Figure 10L being created at the positive input terminal 75 while the negative terminal of the comparator 66 receives a transi- tional voltage corresponding to the dashed level 79 shown in Figure 10L.
• Figure 10M illustrates that the output of the comparator 66 is a digital two state logic signal in which the duty cycle of this signal varies in accordance with the magnitude of the analog signal produced at the terminal 58. For a no vacuum condition corresponding to the level 77 present at the negative input terminal of the comparator 66, the output of the comparator 66 would remain at zero, and for a voltage at the negative input terminal corresponding to the level 78, the output of the comparator 66 would always be high.
• Figure 10M illustrates that for interim values of vacuum (in the case of a continuous analog sensor being used instead of a two position vacuum sensing switch) or in the case of a slowly changing signal representing changing from vacuum to non-vacuum and back again (when a two position vacuum sensing switch is used), an analog signal is produced at the terminal 58 which results in a varying duty cycle signal being produced as the output of the comparator 66.
• this varying duty cycle signal applied to the input of the ROM 48 allows the output of the ROM to vary, in a periodic step- wise manner, between two maximum limits and this produces an output whose average value will be directly related to the magnitude of the analog signal at the terminal 58.
• an accumulator means essentially follows the rate multiplier 53 and effective ⁇ ly converts the pulse count at the terminal 54 into an integrated or accumulated maximum count. It is this accumulation step that results in effectively averaging tne different control signal outputs produced at the ROM output terminals 49 and 52 by use of the pulse width modulator 56 altering the duty cycle of the input ROM control signal at the terminal 55.
• Figure ION represents the incremental count, incrementing at twice the fre-
• the count of the main counter is incremented by counting Ci pulses such that the terminal 43 now indicates a new count as an input signal to the read only memory 48.
• a differ ⁇ ent input control signal is now received by the read only memory 48 and the output terminals 49 through 52 of the ROM now are able to implement different rates of increase SL3 and SL4.
• the rates of increase SL1-S 4 represent different fixed integers used by the rate multiplier for frequency division.
• the ROM 48 can select either of two different rates of increase for the count processed by the rate multiplier 53 because for any main count received as an input by the RUM 48 from the counter 41, either a zero or one logic state can be produced by the pulse width modulator 56 at the input terminal 55.
• Figure 10O illustrates the dif ⁇ ferent characteristics for rates of pulse count increase at terminal 54 that can be implemented by the rate multi ⁇ plier 53 in accordance with the control input signals received by the read only memory 48 which supplies con ⁇ trol inputs to the rate multiplier.
• the present system contemplates selectively switching betv/een maximum rates of increase such as SLi and SL3 and minimum rates of increase such as SL2 and SL4 during the times tiD-tj and after tj, respectively, to obtain a composite (average) rate of increase which can be anywhere within the limits defined by the maximum and minimum rates of increase.
• the output of the rate multiplier 53 at the output terminal 54 is effectively coupled to an accumulator means which accumulates a count related to the total pulse count produced at the output terminal 54.
• This accumulator means essentially comprises a select decoder 80, a main advance up-down counter 81 and an auxiliary advance up counter 82.
• the rate multiplier output term ⁇ inal 54 is coupled as an input to both the select decoder 80 and a count terminal (>) of the auxiliary advance up counter 82.
• the auxiliary advance up counter 82 receives a reget signal by means of a direct connection to the terminal 34 at which the Sj pulses are produced.
• the up counter 82 is a four bit binary counter and produces count outputs at terminals 83 through 86 which are cou ⁇ pled as inputs to preset terminals P _ through P4 or the main advance up-down counter 81.
• the select decoder 80 receives three inputs in addition to the input from the rate multiplier output terminal 54 and produces a main output at a pulse terminal 87 and a latched advance out ⁇ put signal Sj_L at a terminal 88.
• the select decoder 80 receives the delayed advance pulses SjD by means of a direct connection to the terminal 40, and the decoder also receives the pulses C3 from a direct input connec- tion to the terminal 30.
• the select decoder 80 also receives an input signal termed SSp from a spark logic circuit 90.
• the signal SSp is a signal produced by the spark logic circuit 90 at the desired time occurrence t x of spark ignition and this signal is very short in duration (one period of the high frequency clock pulse
• the latched output signal S produced at this terminal is initiated in response to the delayed advance signal S j _D and is terminated at the time t x .
• the output produced by the select decoder 80 at the main output terminal 87 essentially comprises the pulse signal C3 during the pulses ⁇ D (occurring at the times t D) until the time t x at which spark ignition occurs. After the times t x until times t j _D the decoder 80 direct ⁇ ly couples pulses at the rate multiplier output terminal 54 to the main terminal 87.
• the terminal 88 of the select decoder 80 is directly coupled as an input to an up-down control terminal (U/D) of the main up-down advance counter 81.
• the terminal 87 of the select decoder is directly coupled to an input clock terminal (>) of the advance counter 81.
• a preset enable (PE) input terminal of the advance counter 81 directly receives the signal SSp by means of a direct connection to the output terminal 89 of the spark logic circuit 90.
• An input reset terminal of the advance counter 81 receives a power on reset signal POR by means of a direct connection to a terminal 91.
• This power on reset signal is merely utilized to initiate operation of the ignition control system 10 in response to the initial application of power to the ignition control system. This is accom ⁇ plished by means of a capacitor 92 coupled between the terminal 91 and a power on reset terminal 93 that receives positive power when power is applied to the ignition system control 10.
• the terminal 91 is coupled to ground through a resistor 94.
• the components 91 through 94 provide for a positive impulse at terminal 91 upon the first application of power to the power on reset terminal 93, and this is utilized to initiate the reset ⁇ ting of the advance counter 81.
• the advance counter 81 produces an output at a zero detect terminal 94 and this output is produced whenever the advance counter counts down to or through a count of zero.
• the auxiliary advance counter 82 is reset at the times t j _ by the S j _ pulses. The counter 82 then proceeds to count up in accordance with the pulses passed by the rate multiplier 53 and provided at ' the out ⁇ put terminal 54. This count is registered in the four bit binary output terminals 83 through 86.
• the signal SSp produces a positive spike at the preset enable terminal of the main advance counter 81.
• the advance counter 81 after the time t x , essentially acts as if it had continuously counted all of the pulses produced at the terminal 54 since tne initial time t . Tne reason that the counter 81 did not directly count all of the clock pulses at the terminal 54 from the time t j _ to tne time t x was because
• the advance counter 81 continues to count up all of the pulses pro ⁇ cuted at the output terminal 54 of the rate multiplier 53.
• a maximum count is obtained by the main advance counter 81 which is related to the actual time difference betv/een the periodic occurrence of synchronized advance sensor pulses Si at the times t ⁇ >
• the maximum count obtained by the counter 81 is related to engine speed and that the ROM 48 and rate multiplier 53 control this relationship in a piece- wise linear manner to obtain the correct non-linear rela- tionship between the maximum count in the advance counter 81 and engine speed, as well as the relationship between the maximum count and the sensed engine vacuum pressure.
• the select decoder 80 produces a latched signal S ⁇ at the terminal 88 which now instructs the advance counter 81 to count dov/n instead of up. Simultaneously, the select decoder 80 now channels the fixed frequency clock pulses C3 to its output terminal 87.
• This count is essentially the non-linear pulse occurrences which occur at the out ⁇ put terminal 54 of the rate multiplier 53.
• the count of this counter is directly transferred to the advance counter 81 by means of preset enable circuitry.
• Preset enable cir- cuitry for counters is very well known and merely results in loading a counter with a preset count in response to an actuation pulse being received at a preset enable terminal.
• Figure 10J illustrates the count in the main advance counter 81. This figure illustrates that at the times t ] _ a maximum count is obtained by the advance counter 81. Then technicallyat times t_D the counter 81 will count down at the fixed rate determined by the rate occurrence of the signal C3 , whereas the up counting of this counter was determined by the ROM 48 and rate multiplier 53 imple ⁇ menting a stepwise rate of increase of pulse counts.
• U.S. Patent 4,104,997 clearly illustrates how such a stepwise increasing rate combined with a linear decreas ⁇ ing rate will result in accurately determining the spark time occurrence for internal combustion engines so that a proper advance versus engine speed relationship is developed.
• This zero detect signal represents the desired spark timing occurrence
• the spark logic circuit 90 utilizes -this signal to produce the signal SSp at the terminal 89 as well as produce a composite signal (dwell/spark) at an output terminal 100 which contains both dv/ell and spark timing information.
• This composite signal at the terminal 100 is then coupled to an input terminal 101 of an output pre-driver 99 which supplies an output at a terminal 102 to a final driver stage 103, in an ignition coil power stage 98 (shown dashed) , that controls the excitation of the primary winding 104 of an ignition coil.
• a high voltage second ⁇ ary winding 105 of the ignition coil is coupled to the spark gaps of a two cylinder engine to produce ignition pulses therein.
• a primary ignition coil current sensing resistor 106 is contemplated as sensing the current through the pri ⁇ mary coil 104 and providing a feedback signal at a terminal 107 which is coupled as an input to the output pre-driver. This is utilized to maintain constant pri ⁇ mary ignition coil current excitation in a well known manner.
• the output pre-driver 99 also receives an input at the terminal 109 related to actual battery voltage magnitude and another input at a terminal 110 related to whether or not an engine stall condition has occurred. If engine stall, abrupt slow crankshaft rotation, has been detected, then the current through the primary coil 104 will be slowly decreased so as to remove energization from this coil without generating a spark until the engine stall condition has been rectified.
• the battery voltage magnitude signal at the terminal 109 is utilized to alter the ignition coil current driving signal to obtain constant energy spark ignition despite variations in battery voltage.
• the output pre-driver 99 and the ignition coil power stage 98 are contemplated as compris- ing standard electronic ignition system components and therefore the details of these components will not be discussed since they do not form part of the present invention.
• the spark logic circuit 90 which creates the dwell/ spark control signal at terminal 100 receives the master clock pulses C p from a direct connection to the terminal 26.
• the circuit 90 also is directly connected to the terminals 34 and 38 for receiving the signals Si and ⁇ 2, respectively.
• the spark logic circuit 90 receives the POR signal at a reset terminal for initiating the logic components contained in the circuit 90 in response to the initial application of power to the electronic ignition control system 10.
• the circuit 90 also receives the zero detect signal produced at the terminal 94 of the main advance counter 81.
• the spark logic 90 also receives a dwell initiation signal by means of a direct connection to an output terminal 120 of a dwell circuit 121, and the circuit 90 also receives a slow speed detect signal from an output terminal 122 of a slow speed decoder 123.
• the spark logic_ circuit 90 produces the signal SSp at 'the terminal 89 wherein the SSp signal is a pulse at t x which exists for one clock pulse period of the pulses C p .
• the circuit 90 will also create a combined dwell initiate and spark timing occurrence output signal at the output term ⁇ inal 100.
• the logic circuit 90 will receive dwell initiate signals from the terminal 120 and spark timing occurrence signals from the terminal 94 for each cycle of cylinder compression. If for some reason a dwell initiating signal has not been received by the spark logic circuit 90 prior to the
• the spark logic circuit 90 will initiate dwell at the times t j _ corresponding to the occurrence of the pulses S . Similarly, if for some reason a spark igni ⁇ tion has not occurred by the times t2 at v/hich the pulses ⁇ 2 occur, then the spark logic 90 will create a spark occurrence at these times.
• the signal at the terminal 122 insures that dwell will be initiated at the times t]_ and that spark will occur at the times t2 « This provide a dwell equal to 35 degrees of crankshaft rotation for slow speed conditions and provides for spark ignition at essentially top dead center of the cylinder compression cycle.
• the signal at the terminal 122 allows dwell to be initiated by the signal at the terminal 120 and spark to be determined by the zero detect provided at the terminal 94.
• the signal produced at the terminal 100 is initiated in response to when dv/ell is desired to commence (t DW and is terminated in response to when the spark logic 90 determines spark ignition should occur (t x ) .
• FIG. 7 A typical embodiment for the spark logic circuit 90 is illustrated in Figure 7.
• the power on reset connec ⁇ tion has not been shown in Figure 7 in order to simplify the diagram. All of the components in E'igure 7 corre ⁇ spond to standard logic gate components and flip-flop devices.
• the engine stall indicating signal produced at the terminal 110 is the output of an engine stall counter 125 which receives a reset input signal by a direct connec ⁇ tion to the terminal 34.
• the counter 125 receives a counting clock input signal by means of an input direct connection to tne terminal 47 of the main up counter 41.
• the stall counter 125 determines that between consecutive times ti at which the synchronized advance pulses S ] _ occur, the main up counter 41 has registered a predetermined number of changes in the most significant bit of the counter which is connected to the terminal 47, then the counter 125 will indicate that the count being registered by the main up counter 41 is too high. This indicates that the actual time elapsed between consecutive times t ] _ is too great thus indicating that the engine has stalled by virtue of the fact that the engine crankshaft is not rotating above a predeter ⁇ mined speed.
• a stall indicating signal at the terminal 110 will be received by the output pre-driver 99 and result in appropriately modifying the output of the pre-driver to take into account this condi ⁇ tion.
• the internal construction of the stall counter 125 mere-ly consists of a resettable pulse counter which develops an output whenever the pulse count is above a predetermined threshold. Readily available logic cir- cuits can implement such a function.
• the slow speed decoder 123 essentially works on a similar principle to the stall counter 125.
• the slow- speed decoder 123 determines when the count in the main up counter 41 exceeds a predetermined maximum count. This is accomplished oy coupling the terminals 43 through 47 as inputs to the slow speed decoder 123.
• the decoder 123 is reset at times tj_D via a connection to terminal 40.
• the decoder also receives the pulses Si via a direct conrfection to the terminal 34 and it receives a power on reset pulse via a direct connection to the terminal 91.
• the decoder 123 pro ⁇ prises a slow speed detection at the terminal 122 at times t whenever the count of the main counter indicates tnat the actual time between the S D pulses exceeds a pre ⁇ e- teriuined maximum time. Whenever this occurs, this indi- cates that the engine speed is below a predetermined minimum speed, and the signal at the terminal 122 is received by the spark logic circuit 90 and results in initiating dwell at the times t j _ and causing spark igni- tion to occur at the times t2 «
• the engine speed which actuates the stall counter 125 is an engine , speed much less than the predetermined engine speed which resulted in actuating the slow speed decoder 123.
• Figure 6 illustrates a typical embodiment for the slow speed decoder 123 and the components in Figure 6 represent standard logic circuit components used for a typical implementation.
• Figure 5 illustrates a typi ⁇ cal digital circuit implementation for the select decoder 80.
• controllable gates 126 and 127 are illustrated. These gates operate as selective open or short circuits between their throughput terminals in response to the digital logic signals present at their respective control terminals 128 and 129.
• Figure 4 illustrates a typical digital circuit implementation for the advance and reference buffers 21 and 22, the pulse synchronizers 33 and 37, the delay circuit 39 and the inhibit circuit 36.
• the logic circuit implementations shown in Figure 4 comprise standard digi ⁇ tal logic circuits.
• the inhibit circuit 36 besides producing a four millisecond delay pulse at the terminal 35 in response to receiving a spark ignition signal (SSp) and in response to the received C pulses provided as a timing duration input, also provides a two millisecond delay signal after spark ignition at an output terminal 130.
• the terminal 130 is coupled to the dwell circuit 121 and the two millisecond signal serves to inhibit the operation of the dwell circuit until at least two milliseconds after the
• the inhibit circuit 36 merely utilizes the signal (SSp) at the times t x to initiate two differ ⁇ ent monostable time periods which are provided at the terminals 35 and 130 to implement different delays for circuitry in the electronic spark ignition control system 10.
• the detailed configuration of the inhibit circuit 36 will not be specifically recited since the embodiment in Figure 5 is a typical embodiment using standard compon- ents and many other embodiments could accomplish this desired function.
• FIG. 2 A first such typical embodiment 121 is illustrated in Figure 2, and another embodiment 121' is illustrated in Figure 8.
• Figure 8 prime notation is utilized to identify substan ⁇ tially similar corresponding components.
• the dwell circuit 121 receives running count counter inputs from the main counter output term ⁇ inals 42 through 47 at preset input terminals Pi through Pg of a dv/ell down counter 131 (131 1 ).
• the terminal 34 at which the S pulses are produced is directly coupled to a preset enable terminal of the dwell down counter and a counting clock pulse input terminal 132 (132') for the dwell down counter is provided.
• the terminal 31 at which the pulses C4 are produced is coupled through a controllable gate 133 to tne terminal 132.
• the terminal 132 is also coupled as a pulse counter input to an auxiliary dwell counter 134 which has a reset terminal directly coupled to the terminal 40 for receiving reset pulses at the times t D corresponding to the pulses S j _D.
• the count output of the auxiliary dwell counter 134 is coupled to a maximum count logic circuit 135 which is intended to produce a low out ⁇ put signal at its output terminal 136 in response to the count in the auxiliary dwell counter reaching or exceed ⁇ ing a predetermined maximum count.
• the terminal 136 is directly connected to a control terminal 137 of the through gate 133.
• the auxiliary dwell counter 134 insures that after the reception of reset pulses S]_D, the through gate 133 will pass a precise num ⁇ ber of clock pulses as inputs to the input terminal 132 of the dwell down counter 131 and auxiliary counter 134.
• the count of the dwell counter 131 is preset to the maximum running count obtained by the main counter 41, wherein this maximum count is directly linearly related to engine crankshaft speed.
• the auxil- iary dwell counter 134 and controllable gate 133 effec ⁇ tively ' result in, subsequently at times t D, having the dv/ell down counter 131 rapidly count down a predetermined number of counts from the maximum speed related count obtained by the main counter 41. It should be noted that the rate of down counting occurs at the relatively high repetition frequency of the signal C4 , whereas the rate of up counting the main counter 41 occurs at the sub ⁇ stantially slower rate of occurrence of the pulses Cj_.
• the terminals 42 through 47 of the main up counter 41 are also coupled as inputs to a count comparator 138 which also receives the output count of the dwell down counter 131.
• the comparator 138 will produce a logic signal indicating this condition at an output terminal 139.
• the terminal 139 is coupled to an input set terminal 140 of a latch device 141.
• the output of the latch device 141 is coupled through a controllable gate 144 to the output terminal 120 of the dwell circuit 121 and a reset term ⁇ inal 142 of the latch 141 is directly coupled to the terminal 34 at which the ⁇ i signal is produced.
• the tv/o millisecond inhibit signal produced at the terminal 130 is cpupled to a control terminal 143 of the controllable gate 144.
• the dwell circuit shown in Figure 2 operates as follows. At the time occurrence tj_ of the synchronized advance pulses S j _ , the maximum running count in the main counter 41 is preset into the dwell down counter 131. At times tiD after the maximum count of the main counter 41 is loaded into the dwell down counter 131, the circuitry 132 through 137 has the down counter 131 rapidly count down a predetermined number of counts. Preferably this predetermi-ned number of counts which occur at the high fixed frequency of pulses C4 will be equivalent to 6 milliseconds of real time as measured by an equivalent number of pulse counts at the frequency of the signal pulses Ci .
• the main up counter 41 is reset by the pulses Sj_ ⁇ .
• the dwell down counter 131 will have completed its effective subtract- tion of a predetermined number of counts from the maximum count preset into the dwell down counter 131.
• the comparator 138 just after the times tiD, will compare the subtracted output count of the dwell down counter 131 with the newly initiated running count of the main up counter 41.
• the main counter 41 produces a running count by counting the pulses C which have an engine speed independent repetition rate.
• a maximum running count related to engine crank ⁇ shaft rotational speed is loaded into the down counter 131.
• the down counter then effectively subtracts a predetermined number of C4 pulse counts to arrive at a resultant subtracted count at substantially the time occurrence t j _ .
• This resultant subtracted count is then utilized to produce dwell ignition occurrences, prefer ⁇ ably at a substantially fixed time duration prior to the next time occurrence of t j _ whicn corresponds to the next pulse transition of the periodic signal S]_.
• crankshaft position sensor signal S ] _ as the periodic signal having periodic signal pulse transitions occurring at a predetermined variable (speed dependent) rate
• the present invention also con ⁇ templates the use of the spark occurrence signal SSp as the periodic signal having pulse transitions which occur at a variable (speed dependent) rate. In this manner the present invention can implement dwell at a predetermined time prior to spark ignition occurrence rather than at a predetermined time prior to the occurrence of a specific engine crankshaft position.
• minor modifications of the disclosed cir- cuitry are necessary and these modifications are within the capability of those of average skill in the art.
• the count of the dwell counter 131 is illustrated as a solid line whereas the count of the main up counter 41 is illustrated as a dashed line.
• Figure 10P illustrates at the times ti a maximum count is preset into the dwell down counter 131 and then a predetermined number of counts is rapidly subtracted (at times t ⁇ D) from this number. Subsequently the dwell counter 131 maintains this subtracted count as its output.
• the count in the main counter 41 is set to zero and this counter will commence up counting in response to the pulses Cj_ resulting in linear increment ⁇ ing of the count of the counter 41.
• the count in the main counter 41 will equal the sub- tracted count being maintained by the dwell counter 131.
• the comparator 138 will produce a logic signal that will set the latch 141 and thereby signal the initiation of the dwell by the signal produced at the latch output terminal 120.
• the latch 141 will be reset upon the occurrence of the pulse signal S .
• the present invention by utilizing substantially all of the time duration between identical polarity pulse transitions of tne crankshaft position sensor signal j _ to determine the maximum running count which is related to engine speec, has provided a maximum running count which is an extremely accurate indication of engine speed. Since this running count is updated for each engine crankshaft rotation of 360 degrees, the engine speed information is similarly updated for each crank- shaft revolution thus providing an up-to-date indication of engine speed.
• the present invention is capable of producing large dwell angles which is something that has not been obtained by similar prior art circuits (U.S.
• Patent 3,908,616 which illustrate utilizing a first portion of the crankshaft revolution cycle to calculate engine speed and a second portion of the same crankshaft revolution cycle to calculate dwell occurrence.
• the prior art circuits limit dwell occurrence to this second portion of tne crankshaft revolution cycle.
• the present invention implements dv/ell without adjusting count threshold levels of count comparators and without adjust ⁇ ing the various rates of count accumulating. While adjusting the rate of count accumulating was found to be necessary for the spark control circuitry disclosed herein, it is obvious that the rate adjustment circuitry is much more complex and costly than the dwell control circuitry.
• the present invention is believed to be superior to prior dwell control circuits which require adjusting pulse accumulation rates or pulse count switch ⁇ ing threshold levels in order to implement a desired dwell excitation mode over a range of different engine soee ⁇ s.
• the controllable gate 144 is utilized to insure that the dwell initiation signal at terminal 120 will not start until at least 2 milliseconds after the occurrence of spark ignition. This insures that 100 percent dwell will not be obtained, and that therefore the primary ignition coil winding 104 will not be constantly excited. This insures the occurrence of a spark for each cylinder when it is in its compression cycle, since if the primary winding always received current excitation no spark could be generated.
• Figure 8 illustrates another embodiment 121' of the dwell circuit which is similar to the embodiment shown in Figure 2. Identical reference numbers are utilized for identical components and prime notation is'used for simi- lar components.
• output count terminals 42 through 47 of the ..main counter 41 are connected to preset inputs P ⁇ through P6 of a dwell down counter 131' .
• a preset enable terminal of the dwell counter 131' is directly coupled to the terminal 34 such that the counter will be preset in response to the pulses S ] _ .
• a dwell counter overflow terminal is directly connected to a terminal 139' which is coupled to a terminal 140' that is directly connected to the set terminal of a latcn 141' having its output connected to the terminal 120 through a control ⁇ lable gate 144'.
• a reset terminal of the latch 141' is directly connected to the terminal 34 thus providing for resetting the latch 141' in response to the signal S _.
• the controllable gate 144' has a control terminal 143' v/hich is directly connected to the terminal 130 such that the controllable gate 144' will implement a minimum 2 millisecond delay after SSp for initiating a dwell signal at terminal 120.
• the dwell down counter 131' has a clock input term- inal 132' which is coupled through a controllable gate 133' and an OR gate 160' to the terminal 31 at which the pulses C are present.
• An auxiliary dwell counter 134' has a reset terminal directly connected to the terminal 40 and a clock signal input terminal directly connected to an output terminal 159 of gate 133'.
• the output count of the auxiliary dv/ell counter 134' is coupled to a maxi ⁇ mum count logic circuit 135' which produces an output ⁇ signal at a terminal 137' whenever the auxiliary dwell counter count equals or exceeds a predetermined count.
• controllable gate 133' is directly connected as a control input terminal to the controllable gate 133' , and this terminal is also coupled through an inverter stage to a control input terminal 150' of a controllable gate 151' coupled, together with OR gate 160', between the terminal 132' and the terminal 28 at which the pulses C are pres ⁇ ent.
• the OR gate 160' permits pulses passed by either of the .controllable gates 133' or 151' to reach the terminal 132' .
• the dwell circuit 121' illustrated in Figure 8 essentially illustrates the operation of the dwell circuit 121' by illustrating the count of the dwell down counter 131' as a function of time.
• the dwell down counter 131' is preset with the maximum count obtained by the main up counter 41.
• the count of the auxiliary dwell counter 134' is set to zero resulting in the controllable gate 133' passing a predetermined number of the rapidly occurring clock pulses C4.
• the maximum count logic cir ⁇ cuit 135' will open the controllable gate 133' and result in closing the controllable gate 151'.
• the dv/ell dov/n counter 131 has effectively, instantan-
• the dwell down counter 131 ' will continue down counting at a rate determined by the occurrence of the pulses C . It should be noted that this occurrence rate is the same occurrence rate at which the main counter 41 is being linearly incremented up to its maximum count representative of engine crankshaft speed. At a subsequent time the count in the dwell down counter 131' will reach zero and on the next count an overflow indication will be produced at the terminal 139'. This will result in setting the latch 141 and providing a dv/ell initiation signal at the output terminal 120 assuming at least a two millisecond delay between spark occurrence and dwell initiation.
• the dwell circuit in Figure 8 differs from that in Figure 2 in that the need for a complex count comparator such as the comparator 138 in Figure 2 is eliminated by the circuit configuration shown in Figure 8. This is accomplished by having the dwell dov/n counter 131' con ⁇ tinue to count down at a rate determined by the Ci pulses after effectively subtracting a predetermined number of counts occurring at the rapid frequency of the signal C4. In this manner, the output of the dwell down counter 131' will reach zero at predetermined times tpr ⁇ ahead of the predetermined times tj_. This occurs since if no counts were subtracted and engine speed remained the same, then the dwell down count would overflow exactly at times t j _.
• the dwell circuits 121' and 121 insure that dv/ell initiation will occur at a predetermined time prior to the occurrence of the advance pulses ⁇ i at the times t «
• the circuit 121' in Figure 8 accomplishes this end result without the use of the complex comparator 138 shown m Figure 2 and therefore is believed to oe more economical since fewer connecting lines and logic gates are required for the circuit 121'.

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• Engineering & Computer Science (AREA)
• Chemical & Material Sciences (AREA)
• Combustion & Propulsion (AREA)
• Mechanical Engineering (AREA)
• General Engineering & Computer Science (AREA)
• Electrical Control Of Ignition Timing (AREA)
• Combined Controls Of Internal Combustion Engines (AREA)
• Ignition Installations For Internal Combustion Engines (AREA)

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• 1980
  • 1980-06-09 BR BR8008711A patent/BR8008711A/pt unknown
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  • 1980-06-09 WO PCT/US1980/000682 patent/WO1980002862A1/en active IP Right Grant
  • 1980-06-09 EP EP80901351A patent/EP0031834B1/en not_active Expired
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• 1983
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