UST955006I4 - Delay circuits using negative resistance CMOS circuits - Google Patents

Delay circuits using negative resistance CMOS circuits Download PDF

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Publication number
UST955006I4
UST955006I4 US05/695,716 US69571676A UST955006I4 US T955006 I4 UST955006 I4 US T955006I4 US 69571676 A US69571676 A US 69571676A US T955006 I4 UST955006 I4 US T955006I4
Authority
US
United States
Prior art keywords
circuits
negative resistance
circuit
delay
resistance cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US05/695,716
Other languages
English (en)
Inventor
Joseph Richard Cavaliere
David Barry Eardley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE19752549308 priority Critical patent/DE2549308A1/de
Priority to JP50132212A priority patent/JPS5178665A/ja
Priority to FR7534734A priority patent/FR2296307A1/fr
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US05/695,716 priority patent/UST955006I4/en
Application granted granted Critical
Publication of UST955006I4 publication Critical patent/UST955006I4/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0416—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/04163—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/46—One-port networks
    • H03H11/52—One-port networks simulating negative resistances
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/16—Control of transmission; Equalising characterised by the negative-impedance network used
    • H04B3/18—Control of transmission; Equalising characterised by the negative-impedance network used wherein the network comprises semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Nonlinear Science (AREA)
  • Networks Using Active Elements (AREA)
  • Electronic Switches (AREA)
US05/695,716 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits Pending UST955006I4 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE19752549308 DE2549308A1 (de) 1974-12-24 1975-11-04 Schaltung mit negativer widerstandscharakteristik
JP50132212A JPS5178665A (enrdf_load_stackoverflow) 1974-12-24 1975-11-05
FR7534734A FR2296307A1 (fr) 1974-12-24 1975-11-07 Circuits a resistance negative a dispositifs mos complementaires
US05/695,716 UST955006I4 (en) 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53608074A 1974-12-24 1974-12-24
US05/695,716 UST955006I4 (en) 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US53608074A Continuation 1974-12-24 1974-12-24

Publications (1)

Publication Number Publication Date
UST955006I4 true UST955006I4 (en) 1977-02-01

Family

ID=27065031

Family Applications (1)

Application Number Title Priority Date Filing Date
US05/695,716 Pending UST955006I4 (en) 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits

Country Status (3)

Country Link
US (1) UST955006I4 (enrdf_load_stackoverflow)
JP (1) JPS5178665A (enrdf_load_stackoverflow)
FR (1) FR2296307A1 (enrdf_load_stackoverflow)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4217502A (en) 1977-09-10 1980-08-12 Tokyo Shibaura Denki Kabushiki Kaisha Converter producing three output states
EP0023127A1 (en) * 1979-07-19 1981-01-28 Fujitsu Limited CMOS Schmitt-trigger circuit
US4301427A (en) 1977-07-30 1981-11-17 Tokyo Shibaura Denki Kabushiki Kaisha Astable MOS FET multivibrator
EP0023655A3 (en) * 1979-07-26 1982-11-17 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4456837A (en) 1981-10-15 1984-06-26 Rca Corporation Circuitry for generating non-overlapping pulse trains
US4486671A (en) 1982-03-29 1984-12-04 Motorola, Inc. Voltage level shifting circuit
US4554467A (en) 1983-06-22 1985-11-19 Motorola, Inc. CMOS Flip-flop
US4568842A (en) 1983-01-24 1986-02-04 Tokyo Shibaura Denki Kabushiki Kaisha D-Latch circuit using CMOS transistors
US4628218A (en) 1982-02-03 1986-12-09 Nippon Electric Co., Ltd. Driving circuit suppressing peak value of charging current from power supply to capacitive load
US4672243A (en) 1985-05-28 1987-06-09 American Telephone And Telegraph Company, At&T Bell Laboratories Zero standby current TTL to CMOS input buffer
US4712058A (en) 1986-07-22 1987-12-08 Tektronix, Inc. Active load network
US4952818A (en) 1989-05-17 1990-08-28 International Business Machines Corporation Transmission line driver circuits

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4525640A (en) * 1983-03-31 1985-06-25 Ibm Corporation High performance and gate having an "natural" or zero threshold transistor for providing a faster rise time for the output
JPS60125015A (ja) * 1983-12-12 1985-07-04 Hitachi Ltd インバ−タ回路
US4682047A (en) * 1985-08-29 1987-07-21 Siemens Aktiengesellschaft Complementary metal-oxide-semiconductor input circuit
CA1296074C (en) * 1987-06-23 1992-02-18 David E. Fulkerson Fet capacitance driver logic circuit
IT1243691B (it) * 1990-07-27 1994-06-21 Sgs Thomson Microelectronics Traslatore di livello a transistore singolo, con bassa impedenza dinamica, in tecnologia cmos

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911289A (en) * 1972-08-18 1975-10-07 Matsushita Electric Ind Co Ltd MOS type semiconductor IC device
US3832574A (en) * 1972-12-29 1974-08-27 Ibm Fast insulated gate field effect transistor circuit using multiple threshold technology

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4301427A (en) 1977-07-30 1981-11-17 Tokyo Shibaura Denki Kabushiki Kaisha Astable MOS FET multivibrator
US4217502A (en) 1977-09-10 1980-08-12 Tokyo Shibaura Denki Kabushiki Kaisha Converter producing three output states
EP0023127A1 (en) * 1979-07-19 1981-01-28 Fujitsu Limited CMOS Schmitt-trigger circuit
US4535255A (en) 1979-07-26 1985-08-13 Tokyo-Shibaura Denki Kabushiki Kaisha Positive feedback amplifier circuitry
EP0023655A3 (en) * 1979-07-26 1982-11-17 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4456837A (en) 1981-10-15 1984-06-26 Rca Corporation Circuitry for generating non-overlapping pulse trains
US4628218A (en) 1982-02-03 1986-12-09 Nippon Electric Co., Ltd. Driving circuit suppressing peak value of charging current from power supply to capacitive load
US4486671A (en) 1982-03-29 1984-12-04 Motorola, Inc. Voltage level shifting circuit
US4568842A (en) 1983-01-24 1986-02-04 Tokyo Shibaura Denki Kabushiki Kaisha D-Latch circuit using CMOS transistors
US4554467A (en) 1983-06-22 1985-11-19 Motorola, Inc. CMOS Flip-flop
US4672243A (en) 1985-05-28 1987-06-09 American Telephone And Telegraph Company, At&T Bell Laboratories Zero standby current TTL to CMOS input buffer
US4712058A (en) 1986-07-22 1987-12-08 Tektronix, Inc. Active load network
US4952818A (en) 1989-05-17 1990-08-28 International Business Machines Corporation Transmission line driver circuits

Also Published As

Publication number Publication date
JPS5178665A (enrdf_load_stackoverflow) 1976-07-08
FR2296307B1 (enrdf_load_stackoverflow) 1977-12-16
FR2296307A1 (fr) 1976-07-23

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