UST955006I4 - Delay circuits using negative resistance CMOS circuits - Google Patents

Delay circuits using negative resistance CMOS circuits Download PDF

Info

Publication number
UST955006I4
UST955006I4 US05/695,716 US69571676A UST955006I4 US T955006 I4 UST955006 I4 US T955006I4 US 69571676 A US69571676 A US 69571676A US T955006 I4 UST955006 I4 US T955006I4
Authority
US
United States
Prior art keywords
circuits
negative resistance
circuit
delay
resistance cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US05/695,716
Inventor
Joseph Richard Cavaliere
David Barry Eardley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE19752549308 priority Critical patent/DE2549308A1/en
Priority to JP50132212A priority patent/JPS5178665A/ja
Priority to FR7534734A priority patent/FR2296307A1/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US05/695,716 priority patent/UST955006I4/en
Application granted granted Critical
Publication of UST955006I4 publication Critical patent/UST955006I4/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0416—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/04163—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/46—One-port networks
    • H03H11/52—One-port networks simulating negative resistances
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/16—Control of transmission; Equalising characterised by the negative-impedance network used
    • H04B3/18—Control of transmission; Equalising characterised by the negative-impedance network used wherein the network comprises semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Nonlinear Science (AREA)
  • Networks Using Active Elements (AREA)
  • Electronic Switches (AREA)

Abstract

A negative resistance circuit constructed of complementary field effect transistors has several applications. A voltage change at an input to the negative resistance circuit alters the current at the input node in a direction inverse to that normally caused by such a voltage change. The circuit can be used to speed up the charging or the discharging of a circuit node capacitance.
US05/695,716 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits Pending UST955006I4 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE19752549308 DE2549308A1 (en) 1974-12-24 1975-11-04 Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over
JP50132212A JPS5178665A (en) 1974-12-24 1975-11-05
FR7534734A FR2296307A1 (en) 1974-12-24 1975-11-07 Negative resistance integrated circuit - has two MOS FET's with specified gate connections for switching nide change-over
US05/695,716 UST955006I4 (en) 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53608074A 1974-12-24 1974-12-24
US05/695,716 UST955006I4 (en) 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US53608074A Continuation 1974-12-24 1974-12-24

Publications (1)

Publication Number Publication Date
UST955006I4 true UST955006I4 (en) 1977-02-01

Family

ID=27065031

Family Applications (1)

Application Number Title Priority Date Filing Date
US05/695,716 Pending UST955006I4 (en) 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits

Country Status (3)

Country Link
US (1) UST955006I4 (en)
JP (1) JPS5178665A (en)
FR (1) FR2296307A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0023127A1 (en) * 1979-07-19 1981-01-28 Fujitsu Limited CMOS Schmitt-trigger circuit
EP0023655A2 (en) * 1979-07-26 1981-02-11 Kabushiki Kaisha Toshiba Semiconductor memory device
US4952818A (en) 1989-05-17 1990-08-28 International Business Machines Corporation Transmission line driver circuits

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4525640A (en) * 1983-03-31 1985-06-25 Ibm Corporation High performance and gate having an "natural" or zero threshold transistor for providing a faster rise time for the output
JPS60125015A (en) * 1983-12-12 1985-07-04 Hitachi Ltd Inverter circuit
US4682047A (en) * 1985-08-29 1987-07-21 Siemens Aktiengesellschaft Complementary metal-oxide-semiconductor input circuit
CA1296074C (en) * 1987-06-23 1992-02-18 David E. Fulkerson Fet capacitance driver logic circuit
IT1243691B (en) * 1990-07-27 1994-06-21 Sgs Thomson Microelectronics SINGLE TRANSISTOR LEVEL TRANSLATOR, WITH LOW DYNAMIC IMPEDANCE, IN CMOS TECHNOLOGY

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911289A (en) * 1972-08-18 1975-10-07 Matsushita Electric Ind Co Ltd MOS type semiconductor IC device
US3832574A (en) * 1972-12-29 1974-08-27 Ibm Fast insulated gate field effect transistor circuit using multiple threshold technology

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0023127A1 (en) * 1979-07-19 1981-01-28 Fujitsu Limited CMOS Schmitt-trigger circuit
EP0023655A2 (en) * 1979-07-26 1981-02-11 Kabushiki Kaisha Toshiba Semiconductor memory device
EP0023655A3 (en) * 1979-07-26 1982-11-17 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
US4952818A (en) 1989-05-17 1990-08-28 International Business Machines Corporation Transmission line driver circuits

Also Published As

Publication number Publication date
FR2296307B1 (en) 1977-12-16
JPS5178665A (en) 1976-07-08
FR2296307A1 (en) 1976-07-23

Similar Documents

Publication Publication Date Title
UST955006I4 (en) Delay circuits using negative resistance CMOS circuits
KR940017156A (en) Controllable Delay Circuit
ES366284A1 (en) Capacitor charge transferring arragements and circuits
US3562559A (en) P-mos multivibrator
GB1330679A (en) Tri-level voltage generator circuit
GB878296A (en) Improvements in or relating to static multi-state circuits incorporating transistors
GB1112201A (en) High speed,low dissipation logic gates
JPS5570128A (en) Oscillator circuit
JPS55163917A (en) Inverter circuit
SU527003A1 (en) Differential amplifier
SU420124A1 (en) COMPOUND COMPLEX INVERTOR P 1 LR-WL • If '^' OErpTnnk ^ vulk cLu ^ * 1, g sua
SU488222A1 (en) Integrator
GB1430822A (en) High speed signal integrator circuit
SU445157A1 (en) Implikator on optocoupler
SU454670A1 (en) Device for mutual synchronization of multivibrators
JPS5516540A (en) Pulse detection circuit
DK129489B (en) Electronic switching device for switching the polarity of two output terminals, depending on the direction of a current fed to the input.
DAN'KO et al. A transistor amplifier for microelectrode circuitry with an extended range of applicability(Two channel transistor amplifier design with negative capacitance correction for microelectrode applications)
JPS551662A (en) Memory unit
JPS57203319A (en) Pulse delaying circuit
JPS5637885A (en) Buffer circuit
JPS5361250A (en) Analog delay circuit
TALAMONTI Binary capacitors in MOS circuits(Binary capacitors made with p-channel MOS Si gate technology, discussing threshold voltage effects, structural characteristics, bootstrapping and artificial voltage enhancement)
GB1362378A (en) Circuits for forming the mean value of several input voltages
GB1236387A (en) Improvements in or relating to pulse transferring circuit arrangements