JPS5178665A - - Google Patents

Info

Publication number
JPS5178665A
JPS5178665A JP50132212A JP13221275A JPS5178665A JP S5178665 A JPS5178665 A JP S5178665A JP 50132212 A JP50132212 A JP 50132212A JP 13221275 A JP13221275 A JP 13221275A JP S5178665 A JPS5178665 A JP S5178665A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50132212A
Other languages
Japanese (ja)
Inventor
Aaru Kauaarieri Josefu
Bii Aadorei Debido
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5178665A publication Critical patent/JPS5178665A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
    • H03K17/0416—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit
    • H03K17/04163—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the output circuit in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H1/00—Constructional details of impedance networks whose electrical mode of operation is not specified or applicable to more than one type of network
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00—Networks using active elements
    • H03H11/46—One-port networks
    • H03H11/52—One-port networks simulating negative resistances
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/3565—Bistables with hysteresis, e.g. Schmitt trigger
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/16—Control of transmission; Equalising characterised by the negative-impedance network used
    • H04B3/18—Control of transmission; Equalising characterised by the negative-impedance network used wherein the network comprises semiconductor devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
JP50132212A 1974-12-24 1975-11-05 Pending JPS5178665A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US53608074A 1974-12-24 1974-12-24
US05/695,716 UST955006I4 (en) 1974-12-24 1976-06-14 Delay circuits using negative resistance CMOS circuits

Publications (1)

Publication Number Publication Date
JPS5178665A true JPS5178665A (en) 1976-07-08

Family

ID=27065031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50132212A Pending JPS5178665A (en) 1974-12-24 1975-11-05

Country Status (3)

Country Link
US (1) UST955006I4 (en)
JP (1) JPS5178665A (en)
FR (1) FR2296307A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5915567B2 (en) * 1979-07-19 1984-04-10 富士通株式会社 CMOS Schmitt circuit
JPS5619585A (en) * 1979-07-26 1981-02-24 Toshiba Corp Semiconductor memory unit
US4525640A (en) * 1983-03-31 1985-06-25 Ibm Corporation High performance and gate having an "natural" or zero threshold transistor for providing a faster rise time for the output
JPS60125015A (en) * 1983-12-12 1985-07-04 Hitachi Ltd Inverter circuit
US4682047A (en) * 1985-08-29 1987-07-21 Siemens Aktiengesellschaft Complementary metal-oxide-semiconductor input circuit
CA1296074C (en) * 1987-06-23 1992-02-18 David E. Fulkerson Fet capacitance driver logic circuit
US4952818A (en) 1989-05-17 1990-08-28 International Business Machines Corporation Transmission line driver circuits
IT1243691B (en) * 1990-07-27 1994-06-21 Sgs Thomson Microelectronics SINGLE TRANSISTOR LEVEL TRANSLATOR, WITH LOW DYNAMIC IMPEDANCE, IN CMOS TECHNOLOGY

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3911289A (en) * 1972-08-18 1975-10-07 Matsushita Electric Ind Co Ltd MOS type semiconductor IC device
US3832574A (en) * 1972-12-29 1974-08-27 Ibm Fast insulated gate field effect transistor circuit using multiple threshold technology

Also Published As

Publication number Publication date
FR2296307A1 (en) 1976-07-23
FR2296307B1 (en) 1977-12-16
UST955006I4 (en) 1977-02-01

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