USRE44608E1 - Solder joint flip chip interconnection - Google Patents
Solder joint flip chip interconnection Download PDFInfo
- Publication number
- USRE44608E1 USRE44608E1 US13/756,905 US201313756905A USRE44608E US RE44608 E1 USRE44608 E1 US RE44608E1 US 201313756905 A US201313756905 A US 201313756905A US RE44608 E USRE44608 E US RE44608E
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- US
- United States
- Prior art keywords
- lead
- substrate
- bump
- semiconductor device
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- 229910000679 solder Inorganic materials 0.000 title claims description 100
- 239000000758 substrate Substances 0.000 claims abstract description 142
- 239000000463 material Substances 0.000 claims abstract description 23
- 239000011133 lead Substances 0.000 claims description 51
- 239000004065 semiconductor Substances 0.000 claims description 43
- 238000002844 melting Methods 0.000 claims description 23
- 230000008018 melting Effects 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 9
- 229910052718 tin Inorganic materials 0.000 claims description 9
- 239000011135 tin Substances 0.000 claims description 9
- 230000005496 eutectics Effects 0.000 claims description 8
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 239000011800 void material Substances 0.000 claims 12
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims 4
- 238000000034 method Methods 0.000 abstract description 13
- 230000013011 mating Effects 0.000 abstract description 11
- 238000001465 metallisation Methods 0.000 abstract description 6
- 239000004020 conductor Substances 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 27
- 239000002184 metal Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 230000007935 neutral effect Effects 0.000 description 7
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- 239000000155 melt Substances 0.000 description 6
- 229910001128 Sn alloy Inorganic materials 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 230000035882 stress Effects 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 238000005094 computer simulation Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000008602 contraction Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- WIKSRXFQIZQFEH-UHFFFAOYSA-N [Cu].[Pb] Chemical compound [Cu].[Pb] WIKSRXFQIZQFEH-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009661 fatigue test Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000007716 flux method Methods 0.000 description 1
- 239000002241 glass-ceramic Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000010309 melting process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
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Definitions
- This invention relates to semiconductor packaging and, particularly, to flip chip interconnection.
- This invention relates to semiconductor packaging and, particularly, to flip chip interconnection.
- Flip chip packages include a semiconductor die mounted onto a package substrate with the active side of the die facing the substrate.
- the substrate is made up of a dielectric layer and at least one metal layer, patterned to provide substrate circuitry, which includes among other features traces (“leads”) leading to interconnect pads.
- the metal layer may be patterned by, for example, a mask-and etch process.
- interconnection of the circuitry in the die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die, and bonded to a corresponding (complementary) array of interconnect pads (often referred to as “capture pads”) on the substrate.
- the capture pads are typically much wider than the leads, and can be as wide as, for example, about 2 to 4 times the nominal or design width of the leads.
- the interconnect area on the capture pad is approximately equal to the interconnect area on the die pad.
- the areal density of electronic features on integrated circuits has increased enormously, and chips having a greater density of circuit features also may have a greater density of sites (“die pads”) for interconnection with the circuitry on a package substrate.
- the package is connected to underlying circuitry, such as a printed circuit board (e.g., a “motherboard”), in the device in which the package is employed, by way of second level interconnects (e.g., pins, secondary interconnect solder balls) between the package and the underlying circuit.
- the second level interconnects have a greater pitch than the flip chip interconnects, and so the routing on the substrate conventionally “fans out”.
- Significant technological advances in patterning the metal layer on the substrate have enabled construction of fine lines and spaces; but in the conventional arrangement space between adjacent pads limits the number of traces than can escape from the more inward capture pads in the array, and the fan out routing between the capture pads beneath the die and the external pins of the package is conventionally formed on multiple metal layers within the package substrate.
- substrates having multiple layers may be required to achieve routing between the die pads and the second level interconnects on the package.
- the escape routing pattern typically introduces additional electrical parasitics, because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.
- Flip chip interconnection is commonly used in a wide variety of integrated circuit designs, including for example ASIC, GPU, Chipset, DSP, FPGA.
- BoNP or BoL approaches can provide more efficient routing of traces on the substrate.
- the signal routing can be formed entirely in a single metal layer of the substrate. This can reduce the number of layers in the substrate, and forming the signal traces in a single layer also permits relaxation of some of the via, line and space design rules that the substrate must meet. This simplification of the substrate greatly reduces the overall cost of the flip chip package.
- the bump-on-lead architecture also helps eliminate such features as vias and “stubs” from the substrate design, and enables a microstrip controlled impedance electrical environment for signal transmission, thereby greatly improving performance.
- BoL or BoNP flip chip interconnection can be at least as reliable as a conventional bond on capture pad interconnect.
- interconnect structures formed on narrower leads that is, more sharply tapered interconnect structures—can be more reliable than interconnect structures formed on less narrow leads.
- the CTE of the die differs significantly from the CTE of the substrate
- improved reliability can result from configuring the interconnect so that the interconnect structure is tapered, and the area of contact of the solder with the site on the lead is significantly less than the area of contact of the solder with the die pad.
- the contact at the site on the lead can be narrower as a result of a narrow dimension of the lead at the site (BoL) or of a narrow pad at the site (BoNP); or the contact at the site on the lead can be narrow as a consequence of masking a larger pad or otherwise limiting the solder-wettable area of a larger pad.
- the CTE of the substrate is significantly greater than the CTE of the die; and the material of the interconnect structure is selected to be close to that of the substrate.
- the CTE of a laminate (organic) substrate is typically in a range about 16-18 ppm/degree C.; the CTE of silicon is about 2-3 ppm/degree C.; the CTE of “glass ceramic” (in earlier use for substrates) is about 3-4 ppm/degree C.; the CTE of a co-fired ceramic (in use in multilayer substrates—as many as 16-18 layers, for example) is about 8-8.5 ppm/degree C.
- the CTE of a laminate (organic) substrate is typically in a range about 16-18 ppm/degree C., and so a significant CTE mismatch exists between silicon die and organic laminate or build-up substrates.
- the die is silicon-based
- the substrate is an organic laminate or build-up substrate
- the tapered interconnect structure has a CTE in the range of about 18-28 ppm/degree C.
- the invention features a flip chip interconnection having tapered interconnect structures, in which a width of the connection of the interconnect structure with a die pad is greater than a width of the connection of the interconnect structure with a site on a lead.
- the connection at the die pad is about 1.5 times as wide as the connection at the lead, or is about 2 times as wide as the connection at the lead, or is about 3 times as wide as the connection at the lead, or is about 4 times as wide as the connection at the lead.
- the width of the connection at the die pad can be in a range about 50 ⁇ m to about 150 ⁇ m; die pads in common use have widths about 110 (or 120) ⁇ m and about 90 ⁇ m.
- the width of the connection at the site at the lead can be in a range about 20 ⁇ m to about 100 ⁇ m; some standard leads have widths at the site about 50 ⁇ m, or about 40 ⁇ m, or about 30 ⁇ m. Where the CTE mismatch between the die and the substrate is greater, a more sharply tapering interconnect structure may prove more reliable; where the CTE mismatch is less, a less sharply tapered interconnect structure may prove suitable.
- the interconnect structure is a composite structure, including a higher-melting bump connected to the die pad, and a lower-melting solder connecting the bump to the site on the lead.
- the lower-melting component of the composite structure can be provided as a cap on the bump; or, the lower-melting component can be provided on the interconnect site (for example as a solder paste, or a plated spot); or a lower-melting material could be provided on each the bump and the site.
- the higher-melting bump can be of a material that is substantially non-collapsible at the reflow temperatures employed in making the interconnect.
- the higher-melting bump can be, for example, a high-lead solder (such as a lead-tin alloy having high lead content), or copper, or gold, or nickel, or a combination of these.
- the lower-melting solder can be, for example, a eutectic solder, which may be tin-based, including tin and alloys of tin such as silver, copper, or lead, or a combination of these.
- the bump could be entirely of a material that melts at the reflow temperature.
- the bump can be affixed to the die pad; or, it can be formed on the die pad in situ, by printing or plating the bump material at the die pads and then heating to form the bumps.
- the invention features a flip chip package including a die having interconnect pads in an active surface, and a substrate having interconnect sites on electrically conductive traces in a die attach surface, in which tapered interconnect structures connect the die pads to the sites.
- the sites include locations in the leads (BoL); in some embodiments the sites include narrow pads in the leads (BoNP); in some embodiments the sites include small-area portions of capture pads.
- the bump-on-lead interconnection is formed according to methods of the invention either with or without use of a solder mask to confine the molten solder during a re-melt stage in the process. Avoiding the need for a solder mask can allow for finer interconnection geometry.
- the substrate is further provided with a solder mask having openings over the interconnect sites on the leads. In some embodiments the substrate is further provided with solder paste on the leads at the interconnect sites.
- the invention features a substrate for BoL or BoNP flip chip interconnection, in which the lengthwise dimension of the interconnect site (the mating portion of the lead or narrow pad) is oriented in a direction approximately aligned toward the thermally neutral point of the die, or deviating less than about 45° (more usually, less than about 20°; still more usually, less than about 10°) from such an alignment.
- the invention features a method for forming flip chip interconnection, by providing a substrate having interconnect sites in conductive traces formed in a die attach surface, providing a die having bumps attached to interconnect pads in an active surface; providing a fusible conductive material on the bumps or on the interconnect sites (or on each the bumps and the interconnect sites); supporting the substrate and the die; positioning the die with the active side of the die toward the die attach surface of the substrate, and aligning the die and substrate and moving one toward the other so that the bumps contact the corresponding sites; and melting and then re-solidifying the fusible material, forming a metallurgical interconnection between the bump and the trace.
- the method further includes forming an underfill between the die and the substrate.
- the invention features a method for forming flip chip interconnection, by providing a substrate having traces formed in a die attach surface and having a solder mask having openings over interconnect sites on the leads, and a die having bumps attached to interconnect pads in an active surface; supporting the substrate and the die; positioning the die with the active side of the die toward the die attach surface of the substrate, and aligning the die and substrate and moving one toward the other so that the bumps contact the corresponding traces (leads) on the substrate; melting and then re-solidifying to form the interconnection between the bump and the interconnect site on the trace.
- the solder bump includes a collapsible solder portion, and the melt and solidifying step melts the bump to form the interconnection on the interconnect site.
- the substrate is further provided with a solder paste on the interconnect site, and the step of moving the die and the substrate toward one another effects a contact between the bump and the solder on the site, and the melt and solidifying step melts the solder on the site to form the interconnection.
- the invention features a method for forming flip chip interconnection, by providing a substrate having traces formed in a die attach surface and having a solder mask having openings over interconnect sites on the leads and having solder paste on the leads at the interconnect sites, and a die having bumps attached to interconnect pads in an active surface; supporting the substrate and the die; positioning the die with the active side of the die toward the die attach surface of the substrate, and aligning the die and substrate and moving one toward the other so that the bumps contact the solder paste on the corresponding traces (leads) on the substrate; and melting and then re-solidifying the solder paste, forming a metallurgical interconnection between the bump and the trace.
- the invention features a flip chip package, including interconnections formed as described above, and additionally including forming an underfill between the die and the substrate.
- FIG. 1A is a diagrammatic sketch of a portion of a conventional bump-on-capture pad (“BoC”) flip chip interconnection, in a sectional view parallel to the plane of the package substrate surface.
- BoC bump-on-capture pad
- FIG. 1B is a diagrammatic sketch in a plan view showing a die mounted on a substrate in a flip chip manner, in which the die and the substrate have significantly different thermal expansion coefficients, and showing dimensional change of the die in relation to the substrate as a result of change in temperature.
- FIG. 2A is a diagrammatic sketch showing a portion of a flip chip interconnection according to the invention, in a sectional view perpendicular to the plane of the package substrate surface and generally transverse to the long axes of the leads.
- FIG. 2B is a diagrammatic sketch showing a portion of a flip chip interconnection according to the invention, in a sectional view perpendicular to the plane of the package substrate surface and generally parallel long axes of the lead.
- FIGS. 3A and 3B are diagrammatic sketches as in FIGS. 2B and 2B , respectively indicating dimensional references for various of the features.
- FIG. 4 is a diagrammatic sketch in a sectional view of an embodiment of the invention, showing an underfill.
- the conventional flip chip interconnection is made by using a melting process to join the bumps (conventionally, solder bumps) onto the mating surfaces of the corresponding capture pads and, accordingly, this is known as a “bump-on-capture pad” (“BoC”) interconnect.
- BoC bump-on-capture pad
- Two features are evident in the BOC design: first, a comparatively large capture pad is required to mate with the bump on the die; second, an insulating material, typically known as a “solder mask” is required to confine the flow of solder during the interconnection process.
- the solder mask opening may define the contour of the melted solder at the capture pad (“solder mask defined”), or the solder contour may not be defined by the mask opening (“non-solder mask defined”).
- solder mask openings have wide tolerance ranges. Consequently, for a solder mask defined bump configuration, the capture pad must be large (typically considerably larger than the design size for the mask opening), to ensure that the mask opening will be located on the mating surface of the pad; and for a non-solder mask defined bump configuration, the solder mask opening must be larger than the capture pad.
- the width of capture pads is typically about the same as the ball (or bump) diameter, and can be as much as two to four times wider than the trace width. This results in considerable loss of routing space on the top substrate layer. In particular, for example, the “escape routing pitch” is much bigger than the finest trace pitch that the substrate technology can offer. This means that a significant number of pads must be routed on lower substrate layers by means of short stubs and vias, often beneath the footprint of the die, emanating from the pads in question.
- FIG. 1A shows a portion of a conventional flip chip package, in diagrammatic sectional view; the partial sectional view in FIG. 1A is taken in a plane perpendicular to the package substrate surface.
- a die attach surface of the package substrate includes a patterned electrically conductive layer formed on a dielectric layer 10 .
- the metal layer is patterned to form leads and capture pads 16 .
- An insulating layer 11 typically termed a “solder mask”, covers the die attach surface of the substrate; the solder mask is usually constructed of a photodefinable material, and is patterned by conventional photoresist patterning techniques to have openings, indicated at 12 , leaving the mating surfaces of the capture pads 16 exposed.
- Interconnect bumps 17 attached to pads (so-called “under bump metallization”) 18 on the active side of the die 14 are joined to the mating surfaces of corresponding capture pads 16 on the substrate to form appropriate electrical interconnection between the circuitry on the die and the leads on the substrate.
- the active side of the die 14 is covered, except at the contact surfaces of the die pads 16 , with a die passivation layer 15 , which may be, for example, a polyimide layer.
- an underfill material (not shown in these FIGs.) is introduced into the space between the die and the substrate, mechanically stabilizing the interconnects and protecting the features between the die and the substrate.
- signal escape traces in the upper metal layer of the substrate lead from their respective capture pads across the die edge location, and away from the die footprint.
- the capture pads are typically three times greater than the trace width.
- the capture pads are arranged in a 210 ⁇ m two-row area array pitch in a solder mask defined configuration, with one signal trace between capture pads in the marginal row, resulting in an effective escape pitch about 105 ⁇ m, for example.
- the interconnect sites can be arranged in a 210 ⁇ m three-row area array pitch, with two signal traces between sites in the outer row, resulting in an effective escape pitch about 70 ⁇ m.
- BoL interconnection also further opens the prospect of routing a considerable proportion of flip chip designs in conventional through-hole laminate substrates, inasmuch as laminate substrates have line/space capacities of about 40 ⁇ m/40 ⁇ m (or better). This could provide for substantial cost reduction.
- FIG. 1A shows a solder mask defined solder contour.
- the molten solder tends to “wet” the metal of the capture pads, and the solder tends to “run out” over any contiguous metal surfaces that are not masked.
- the solder tends to flow along the underlying pad (and exposed contiguous lead), and in the solder mask defined contour the solder flow is limited by the solder mask, for example by the width of the opening 12 in the solder mask 11 .
- a non-solder mask defined solder contour may alternatively be employed, in which the flow of solder along the lead is limited at least in part by a patterned deposition of non-solder-wettable material on the lead surface.
- Thermal movement (in the x-y plane) of die pads on the die attach surface of the die in relation to the corresponding points on the substrate can result in stresses to the interconnections between the die pad and the site on the substrate.
- Dimensional change, resulting from temperature changes, of a flip chip mounted die in relation to a substrate is shown diagrammatically (and with dimensions exaggerated) in plan view in FIG. 1 B. In this example, there is a significant mismatch between the CTE of the die and the CE of the substrate. A portion of the substrate is shown at 11 .
- a footprint of the die at a higher temperature is shown at 14 B; a footprint of the die at a lower temperature is shown at 14 B.
- registration of any point on the active surface of the die 14 with respect to a corresponding underlying point on the die attach surface of the substrate 11 will change as the dimensions of the die and substrate change differentially as a result of thermal stress.
- the thermally neutral point may approximately coincide with the geometric center of the die surface.
- thermal movement depends at least in part upon the distance of that point from the thermally neutral point on the die; accordingly, there is greater relative thermal movement at points nearer the edges of the die (and, particularly, near the corners of the die) than at points nearer the thermally neutral point.
- Movement (in the x-y plane) of a die pad in relation to an underlying contact pad can result in stresses to the interconnection between the pad and the contact pad. Where the movement passes a limit, something has to give: failure of the interconnect can result. In conventional flip chip interconnects, where there is a thermal mismatch between the die and the substrate, failure typically occurs at the joint between the solder bump and the die pad. And, in conventional flip chip interconnects, where there is a thermal mismatch between the die and the substrate, even if there is no failure, thermal stress at the die pad can cause damage to the die.
- the area (diameter) of the interconnect pad on the substrate is approximately equal to the area (diameter) of the interconnect pad on the die, as shown by way of example in FIG. 1A .
- the primary locus of stress is as referenced at 19 in FIG. 1A .
- the thermal movement of the die in relation to the substrate is as shown at arrow 13 in FIG. 1A
- the greatest (“Maximum”) plastic strain on the interconnect is predicted by the computer model to be at the “leading edge” 19 of the connection (interface) between the solder 17 and the die pad (UBM) 18 .
- the arrow might be positioned at the substrate, but reversed, showing relative movement of the substrate in the opposite direction; the relative movement is pointed out here in relation to the die, because the thermally neutral point is established in relation to the die footprint.
- a BoL interconnection according to an embodiment of the invention is shown by way of example in sectional views perpendicular to the surface of the substrate in FIGS. 2A and 2B .
- FIG. 2A two solder joints are shown in a sectional view transverse to the lead, and in FIG. 2B , one solder joint is shown in a sectional view parallel to the lead.
- a die attach surface of the package substrate includes a patterned electrically conductive layer formed on a dielectric layer 20 .
- the metal layer is patterned to form leads having interconnect sites 26 .
- An insulating layer 21 covers the die attach surface of the substrate; the solder mask is usually constructed of a photodefinable material, and is patterned by conventional photoresist patterning techniques to have openings, indicated at 22 , leaving the top surface and the sides of the lead (the “mating surfaces”) exposed at the interconnect site 26 .
- Interconnect structures 27 are attached to pads (so-called “under bump metallization”) 28 on the active side of the die 24 and are joined to the mating surfaces of the leads at the interconnect sites 26 on the substrate to form appropriate electrical interconnection between the circuitry on the die and the leads on the substrate.
- the active side of the die 24 is covered, except at the contact surfaces of the die pads 26 , with a die passivation layer (such as a polyimide layer) 25 .
- a die passivation layer such as a polyimide layer
- an underfill material is introduced into the space between the die and the substrate, mechanically stabilizing the interconnects and protecting the features between the die and the substrate.
- FIG. 2B an interconnect is shown in a sectional view taken along the line 2 B- 2 B in FIG. 2A . (In this view, the solder mask 21 is not shown.) This view shows the solder of interconnect structure 27 covering the sides of the lead 26 .
- interconnect structures according to some embodiments can be made using entirely fusible materials, or using composite bumps, or using a solder-on-lead method, as described above.
- Composite interconnect structures have at least two bump portions, made of different materials, including one which is collapsible under reflow conditions, and one which is substantially non-collapsible under reflow conditions.
- the non-collapsible portion is attached to the interconnect pad on the die; typical conventional materials for the non-collapsible portion include various solders having a high lead (Pb) content, for example, (such as a lead-tin alloy having high lead content), or copper, or gold, or nickel, or a combination of these.
- Pb lead
- the collapsible portion is joined to the non-collapsible portion, and it is the collapsible portion that makes the connection with the interconnect site on the lead.
- Typical conventional materials for the collapsible portion of the composite bump include eutectic solders, for example, which may be tin-based, including tin and alloys of tin such as silver, copper, or lead, or a combination of these.
- This structure can be formed in the following way, for example.
- Solder bumps (or balls) are attached to or formed on the die pads (under bump metallization or UBM). Solder is applied to the interconnect sites on the traces, for example in the form of a solder paste.
- the die is oriented, active side facing the mounting surface of the substrate, so that the bumps on the die are aligned with the respective interconnect sites on the leads, and the die is moved toward the substrate to bring the bumps into contact with the solder on the leads.
- the assembly is then heated, to reflow the solder and form the connection at the interconnect site. As the solder on the lead reflows, it wicks to the solder-wettable surface of the solder bump, and to the solder-wettable mating surfaces of the lead.
- the surface of the substrate dielectric 20 is not solder-wettable, and the solder tends to make little or no contact with the substrate dielectric.
- the tapered form of the connection structure (as viewed in section across the lead, as in FIG. 2A ) results from the narrow dimension of the lead at the interconnect site, and the wicking of the solder during reflow.
- the bumps may be formed of a high-lead (high-Pb) solder (e.g., 97% lead, 2% tin), and the solder on the interconnect site can be a eutectic solder. Reflow in some such examples can be carried out at a peak temperature of 235° C., employing flux in a jet flux method.
- high-Pb high-lead
- solder on the interconnect site can be a eutectic solder.
- Reflow in some such examples can be carried out at a peak temperature of 235° C., employing flux in a jet flux method.
- the width of the leads may vary over their length, no particular widening of the leads is formed at the interconnect sites; in a BoNP construct, the leads may be widened to a limited extent at the interconnect sites.
- the sides of the lead—as well as the top—(the mating surfaces) are exposed to the solder at the interconnect site, and during reflow solder wicks to the solder-wettable surfaces.
- solder mask is employed in these embodiments to limit the flow of solder along the length of the leads.
- the leads may be treated to be non-solder-wettable along portions of the leads adjacent the mating surfaces at the interconnect sites, so that flow of solder away from the interconnect sites along the leads is limited without use of a solder mask.
- any of a variety of substrate types can be employed according to the invention, including for example build-up film substrates and laminate substrates.
- a 1-2-1 high-density build-up substrate can be used (such as an Ajinomoto Build-Up Film, or other high density substrate build-up film), or a 4-layer laminate substrate can be used.
- FIGS. 3A and 3B are similar to FIGS. 2A and 2B , marked up for reference to dimensions of certain of the features.
- the features are referenced as follows: H, interconnect height as measured from the die surface to the solder mask surface; D, bump diameter at half the interconnect height (H/2); UD, under bump metallization diameter; OPx, mask opening width in the x-direction (across the lead); OPy, mask opening width in the y-direction (along the lead); CW, width of the (Copper) lead at the interconnect site; CH, thickness (height) of the lead at the interconnect site; T, solder mask thickness.
- a BoL construct according to the invention may have the following dimensions, for example: UD, 90 ⁇ m; D, 0.110 ⁇ m; H, 75 ⁇ m; T, 40 ⁇ m; CW, 30 ⁇ m, CT, 20 ⁇ m.
- a BoL construct having these dimensions formed on an Ajinomoto Build-Up Film (ABF) 1-2-1 substrate has performed well in fatigue failure tests. This result is surprising, because it is conventionally believed that preferred interconnects should have a shape and support area for the joint at the die side approximately equal to that on the substrate side (bond-on-capture pad, or BoC).
- a conventional (BoC) construct having the following dimensions was used for the FET analysis: UD, 90 ⁇ m; D, 0.110 ⁇ m; H, 75 ⁇ m; OPx, 95 ⁇ m; T, 40 ⁇ m; CW, 115 ⁇ m, CT, 20 ⁇ m.
- the analysis showed a considerable concentration of maximum strain at the interface with the die pad in the BoC model, and a maximum plastic strain in a zone on the “leading edge” of the structure at the die pad (see, FIG. 1A ). In the BoL model, the maximum plastic strain is reduced, and it is shifted away from the die pad interface.
- a flip chip package according to the invention includes an underfill, between the substrate 20 and the die 24 , as shown in one embodiment at 47 in FIG. 4 .
- the contact of the interconnect structure 27 with the solder mask can prevent flow of the underfill material into the region in the solder mask opening immediately adjacent the interconnection structure with the site on the trace.
- the existence of voids can be undesired and, accordingly, it may be preferred to reduce the thickness of the solder mask, as shown at Ts in FIG. 4 , to provide an opening between the solder mask opening and the interconnect structure 27 for flow of the underfill material into this region. Accordingly, in the embodiment shown in FIG. 4 , there are substantially no voids in the underfill.
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Abstract
Description
Claims (25)
Priority Applications (1)
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US13/756,905 USRE44608E1 (en) | 2003-11-10 | 2013-02-01 | Solder joint flip chip interconnection |
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US51886403P | 2003-11-10 | 2003-11-10 | |
US53391803P | 2003-12-31 | 2003-12-31 | |
US10/985,654 US7368817B2 (en) | 2003-11-10 | 2004-11-10 | Bump-on-lead flip chip interconnection |
US66520805P | 2005-03-25 | 2005-03-25 | |
US59764805P | 2005-12-14 | 2005-12-14 | |
US11/388,755 US20060216860A1 (en) | 2005-03-25 | 2006-03-24 | Flip chip interconnection having narrow interconnection sites on the substrate |
US11/640,468 US20070105277A1 (en) | 2004-11-10 | 2006-12-14 | Solder joint flip chip interconnection |
US12/624,482 US8129841B2 (en) | 2006-12-14 | 2009-11-24 | Solder joint flip chip interconnection |
US13/756,905 USRE44608E1 (en) | 2003-11-10 | 2013-02-01 | Solder joint flip chip interconnection |
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Cited By (1)
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---|---|---|---|---|
US9902006B2 (en) | 2014-07-25 | 2018-02-27 | Raytheon Company | Apparatus for cleaning an electronic circuit board |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7602062B1 (en) * | 2005-08-10 | 2009-10-13 | Altera Corporation | Package substrate with dual material build-up layers |
US8502362B2 (en) | 2011-08-16 | 2013-08-06 | Advanced Analogic Technologies, Incorporated | Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance |
US20090250814A1 (en) * | 2008-04-03 | 2009-10-08 | Stats Chippac, Ltd. | Flip Chip Interconnection Structure Having Void-Free Fine Pitch and Method Thereof |
US20100025862A1 (en) * | 2008-07-29 | 2010-02-04 | Peter Alfred Gruber | Integrated Circuit Interconnect Method and Apparatus |
TWI455263B (en) * | 2009-02-16 | 2014-10-01 | Ind Tech Res Inst | Chip package structure and chip package method |
WO2013157197A1 (en) | 2012-04-19 | 2013-10-24 | パナソニック株式会社 | Electronic component mounting method and electronic component mounting line |
US20160029486A1 (en) * | 2014-07-24 | 2016-01-28 | Samsung Electro-Mechanics Co., Ltd. | Solder joint structure and electronic component module including the same |
US9842819B2 (en) | 2015-08-21 | 2017-12-12 | Invensas Corporation | Tall and fine pitch interconnects |
Citations (141)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04355933A (en) | 1991-02-07 | 1992-12-09 | Nitto Denko Corp | Packaging structure of flip chip |
US5186383A (en) | 1991-10-02 | 1993-02-16 | Motorola, Inc. | Method for forming solder bump interconnections to a solder-plated circuit trace |
US5378859A (en) | 1992-03-02 | 1995-01-03 | Casio Computer Co., Ltd. | Film wiring board |
US5386624A (en) | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
US5434410A (en) | 1992-05-29 | 1995-07-18 | Texas Instruments Incorporated | Fine-grain pyroelectric detector material and method |
US5508561A (en) | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
US5519580A (en) | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
JPH0997791A (en) | 1995-09-27 | 1997-04-08 | Internatl Business Mach Corp <Ibm> | Bump structure, formation of bump and installation connection body |
US5650595A (en) | 1995-05-25 | 1997-07-22 | International Business Machines Corporation | Electronic module with multiple solder dams in soldermask window |
US5710071A (en) | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
US5795818A (en) | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
JPH10256307A (en) | 1997-03-13 | 1998-09-25 | Ngk Spark Plug Co Ltd | Wiring board with semiconductor device, wiring board and manufacture thereof |
US5844782A (en) | 1994-12-20 | 1998-12-01 | Sony Corporation | Printed wiring board and electronic device using same |
US5854514A (en) | 1996-08-05 | 1998-12-29 | International Buisness Machines Corporation | Lead-free interconnection for electronic devices |
US5869886A (en) | 1996-03-22 | 1999-02-09 | Nec Corporation | Flip chip semiconductor mounting structure with electrically conductive resin |
US5872399A (en) | 1996-04-01 | 1999-02-16 | Anam Semiconductor, Inc. | Solder ball land metal structure of ball grid semiconductor package |
US5889326A (en) | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
JPH11145176A (en) | 1997-11-11 | 1999-05-28 | Fujitsu Ltd | Method for forming solder bump and method for forming preliminary solder |
US5915169A (en) | 1995-12-22 | 1999-06-22 | Anam Industrial Co., Ltd. | Semiconductor chip scale package and method of producing such |
JPH11233571A (en) | 1998-02-12 | 1999-08-27 | Hitachi Ltd | Semiconductor device, underfill material, and thermosetting film material |
US5985456A (en) | 1997-07-21 | 1999-11-16 | Miguel Albert Capote | Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits |
US6002172A (en) | 1997-03-12 | 1999-12-14 | International Business Machines Corporation | Substrate structure and method for improving attachment reliability of semiconductor chips and modules |
JP2000031204A (en) | 1998-07-07 | 2000-01-28 | Ricoh Co Ltd | Manufacture of semiconductor package |
JP2000349194A (en) | 1999-06-08 | 2000-12-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
US6201305B1 (en) | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
US6218630B1 (en) | 1997-06-30 | 2001-04-17 | Fuji Photo Film Co., Ltd. | Printed circuit board having arrays of lands arranged inside and outside of each other having a reduced terminal-pitch |
US6229209B1 (en) | 1995-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Chip carrier |
US6228466B1 (en) | 1997-04-11 | 2001-05-08 | Ibiden Co. Ltd. | Printed wiring board and method for manufacturing the same |
JP2001156203A (en) | 1999-11-24 | 2001-06-08 | Matsushita Electric Works Ltd | Printed wiring board for mounting semiconductor chip |
US6259163B1 (en) | 1997-12-25 | 2001-07-10 | Oki Electric Industry Co., Ltd. | Bond pad for stress releif between a substrate and an external substrate |
US20010013423A1 (en) | 1996-10-31 | 2001-08-16 | Hormazdyar M. Dalal | Flip chip attach on flexible circuit carrier using chip with metallic cap on solder |
US6281450B1 (en) | 1997-06-26 | 2001-08-28 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
US6297560B1 (en) | 1996-10-31 | 2001-10-02 | Miguel Albert Capote | Semiconductor flip-chip assembly with pre-applied encapsulating layers |
US6324754B1 (en) | 1998-03-25 | 2001-12-04 | Tessera, Inc. | Method for fabricating microelectronic assemblies |
US6329605B1 (en) | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
US6333206B1 (en) | 1996-12-24 | 2001-12-25 | Nitto Denko Corporation | Process for the production of semiconductor device |
US6335571B1 (en) | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US6335568B1 (en) | 1998-10-28 | 2002-01-01 | Seiko Epson Corporation | Semiconductor device and method of fabrication thereof, circuit board, and electronic equipment |
US20020041036A1 (en) | 1998-02-03 | 2002-04-11 | Smith John W. | Microelectronic assemblies with composite conductive elements |
US6383916B1 (en) | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
US6396707B1 (en) | 1999-10-21 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Ball grid array package |
US6409073B1 (en) | 1998-07-15 | 2002-06-25 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Method for transfering solder to a device and/or testing the device |
US6441316B1 (en) | 1999-08-27 | 2002-08-27 | Mitsubishi Denki Kabushiki Kaisha | Printed-circuit board and a semiconductor module, and a manufacturing process of the semiconductor module |
US20020121706A1 (en) | 2000-12-28 | 2002-09-05 | Matsushita Electic Works, Ltd. | Semiconductor-chip mounting substrate and method of manufacturing the same |
US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
JP2002270732A (en) | 2001-03-13 | 2002-09-20 | Sharp Corp | Electronic component with underfill material |
US6458622B1 (en) | 1999-07-06 | 2002-10-01 | Motorola, Inc. | Stress compensation composition and semiconductor component formed using the stress compensation composition |
US6462425B1 (en) | 1999-04-19 | 2002-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US20020155637A1 (en) | 2001-04-20 | 2002-10-24 | Shih-Chang Lee | Flip chip interconnected structure and a fabrication method thereof |
US6472608B2 (en) | 2000-02-18 | 2002-10-29 | Nec Corporation | Semiconductor device |
US20020192865A1 (en) | 1997-03-27 | 2002-12-19 | Hitachi, Ltd. And Hitachi Hokkai Semiconductor, Ltd. | Process for mounting electronic device and semiconductor device |
US6518674B2 (en) | 1999-09-23 | 2003-02-11 | International Business Machines Corporation | Temporary attach article and method for temporary attach of devices to a substrate |
US20030049411A1 (en) | 2001-09-10 | 2003-03-13 | Delphi Technologies,Inc | No-flow underfill material and underfill method for flip chip devices |
US20030067084A1 (en) | 2000-06-28 | 2003-04-10 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US6573610B1 (en) | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
US20030127734A1 (en) | 2002-01-07 | 2003-07-10 | Jin-Yuan Lee | Cylindrical bonding structure and method of manufacture |
US6600234B2 (en) | 1999-02-03 | 2003-07-29 | Casio Computer Co., Ltd. | Mounting structure having columnar electrodes and a sealing film |
US6608388B2 (en) | 2001-11-01 | 2003-08-19 | Siliconware Precision Industries Co., Ltd. | Delamination-preventing substrate and semiconductor package with the same |
WO2003071842A1 (en) | 2001-12-26 | 2003-08-28 | Motorola, Inc. | Method of mounting a semiconductor die on a substrate without using a solder mask |
US20030168748A1 (en) | 2002-03-08 | 2003-09-11 | Mitsuaki Katagiri | Semiconductor device |
US6664483B2 (en) | 2001-05-15 | 2003-12-16 | Intel Corporation | Electronic package with high density interconnect and associated methods |
US6678948B1 (en) | 1998-09-01 | 2004-01-20 | Robert Bosch Gmbh | Method for connecting electronic components to a substrate, and a method for checking such a connection |
US20040035909A1 (en) | 2002-08-22 | 2004-02-26 | Shing Yeh | Lead-based solder alloys containing copper |
US6710458B2 (en) | 2000-10-13 | 2004-03-23 | Sharp Kabushiki Kaisha | Tape for chip on film and semiconductor therewith |
US20040056341A1 (en) | 2002-09-19 | 2004-03-25 | Kabushiki Kaisha Toshiba | Semiconductor device, semiconductor package member, and semiconductor device manufacturing method |
US6734557B2 (en) | 2002-03-12 | 2004-05-11 | Sharp Kabushiki Kaisha | Semiconductor device |
US20040105223A1 (en) | 2001-03-19 | 2004-06-03 | Ryoichi Okada | Method of manufacturing electronic part and electronic part obtained by the method |
JP2004165283A (en) | 2002-11-11 | 2004-06-10 | Fujitsu Ltd | Semiconductor device |
US20040108135A1 (en) | 2002-10-11 | 2004-06-10 | Takeshi Ashida | Circuit board, mounting structure of ball grid array, electro-optic device and electronic device |
US6768190B2 (en) | 2002-01-25 | 2004-07-27 | Advanced Semiconductor Engineering, Inc. | Stack type flip-chip package |
JP2004221205A (en) | 2003-01-10 | 2004-08-05 | Seiko Epson Corp | Method for mounting semiconductor chip, semiconductor mounting substrate, electronic device and electronic equipment |
US6774497B1 (en) | 2003-03-28 | 2004-08-10 | Freescale Semiconductor, Inc. | Flip-chip assembly with thin underfill and thick solder mask |
US6780682B2 (en) | 2001-02-27 | 2004-08-24 | Chippac, Inc. | Process for precise encapsulation of flip chip interconnects |
US6780673B2 (en) | 2002-06-12 | 2004-08-24 | Texas Instruments Incorporated | Method of forming a semiconductor device package using a plate layer surrounding contact pads |
US6787918B1 (en) | 2000-06-02 | 2004-09-07 | Siliconware Precision Industries Co., Ltd. | Substrate structure of flip chip package |
US6809262B1 (en) | 2003-06-03 | 2004-10-26 | Via Technologies, Inc. | Flip chip package carrier |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US6821878B2 (en) | 2003-02-27 | 2004-11-23 | Freescale Semiconductor, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
US20040232562A1 (en) | 2003-05-23 | 2004-11-25 | Texas Instruments Incorporated | System and method for increasing bump pad height |
US6849944B2 (en) | 2003-05-30 | 2005-02-01 | Texas Instruments Incorporated | Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad |
JP2005028037A (en) | 2003-07-11 | 2005-02-03 | Fuji Photo Film Co Ltd | Medical image processing device and medical image processing method |
US20050046041A1 (en) | 2003-08-29 | 2005-03-03 | Advanced Semiconductor Engineering, Inc. | Integrated circuit device with embedded passive component by flip-chip connection and method for manufacturing the same |
US6870276B1 (en) | 2001-12-26 | 2005-03-22 | Micron Technology, Inc. | Apparatus for supporting microelectronic substrates |
JP2005109187A (en) | 2003-09-30 | 2005-04-21 | Tdk Corp | Flip chip packaging circuit board and its manufacturing method, and integrated circuit device |
US6888255B2 (en) | 2003-05-30 | 2005-05-03 | Texas Instruments Incorporated | Built-up bump pad structure and method for same |
US6913948B2 (en) | 1999-11-10 | 2005-07-05 | International Business Machines Corporation | Partially captured oriented interconnections for BGA packages and a method of forming the interconnections |
US20050248037A1 (en) | 2004-05-06 | 2005-11-10 | Advanced Semiconductor Engineering, Inc. | Flip-chip package substrate with a high-density layout |
US7005743B2 (en) | 2000-04-28 | 2006-02-28 | Sony Corporation | Semiconductor device using bumps, method for fabricating same, and method for forming bumps |
US7005750B2 (en) | 2003-08-01 | 2006-02-28 | Advanced Semiconductor Engineering, Inc. | Substrate with reinforced contact pad structure |
US7005585B2 (en) | 2002-09-02 | 2006-02-28 | Murata Manufacturing Co., Ltd. | Mounting board and electronic device using same |
US7049705B2 (en) | 2003-07-15 | 2006-05-23 | Advanced Semiconductor Engineering, Inc. | Chip structure |
US7057284B2 (en) | 2004-08-12 | 2006-06-06 | Texas Instruments Incorporated | Fine pitch low-cost flip chip substrate |
US7064435B2 (en) | 2003-07-29 | 2006-06-20 | Samsung Electronics Co., Ltd. | Semiconductor package with improved ball land structure |
US20060131758A1 (en) | 2004-12-22 | 2006-06-22 | Stmicroelectronics, Inc. | Anchored non-solder mask defined ball pad |
US7098407B2 (en) | 2003-08-23 | 2006-08-29 | Samsung Electronics Co., Ltd. | Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate |
US20060192294A1 (en) | 2004-11-15 | 2006-08-31 | Chippac, Inc | Chip scale package having flip chip interconnect on die paddle |
US7102222B2 (en) | 2003-10-02 | 2006-09-05 | Siliconware Precision Industries Co., Ltd. | Conductive trace structure and semiconductor package having the conductive trace structure |
US7102239B2 (en) | 2003-08-18 | 2006-09-05 | Siliconware Precision Industries Co., Ltd. | Chip carrier for semiconductor chip |
US20060202331A1 (en) | 2005-03-09 | 2006-09-14 | Wen-Hung Hu | Conductive bump structure of circuit board and method for fabricating the same |
US7112524B2 (en) | 2003-09-29 | 2006-09-26 | Phoenix Precision Technology Corporation | Substrate for pre-soldering material and fabrication method thereof |
US7173828B2 (en) | 2003-07-28 | 2007-02-06 | Siliconware Precision Industries Co., Ltd. | Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure |
US7224073B2 (en) | 2004-05-18 | 2007-05-29 | Ultratera Corporation | Substrate for solder joint |
US7242099B2 (en) | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
US20070200234A1 (en) | 2006-02-28 | 2007-08-30 | Texas Instruments Incorporated | Flip-Chip Device Having Underfill in Controlled Gap |
US7271484B2 (en) | 2003-09-25 | 2007-09-18 | Infineon Technologies Ag | Substrate for producing a soldering connection |
US7294929B2 (en) | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
US7317245B1 (en) | 2006-04-07 | 2008-01-08 | Amkor Technology, Inc. | Method for manufacturing a semiconductor device substrate |
US7361990B2 (en) | 2005-03-17 | 2008-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads |
US20080093749A1 (en) | 2006-10-20 | 2008-04-24 | Texas Instruments Incorporated | Partial Solder Mask Defined Pad Design |
US7405484B2 (en) | 2003-09-30 | 2008-07-29 | Sanyo Electric Co., Ltd. | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof |
US20080179740A1 (en) | 2007-01-25 | 2008-07-31 | Advanced Semiconductor Engineering, Inc. | Package substrate, method of fabricating the same and chip package |
US7436063B2 (en) | 2004-10-04 | 2008-10-14 | Rohm Co., Ltd. | Packaging substrate and semiconductor device |
US20080277802A1 (en) | 2007-05-10 | 2008-11-13 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package and package substrate applicable thereto |
US7488896B2 (en) | 2004-11-04 | 2009-02-10 | Ngk Spark Plug Co., Ltd. | Wiring board with semiconductor component |
US7521284B2 (en) | 2007-03-05 | 2009-04-21 | Texas Instruments Incorporated | System and method for increased stand-off height in stud bumping process |
US20090108445A1 (en) | 2007-10-31 | 2009-04-30 | Advanced Semiconductor Engineering, Inc. | Substrate structure and semiconductor package using the same |
US20090114436A1 (en) | 2007-11-07 | 2009-05-07 | Advanced Semiconductor Engineering, Inc. | Substrate structure |
US20090152716A1 (en) | 2007-12-12 | 2009-06-18 | Shinko Electric Industries Co., Ltd. | Wiring substrate and electronic component mounting structure |
US20090191329A1 (en) | 2008-01-30 | 2009-07-30 | Advanced Semiconductor Engineering, Inc. | Surface treatment process for circuit board |
US20090288866A1 (en) | 2006-01-16 | 2009-11-26 | Siliconware Precision Industries Co., Ltd. | Electronic carrier board |
US20090308647A1 (en) | 2008-06-11 | 2009-12-17 | Advanced Semiconductor Engineering, Inc. | Circuit board with buried conductive trace formed thereon and method for manufacturing the same |
US7642660B2 (en) | 2002-12-17 | 2010-01-05 | Cheng Siew Tay | Method and apparatus for reducing electrical interconnection fatigue |
US7670939B2 (en) | 2008-05-12 | 2010-03-02 | Ati Technologies Ulc | Semiconductor chip bump connection apparatus and method |
US7671454B2 (en) | 2006-05-12 | 2010-03-02 | Sharp Kabushiki Kaisha | Tape carrier, semiconductor apparatus, and semiconductor module apparatus |
US7700407B2 (en) | 2003-11-10 | 2010-04-20 | Stats Chippac, Ltd. | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density |
US7732913B2 (en) | 2006-02-03 | 2010-06-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package substrate |
US20100139965A1 (en) | 2008-12-09 | 2010-06-10 | Advanced Semiconductor Engineering, Inc. | Embedded circuit substrate and manufacturing method thereof |
US7750457B2 (en) | 2004-03-30 | 2010-07-06 | Sharp Kabushiki Kaisha | Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus |
US7790509B2 (en) | 2008-06-27 | 2010-09-07 | Texas Instruments Incorporated | Method for fine-pitch, low stress flip-chip interconnect |
US7791211B2 (en) | 2007-10-19 | 2010-09-07 | Advanced Semiconductor Engineering, Inc. | Flip chip package structure and carrier thereof |
US7847417B2 (en) | 2005-12-22 | 2010-12-07 | Shinko Electric Industries Co., Ltd. | Flip-chip mounting substrate and flip-chip mounting method |
US7847399B2 (en) | 2007-12-07 | 2010-12-07 | Texas Instruments Incorporated | Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles |
US7851928B2 (en) | 2008-06-10 | 2010-12-14 | Texas Instruments Incorporated | Semiconductor device having substrate with differentially plated copper and selective solder |
US7898083B2 (en) | 2008-12-17 | 2011-03-01 | Texas Instruments Incorporated | Method for low stress flip-chip assembly of fine-pitch semiconductor devices |
US20110049703A1 (en) | 2009-08-25 | 2011-03-03 | Jun-Chung Hsu | Flip-Chip Package Structure |
US7902678B2 (en) | 2004-03-29 | 2011-03-08 | Nec Corporation | Semiconductor device and manufacturing method thereof |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
US7932170B1 (en) | 2008-06-23 | 2011-04-26 | Amkor Technology, Inc. | Flip chip bump structure and fabrication method |
US7947602B2 (en) | 2007-02-21 | 2011-05-24 | Texas Instruments Incorporated | Conductive pattern formation method |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
-
2006
- 2006-12-14 US US11/640,468 patent/US20070105277A1/en not_active Abandoned
-
2013
- 2013-02-01 US US13/756,905 patent/USRE44608E1/en active Active
Patent Citations (148)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04355933A (en) | 1991-02-07 | 1992-12-09 | Nitto Denko Corp | Packaging structure of flip chip |
US5186383A (en) | 1991-10-02 | 1993-02-16 | Motorola, Inc. | Method for forming solder bump interconnections to a solder-plated circuit trace |
WO1993006964A1 (en) | 1991-10-02 | 1993-04-15 | Motorola, Inc. | Method for forming solder bump interconnections to a solder-plated circuit trace |
US5378859A (en) | 1992-03-02 | 1995-01-03 | Casio Computer Co., Ltd. | Film wiring board |
US5434410A (en) | 1992-05-29 | 1995-07-18 | Texas Instruments Incorporated | Fine-grain pyroelectric detector material and method |
US5386624A (en) | 1993-07-06 | 1995-02-07 | Motorola, Inc. | Method for underencapsulating components on circuit supporting substrates |
US5508561A (en) | 1993-11-15 | 1996-04-16 | Nec Corporation | Apparatus for forming a double-bump structure used for flip-chip mounting |
US5519580A (en) | 1994-09-09 | 1996-05-21 | Intel Corporation | Method of controlling solder ball size of BGA IC components |
US5844782A (en) | 1994-12-20 | 1998-12-01 | Sony Corporation | Printed wiring board and electronic device using same |
US6229209B1 (en) | 1995-02-23 | 2001-05-08 | Matsushita Electric Industrial Co., Ltd. | Chip carrier |
US5650595A (en) | 1995-05-25 | 1997-07-22 | International Business Machines Corporation | Electronic module with multiple solder dams in soldermask window |
US6229220B1 (en) | 1995-06-27 | 2001-05-08 | International Business Machines Corporation | Bump structure, bump forming method and package connecting body |
JPH0997791A (en) | 1995-09-27 | 1997-04-08 | Internatl Business Mach Corp <Ibm> | Bump structure, formation of bump and installation connection body |
US5710071A (en) | 1995-12-04 | 1998-01-20 | Motorola, Inc. | Process for underfilling a flip-chip semiconductor device |
US5915169A (en) | 1995-12-22 | 1999-06-22 | Anam Industrial Co., Ltd. | Semiconductor chip scale package and method of producing such |
US5889326A (en) | 1996-02-27 | 1999-03-30 | Nec Corporation | Structure for bonding semiconductor device to substrate |
US5869886A (en) | 1996-03-22 | 1999-02-09 | Nec Corporation | Flip chip semiconductor mounting structure with electrically conductive resin |
US5872399A (en) | 1996-04-01 | 1999-02-16 | Anam Semiconductor, Inc. | Solder ball land metal structure of ball grid semiconductor package |
US5854514A (en) | 1996-08-05 | 1998-12-29 | International Buisness Machines Corporation | Lead-free interconnection for electronic devices |
US6297560B1 (en) | 1996-10-31 | 2001-10-02 | Miguel Albert Capote | Semiconductor flip-chip assembly with pre-applied encapsulating layers |
US20010013423A1 (en) | 1996-10-31 | 2001-08-16 | Hormazdyar M. Dalal | Flip chip attach on flexible circuit carrier using chip with metallic cap on solder |
US5795818A (en) | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
US6333206B1 (en) | 1996-12-24 | 2001-12-25 | Nitto Denko Corporation | Process for the production of semiconductor device |
US6002172A (en) | 1997-03-12 | 1999-12-14 | International Business Machines Corporation | Substrate structure and method for improving attachment reliability of semiconductor chips and modules |
US6281581B1 (en) | 1997-03-12 | 2001-08-28 | International Business Machines Corporation | Substrate structure for improving attachment reliability of semiconductor chips and modules |
JPH10256307A (en) | 1997-03-13 | 1998-09-25 | Ngk Spark Plug Co Ltd | Wiring board with semiconductor device, wiring board and manufacture thereof |
US20020192865A1 (en) | 1997-03-27 | 2002-12-19 | Hitachi, Ltd. And Hitachi Hokkai Semiconductor, Ltd. | Process for mounting electronic device and semiconductor device |
US6228466B1 (en) | 1997-04-11 | 2001-05-08 | Ibiden Co. Ltd. | Printed wiring board and method for manufacturing the same |
US6281450B1 (en) | 1997-06-26 | 2001-08-28 | Hitachi Chemical Company, Ltd. | Substrate for mounting semiconductor chips |
US6218630B1 (en) | 1997-06-30 | 2001-04-17 | Fuji Photo Film Co., Ltd. | Printed circuit board having arrays of lands arranged inside and outside of each other having a reduced terminal-pitch |
US6335571B1 (en) | 1997-07-21 | 2002-01-01 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
US5985456A (en) | 1997-07-21 | 1999-11-16 | Miguel Albert Capote | Carboxyl-containing polyunsaturated fluxing adhesive for attaching integrated circuits |
US6448665B1 (en) | 1997-10-15 | 2002-09-10 | Kabushiki Kaisha Toshiba | Semiconductor package and manufacturing method thereof |
JPH11145176A (en) | 1997-11-11 | 1999-05-28 | Fujitsu Ltd | Method for forming solder bump and method for forming preliminary solder |
US6109507A (en) | 1997-11-11 | 2000-08-29 | Fujitsu Limited | Method of forming solder bumps and method of forming preformed solder bumps |
US6259163B1 (en) | 1997-12-25 | 2001-07-10 | Oki Electric Industry Co., Ltd. | Bond pad for stress releif between a substrate and an external substrate |
US20020041036A1 (en) | 1998-02-03 | 2002-04-11 | Smith John W. | Microelectronic assemblies with composite conductive elements |
JPH11233571A (en) | 1998-02-12 | 1999-08-27 | Hitachi Ltd | Semiconductor device, underfill material, and thermosetting film material |
US6324754B1 (en) | 1998-03-25 | 2001-12-04 | Tessera, Inc. | Method for fabricating microelectronic assemblies |
US6329605B1 (en) | 1998-03-26 | 2001-12-11 | Tessera, Inc. | Components with conductive solder mask layers |
JP2000031204A (en) | 1998-07-07 | 2000-01-28 | Ricoh Co Ltd | Manufacture of semiconductor package |
US6409073B1 (en) | 1998-07-15 | 2002-06-25 | Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. | Method for transfering solder to a device and/or testing the device |
US6678948B1 (en) | 1998-09-01 | 2004-01-20 | Robert Bosch Gmbh | Method for connecting electronic components to a substrate, and a method for checking such a connection |
US6335568B1 (en) | 1998-10-28 | 2002-01-01 | Seiko Epson Corporation | Semiconductor device and method of fabrication thereof, circuit board, and electronic equipment |
US6383916B1 (en) | 1998-12-21 | 2002-05-07 | M. S. Lin | Top layers of metal for high performance IC's |
US6600234B2 (en) | 1999-02-03 | 2003-07-29 | Casio Computer Co., Ltd. | Mounting structure having columnar electrodes and a sealing film |
US6462425B1 (en) | 1999-04-19 | 2002-10-08 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
JP2000349194A (en) | 1999-06-08 | 2000-12-15 | Matsushita Electric Ind Co Ltd | Semiconductor device and its manufacture |
US6458622B1 (en) | 1999-07-06 | 2002-10-01 | Motorola, Inc. | Stress compensation composition and semiconductor component formed using the stress compensation composition |
US6441316B1 (en) | 1999-08-27 | 2002-08-27 | Mitsubishi Denki Kabushiki Kaisha | Printed-circuit board and a semiconductor module, and a manufacturing process of the semiconductor module |
US6518674B2 (en) | 1999-09-23 | 2003-02-11 | International Business Machines Corporation | Temporary attach article and method for temporary attach of devices to a substrate |
US6396707B1 (en) | 1999-10-21 | 2002-05-28 | Siliconware Precision Industries Co., Ltd. | Ball grid array package |
US6913948B2 (en) | 1999-11-10 | 2005-07-05 | International Business Machines Corporation | Partially captured oriented interconnections for BGA packages and a method of forming the interconnections |
JP2001156203A (en) | 1999-11-24 | 2001-06-08 | Matsushita Electric Works Ltd | Printed wiring board for mounting semiconductor chip |
US6472608B2 (en) | 2000-02-18 | 2002-10-29 | Nec Corporation | Semiconductor device |
US7005743B2 (en) | 2000-04-28 | 2006-02-28 | Sony Corporation | Semiconductor device using bumps, method for fabricating same, and method for forming bumps |
US6787918B1 (en) | 2000-06-02 | 2004-09-07 | Siliconware Precision Industries Co., Ltd. | Substrate structure of flip chip package |
US6573610B1 (en) | 2000-06-02 | 2003-06-03 | Siliconware Precision Industries Co., Ltd. | Substrate of semiconductor package for flip chip package |
US6201305B1 (en) | 2000-06-09 | 2001-03-13 | Amkor Technology, Inc. | Making solder ball mounting pads on substrates |
US20030067084A1 (en) | 2000-06-28 | 2003-04-10 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method thereof |
US6710458B2 (en) | 2000-10-13 | 2004-03-23 | Sharp Kabushiki Kaisha | Tape for chip on film and semiconductor therewith |
US20020121706A1 (en) | 2000-12-28 | 2002-09-05 | Matsushita Electic Works, Ltd. | Semiconductor-chip mounting substrate and method of manufacturing the same |
US6780682B2 (en) | 2001-02-27 | 2004-08-24 | Chippac, Inc. | Process for precise encapsulation of flip chip interconnects |
US6818545B2 (en) | 2001-03-05 | 2004-11-16 | Megic Corporation | Low fabrication cost, fine pitch and high reliability solder bump |
US7242099B2 (en) | 2001-03-05 | 2007-07-10 | Megica Corporation | Chip package with multiple chips connected by bumps |
US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
JP2002270732A (en) | 2001-03-13 | 2002-09-20 | Sharp Corp | Electronic component with underfill material |
US20040105223A1 (en) | 2001-03-19 | 2004-06-03 | Ryoichi Okada | Method of manufacturing electronic part and electronic part obtained by the method |
US20020155637A1 (en) | 2001-04-20 | 2002-10-24 | Shih-Chang Lee | Flip chip interconnected structure and a fabrication method thereof |
US6664483B2 (en) | 2001-05-15 | 2003-12-16 | Intel Corporation | Electronic package with high density interconnect and associated methods |
US6660560B2 (en) | 2001-09-10 | 2003-12-09 | Delphi Technologies, Inc. | No-flow underfill material and underfill method for flip chip devices |
US20030049411A1 (en) | 2001-09-10 | 2003-03-13 | Delphi Technologies,Inc | No-flow underfill material and underfill method for flip chip devices |
US6608388B2 (en) | 2001-11-01 | 2003-08-19 | Siliconware Precision Industries Co., Ltd. | Delamination-preventing substrate and semiconductor package with the same |
US6870276B1 (en) | 2001-12-26 | 2005-03-22 | Micron Technology, Inc. | Apparatus for supporting microelectronic substrates |
WO2003071842A1 (en) | 2001-12-26 | 2003-08-28 | Motorola, Inc. | Method of mounting a semiconductor die on a substrate without using a solder mask |
US20030127734A1 (en) | 2002-01-07 | 2003-07-10 | Jin-Yuan Lee | Cylindrical bonding structure and method of manufacture |
US6768190B2 (en) | 2002-01-25 | 2004-07-27 | Advanced Semiconductor Engineering, Inc. | Stack type flip-chip package |
US20030168748A1 (en) | 2002-03-08 | 2003-09-11 | Mitsuaki Katagiri | Semiconductor device |
US6734557B2 (en) | 2002-03-12 | 2004-05-11 | Sharp Kabushiki Kaisha | Semiconductor device |
US6780673B2 (en) | 2002-06-12 | 2004-08-24 | Texas Instruments Incorporated | Method of forming a semiconductor device package using a plate layer surrounding contact pads |
US20040035909A1 (en) | 2002-08-22 | 2004-02-26 | Shing Yeh | Lead-based solder alloys containing copper |
US7005585B2 (en) | 2002-09-02 | 2006-02-28 | Murata Manufacturing Co., Ltd. | Mounting board and electronic device using same |
US20040056341A1 (en) | 2002-09-19 | 2004-03-25 | Kabushiki Kaisha Toshiba | Semiconductor device, semiconductor package member, and semiconductor device manufacturing method |
US20040108135A1 (en) | 2002-10-11 | 2004-06-10 | Takeshi Ashida | Circuit board, mounting structure of ball grid array, electro-optic device and electronic device |
JP2004165283A (en) | 2002-11-11 | 2004-06-10 | Fujitsu Ltd | Semiconductor device |
US7642660B2 (en) | 2002-12-17 | 2010-01-05 | Cheng Siew Tay | Method and apparatus for reducing electrical interconnection fatigue |
JP2004221205A (en) | 2003-01-10 | 2004-08-05 | Seiko Epson Corp | Method for mounting semiconductor chip, semiconductor mounting substrate, electronic device and electronic equipment |
US6821878B2 (en) | 2003-02-27 | 2004-11-23 | Freescale Semiconductor, Inc. | Area-array device assembly with pre-applied underfill layers on printed wiring board |
US6774497B1 (en) | 2003-03-28 | 2004-08-10 | Freescale Semiconductor, Inc. | Flip-chip assembly with thin underfill and thick solder mask |
US20040232562A1 (en) | 2003-05-23 | 2004-11-25 | Texas Instruments Incorporated | System and method for increasing bump pad height |
US6888255B2 (en) | 2003-05-30 | 2005-05-03 | Texas Instruments Incorporated | Built-up bump pad structure and method for same |
US6849944B2 (en) | 2003-05-30 | 2005-02-01 | Texas Instruments Incorporated | Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad |
US6809262B1 (en) | 2003-06-03 | 2004-10-26 | Via Technologies, Inc. | Flip chip package carrier |
JP2005028037A (en) | 2003-07-11 | 2005-02-03 | Fuji Photo Film Co Ltd | Medical image processing device and medical image processing method |
US7049705B2 (en) | 2003-07-15 | 2006-05-23 | Advanced Semiconductor Engineering, Inc. | Chip structure |
US7173828B2 (en) | 2003-07-28 | 2007-02-06 | Siliconware Precision Industries Co., Ltd. | Ground pad structure for preventing solder extrusion and semiconductor package having the ground pad structure |
US7064435B2 (en) | 2003-07-29 | 2006-06-20 | Samsung Electronics Co., Ltd. | Semiconductor package with improved ball land structure |
US7005750B2 (en) | 2003-08-01 | 2006-02-28 | Advanced Semiconductor Engineering, Inc. | Substrate with reinforced contact pad structure |
US7102239B2 (en) | 2003-08-18 | 2006-09-05 | Siliconware Precision Industries Co., Ltd. | Chip carrier for semiconductor chip |
US7098407B2 (en) | 2003-08-23 | 2006-08-29 | Samsung Electronics Co., Ltd. | Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate |
US20050046041A1 (en) | 2003-08-29 | 2005-03-03 | Advanced Semiconductor Engineering, Inc. | Integrated circuit device with embedded passive component by flip-chip connection and method for manufacturing the same |
US7271484B2 (en) | 2003-09-25 | 2007-09-18 | Infineon Technologies Ag | Substrate for producing a soldering connection |
US7112524B2 (en) | 2003-09-29 | 2006-09-26 | Phoenix Precision Technology Corporation | Substrate for pre-soldering material and fabrication method thereof |
US7405484B2 (en) | 2003-09-30 | 2008-07-29 | Sanyo Electric Co., Ltd. | Semiconductor device containing stacked semiconductor chips and manufacturing method thereof |
US20050103516A1 (en) | 2003-09-30 | 2005-05-19 | Tdk Corporation | Flip-chip mounting circuit board, manufacturing method thereof and integrated circuit device |
JP2005109187A (en) | 2003-09-30 | 2005-04-21 | Tdk Corp | Flip chip packaging circuit board and its manufacturing method, and integrated circuit device |
US7102222B2 (en) | 2003-10-02 | 2006-09-05 | Siliconware Precision Industries Co., Ltd. | Conductive trace structure and semiconductor package having the conductive trace structure |
US7973406B2 (en) | 2003-11-10 | 2011-07-05 | Stats Chippac, Ltd. | Bump-on-lead flip chip interconnection |
US7700407B2 (en) | 2003-11-10 | 2010-04-20 | Stats Chippac, Ltd. | Method of forming a bump-on-lead flip chip interconnection having higher escape routing density |
US7294929B2 (en) | 2003-12-30 | 2007-11-13 | Texas Instruments Incorporated | Solder ball pad structure |
US7902678B2 (en) | 2004-03-29 | 2011-03-08 | Nec Corporation | Semiconductor device and manufacturing method thereof |
US7750457B2 (en) | 2004-03-30 | 2010-07-06 | Sharp Kabushiki Kaisha | Semiconductor apparatus, manufacturing method thereof, semiconductor module apparatus using semiconductor apparatus, and wire substrate for semiconductor apparatus |
US20050248037A1 (en) | 2004-05-06 | 2005-11-10 | Advanced Semiconductor Engineering, Inc. | Flip-chip package substrate with a high-density layout |
US7224073B2 (en) | 2004-05-18 | 2007-05-29 | Ultratera Corporation | Substrate for solder joint |
US7057284B2 (en) | 2004-08-12 | 2006-06-06 | Texas Instruments Incorporated | Fine pitch low-cost flip chip substrate |
US7436063B2 (en) | 2004-10-04 | 2008-10-14 | Rohm Co., Ltd. | Packaging substrate and semiconductor device |
US7488896B2 (en) | 2004-11-04 | 2009-02-10 | Ngk Spark Plug Co., Ltd. | Wiring board with semiconductor component |
US20060192294A1 (en) | 2004-11-15 | 2006-08-31 | Chippac, Inc | Chip scale package having flip chip interconnect on die paddle |
US20060131758A1 (en) | 2004-12-22 | 2006-06-22 | Stmicroelectronics, Inc. | Anchored non-solder mask defined ball pad |
US20060202331A1 (en) | 2005-03-09 | 2006-09-14 | Wen-Hung Hu | Conductive bump structure of circuit board and method for fabricating the same |
US7361990B2 (en) | 2005-03-17 | 2008-04-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads |
US7847417B2 (en) | 2005-12-22 | 2010-12-07 | Shinko Electric Industries Co., Ltd. | Flip-chip mounting substrate and flip-chip mounting method |
US20090288866A1 (en) | 2006-01-16 | 2009-11-26 | Siliconware Precision Industries Co., Ltd. | Electronic carrier board |
US7732913B2 (en) | 2006-02-03 | 2010-06-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package substrate |
US20070200234A1 (en) | 2006-02-28 | 2007-08-30 | Texas Instruments Incorporated | Flip-Chip Device Having Underfill in Controlled Gap |
US7317245B1 (en) | 2006-04-07 | 2008-01-08 | Amkor Technology, Inc. | Method for manufacturing a semiconductor device substrate |
US7671454B2 (en) | 2006-05-12 | 2010-03-02 | Sharp Kabushiki Kaisha | Tape carrier, semiconductor apparatus, and semiconductor module apparatus |
US7902660B1 (en) | 2006-05-24 | 2011-03-08 | Amkor Technology, Inc. | Substrate for semiconductor device and manufacturing method thereof |
US20080093749A1 (en) | 2006-10-20 | 2008-04-24 | Texas Instruments Incorporated | Partial Solder Mask Defined Pad Design |
US8129841B2 (en) | 2006-12-14 | 2012-03-06 | Stats Chippac, Ltd. | Solder joint flip chip interconnection |
US20080179740A1 (en) | 2007-01-25 | 2008-07-31 | Advanced Semiconductor Engineering, Inc. | Package substrate, method of fabricating the same and chip package |
US7947602B2 (en) | 2007-02-21 | 2011-05-24 | Texas Instruments Incorporated | Conductive pattern formation method |
US7521284B2 (en) | 2007-03-05 | 2009-04-21 | Texas Instruments Incorporated | System and method for increased stand-off height in stud bumping process |
US20080277802A1 (en) | 2007-05-10 | 2008-11-13 | Siliconware Precision Industries Co., Ltd. | Flip-chip semiconductor package and package substrate applicable thereto |
US7791211B2 (en) | 2007-10-19 | 2010-09-07 | Advanced Semiconductor Engineering, Inc. | Flip chip package structure and carrier thereof |
US20090108445A1 (en) | 2007-10-31 | 2009-04-30 | Advanced Semiconductor Engineering, Inc. | Substrate structure and semiconductor package using the same |
US20090114436A1 (en) | 2007-11-07 | 2009-05-07 | Advanced Semiconductor Engineering, Inc. | Substrate structure |
US7847399B2 (en) | 2007-12-07 | 2010-12-07 | Texas Instruments Incorporated | Semiconductor device having solder-free gold bump contacts for stability in repeated temperature cycles |
US20090152716A1 (en) | 2007-12-12 | 2009-06-18 | Shinko Electric Industries Co., Ltd. | Wiring substrate and electronic component mounting structure |
US20090191329A1 (en) | 2008-01-30 | 2009-07-30 | Advanced Semiconductor Engineering, Inc. | Surface treatment process for circuit board |
US7670939B2 (en) | 2008-05-12 | 2010-03-02 | Ati Technologies Ulc | Semiconductor chip bump connection apparatus and method |
US7851928B2 (en) | 2008-06-10 | 2010-12-14 | Texas Instruments Incorporated | Semiconductor device having substrate with differentially plated copper and selective solder |
US20090308647A1 (en) | 2008-06-11 | 2009-12-17 | Advanced Semiconductor Engineering, Inc. | Circuit board with buried conductive trace formed thereon and method for manufacturing the same |
US7932170B1 (en) | 2008-06-23 | 2011-04-26 | Amkor Technology, Inc. | Flip chip bump structure and fabrication method |
US7790509B2 (en) | 2008-06-27 | 2010-09-07 | Texas Instruments Incorporated | Method for fine-pitch, low stress flip-chip interconnect |
US20100139965A1 (en) | 2008-12-09 | 2010-06-10 | Advanced Semiconductor Engineering, Inc. | Embedded circuit substrate and manufacturing method thereof |
US7898083B2 (en) | 2008-12-17 | 2011-03-01 | Texas Instruments Incorporated | Method for low stress flip-chip assembly of fine-pitch semiconductor devices |
US20110049703A1 (en) | 2009-08-25 | 2011-03-03 | Jun-Chung Hsu | Flip-Chip Package Structure |
Non-Patent Citations (5)
Title |
---|
Kawahara, Toshimi, "SuperCSP", IEEE Transactions on Advanced Packaging, May 2000, pp. 215-219, vol. 23, No. 2. |
Lu, H. et al., "Predicting Optimal Process Conditions for Flip-Chip Assembly Using Copper Column Bumped Dies", Electronics Packaging Technology Conference, 2002, pp. 338-343. |
Son, Ho-Young, "Studies on the Thermal Cycling Reliability of Fine Pitch Cu/SnAg Double-Bump Flip Chip Assemblies on Organic Substrates: Experimental Results and Numerical Analysis", IEEE Electronic Components and Technology Conference, 2008, pp. 2035-2043. |
Yamada, Hiroshi et al., "A fine pitch and high aspect ratio bump array for flip-chip interconnection", Int'l Electronics Manufacturing Technology Symposium, 1992, pp. 288-292, IEEE/CHMT. |
Yamada, Hiroshi et al., "Advanced copper column based solder bump for flip-chip interconnection", International Symposium on Microelectronics, 1997, pp. 417-422, The British Library-"The world's knowledge". |
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