USRE40137E1 - Methods for forming integrated circuits within substrates - Google Patents
Methods for forming integrated circuits within substrates Download PDFInfo
- Publication number
- USRE40137E1 USRE40137E1 US10/734,072 US73407203A USRE40137E US RE40137 E1 USRE40137 E1 US RE40137E1 US 73407203 A US73407203 A US 73407203A US RE40137 E USRE40137 E US RE40137E
- Authority
- US
- United States
- Prior art keywords
- recess
- antenna
- method
- substrate
- providing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06K—RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
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- G—PHYSICS
- G06—COMPUTING; CALCULATING; COUNTING
- G06K—RECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
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- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—BASIC ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
Abstract
Description
More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,329,213 B1. The reissue applications are application Ser. Nos. 10/734,072 (the present application), 11/302,543, and 11/496,088, all of which are continuation reissues of U.S. Pat. No. 6,329,213 B1.
The invention pertains to methods of forming integrated circuits within substrates, and to embedded circuits. The invention is thought to have particular application towards methods of forming integrated circuits within personal cards, such as personal identification cards and credit cards.
Smart cards typically include an integrated circuit providing both memory and processing functions, have words or pictures printed on them, and control who uses information stored in the integrated circuit and how the information is used.
Some smart cards have length and width dimensions corresponding to those of credit cards. The size of such smart cards is determined by an international standard (ISO 7816). ISO 7816 also defines the physical characteristics of the plastic, including temperature tolerance and flexibility. ISO 7816 also defines the position of electrical contacts and their functions, and the protocol for communications between the integrated circuit and readers (vending machines, pay phones, etc.) The term “smart card”, as used herein, is meant to include cards that include microprocessors. Such cards might not conform to ISO 7816.
Several types of plastic are used for the casings or housings of smart cards. PVC and ABS are typical. PVC can be embossed, but is not recyclable. ABS is not readily embossed, but is recyclable.
Smart cards have many different applications. For example, smart cards can be pre-paid cards used instead of money for making purchases from vending machines, gaming machines, gas stations, car washes, photocopiers, laundry machines, cinemas, fast-food restaurants, retail outlets, or anywhere where cash is used. For example, they are commonly used in Europe with public telephones. A timer is used to detect a balance from the card automatically while a conversation continues. Smart cards can be used as food stamps, or for redeeming other government-provided benefits. Because the transaction is electronic, the telephone, vending machine, etc. does not need to store cash, so risk of loss due to theft can be reduced. Change does not need to be stored and disbursed, and received payment can be directly wired to a bank. Pre-paid cards can be a form of advertising, because they can have logos or other information printed on them. The user would typically carry the card for weeks before using up the value on the card.
To authenticate a conventional credit card, a telephone call must be made to verify that sufficient funds are available. Smart cards permit such verification to be performed off-line, thus saving telecommunication charges. Smart cards thus provide an advantage over conventional credit cards. Smart cards can also be used as keys to gain access to restricted areas, such as secure areas of buildings, or to access parking lots.
Radio frequency identification devices (RFIDs) can also be considered smart cards if they include an integrated circuit. RFIDs are described in detail in U.S. patent application Ser. No. 08/705,043, filed Aug. 29, 1996, and incorporated herein by reference. RFIDs comprising integrated circuits may be referred to as intelligent RFIDs or as remote intelligent communication (RIC) devices.
Smart cards will typically contain an integrated circuit, typically provided as a packaged integrated circuit chip (IC chip). The smart card may also comprise electrical interconnects for connecting the IC chip to terminals. In other instances, the electronic interconnects will comprise an antenna, such as, for example, when the integrated circuit comprises radio frequency identification device circuitry. In other instances, an antenna, battery and IC may be inserted into smart cards. As smart cards are intended to be conveniently carried by persons, it is desirable to produce smart cards which are relatively thin, preferably having a size and shape similar to credit cards. This enables the cards to be carried on a person, such as, for example, in a persons's wallet.
The invention encompasses methods for forming integrated circuits within substrates, and embedded circuits.
In one aspect, the invention encompasses a method of forming an integrated circuit within a substrate. A recess is formed in the substrate, and an antenna is printed within the recess. An integrated circuit chip and a battery are provided in operative electrical connection with the antenna.
In another aspect, the invention encompasses a method of forming a plurality of cards. A substrate sheet is provided and a plurality of recesses are formed within the substrate sheet. The individual recesses have bottom surfaces and sidewall surfaces joined to the bottom surfaces. A conductive film is printed within the recesses to form electrical interconnects within the recesses. The electrical interconnects extend along the bottom surfaces and the sidewall surfaces of the recesses, and also on top surfaces of the substrate sheet. Integrated circuit chips are placed within the recesses and in electrical connection with the electrical interconnects. The integrated circuit chips and the conductive film within the recesses are covered with a protective cover. The substrate sheet is divided into a plurality of cards.
In another aspect, the invention encompasses an embedded circuit. The embedded circuit includes a substrate having a recess therein; a conductive circuit printed within the recess and an integrated circuit chip bonded to the conductive circuit.
In another aspect, the invention encompasses an embedded circuit. The embedded circuit includes a substrate having a recess therein; a conductive circuit provided within the recess; an integrated circuit chip bonded to the conductive circuit; and a battery in electrical connection with the integrated circuit chip.
In accordance with another embodiment, a recess is provided in a plastic substrate containing an integrated circuit comprising RFID circuitry. A conductive material extends over a sidewall of the recess and is coupled to the integrated circuit in a first region and to an antenna in a second region. A flexible film may be disposed over the recess, the integrated circuit, and the conductive material.
Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
A first embodiment method of the present invention is described with reference to
Substrate 10 comprises a substrate body 13, a front surface 12, and an opposing back surface 11 (shown in FIG. 5). A recess 14 is provided through front surface 12 and into substrate 10. Recess 14 can be formed by conventional methods. Examples include cutting with a blade, grinding wheel or laser. Another example method for forming recess 14 is to form the recess in situ at a time of card creation by injection molding the card in a shape comprising recess 14. Recess 14 has a bottom surface 16 and sidewall surfaces 18 joined to bottom surface 16. As most clearly shown in
Still referring to
Referring to
After curing, circuit 22 will have a thickness and associated degree of conductivity. If the conductive is lower than desired as may occur if, for example, conductive material of circuit 22 is too thin, or not adequately a low resistance material, the conductivity can be enhanced by providing an electroless plated metal, such as copper or nickel, against substrate 10 and circuit 22. The electroless plated metal selectively plates conductive circuit 22, while not plating non-conductive surfaces of substrate 10. The electroless plating of metal can be accomplished by conventional methods.
Referring to
In the preferred embodiment, antenna 26 constitutes a part of, and is formed at the same time as, the other integrated circuitry. It is noted that antenna 26 could be formed in two steps, with a portion of antenna 26 being formed before or after pad printing of circuit 22. For instance, the portion of antenna 26 extending along upper surface 12 could be formed prior to printing circuit 22. Then, a portion of antenna 26 could be printed as part of circuit 22 to create nodes 32 and 33, and to connect the previously formed portion of antenna 26 with nodes 32 and 33. In such circumstances, the portion of antenna 26 which is not formed as part of circuit 22 could be formed by methods other than those utilized to form circuit 22. For instance, if circuit 22 is pad printed, the portion of antenna 26 not formed as part of circuit 22 could be formed by a method other than pad printing. Such other methods will be recognized by persons of ordinary skill in the art.
Referring to
In the illustrated embodiment, interconnects 23 and 24 connect battery 36 to integrated circuit 38, and antenna 26 connects with integrated circuit 38. Battery 36, interconnects 23 and 24, integrated circuit 38 and antenna 26 together form a radio frequency identification device (RFID).
After provision of circuit 22 and one or both of components 36 and 38 within recess 14, a protective cover is ideally formed over circuit 22 and recess 14.
Referring to
It is noted that the methods of
After provision of a protective cover over recess 14, the construction of a card is substantially finished. The card may then be covered with a laminating film for cosmetic, printability, or logo reasons. An example laminating film would be a thin (less than about one mil) PVC sheet bonded to substrate 10 with an adhesive.
A second embodiment method of the present invention is described with reference to
Referring to
In the illustrated embodiment, components 36a and 38a are each within a recess, with component 36a being within first recess 52 and component 38a being within second recess 54. First recess 52 comprises a bottom surface 56 and sidewall surfaces 58. Second recess 54 comprises a bottom surface 60 and sidewall surfaces 62. Sidewall surfaces 58 and 62 can extend non-perpendicularly form bottom surfaces 56 and 60, respectively, to simply printing of circuit 22a over such sidewall surfaces. First recess 52 is separated from second recess 54 by one of the sidewall surfaces 62. The separating sidewall 62 extends non-perpendicularly from both of bottom surface 56 and bottom surface 60. Interconnects 23a and 24a extend over the separating sidewall surface 62 and along bottom surfaces 60 and 56. Interconnects 23a and 24a thus extend continuously from electrical component 36a to electrical component 38a.
Substrate 10a comprises a front surface 12a and an opposing back surface 11a. Preferably, first recess 52 and second recess 54 both extend through the same of either front surface 12a or back surface 11a. In
Subsequent processing of substrate 10a can be performed in accordance with the processing of either
A third embodiment method of the present invention is described with reference to
A substrate 10b comprises a substrate body 13b, a front surface 12b, and an opposing back surface 11b. A recess 14b is provided through front surface 12b and into substrate 10b. Electrical components 36b and 38b are within recess 14b and connected by interconnects 23b and 24b. A loop antenna 26b is electrically connected with component 38b. Loop antenna 26b extends from component 38b, out of recess 14b, and along surface 12b of substrate 10b. Antenna 26b crosses over itself at a bypass 70. Antenna 26b comprises a first portion 66 and a second portion 68 at bypass 70, with second portion 68 crossing over first portion 66. Bypass 70 comprises an insulative material 72 separating first portion 66 from second portion 68. Insulative material 72 can comprise, for example, silicon dioxide.
Methods for forming antenna 26b will be recognized by persons of ordinary skill in the art. Such methods could include, for example, printing methods similar to those discussed above in discussing
Although the embodiment of
It is noted that although antenna second portion 68 is illustrated as being substantially perpendicular to antenna first portion 66 at bypass 70, the invention encompasses other embodiments (not shown) in which an antenna second portion is non-perpendicular to an antenna first portion at a bypass of the antenna portions.
The processing described above with reference to
Although
The formation of a number of individual cards from a single sheet substrate is illustrated in
In compliance with the statue, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims (58)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US08/847,123 US6329213B1 (en) | 1997-05-01 | 1997-05-01 | Methods for forming integrated circuits within substrates |
US10/734,072 USRE40137E1 (en) | 1997-05-01 | 2003-12-10 | Methods for forming integrated circuits within substrates |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/734,072 USRE40137E1 (en) | 1997-05-01 | 2003-12-10 | Methods for forming integrated circuits within substrates |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date | |
---|---|---|---|---|
US08/847,123 Reissue US6329213B1 (en) | 1997-05-01 | 1997-05-01 | Methods for forming integrated circuits within substrates |
Publications (1)
Publication Number | Publication Date |
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USRE40137E1 true USRE40137E1 (en) | 2008-03-04 |
Family
ID=25299818
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/847,123 Expired - Lifetime US6329213B1 (en) | 1997-05-01 | 1997-05-01 | Methods for forming integrated circuits within substrates |
US09/305,107 Expired - Lifetime US6271801B2 (en) | 1997-05-01 | 1999-05-04 | Embedded circuits |
US10/734,072 Expired - Lifetime USRE40137E1 (en) | 1997-05-01 | 2003-12-10 | Methods for forming integrated circuits within substrates |
Family Applications Before (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/847,123 Expired - Lifetime US6329213B1 (en) | 1997-05-01 | 1997-05-01 | Methods for forming integrated circuits within substrates |
US09/305,107 Expired - Lifetime US6271801B2 (en) | 1997-05-01 | 1999-05-04 | Embedded circuits |
Country Status (6)
Country | Link |
---|---|
US (3) | US6329213B1 (en) |
JP (2) | JP3705444B2 (en) |
AU (1) | AU7470898A (en) |
DE (1) | DE19882361T1 (en) |
GB (1) | GB2339407B (en) |
WO (1) | WO1998049653A1 (en) |
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US20110057628A1 (en) * | 2006-07-28 | 2011-03-10 | Semiconductor Energy Laboratory Co., Ltd. | Power storage device |
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US7993773B2 (en) | 2002-08-09 | 2011-08-09 | Infinite Power Solutions, Inc. | Electrochemical apparatus with barrier layer protected substrate |
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Also Published As
Publication number | Publication date |
---|---|
WO1998049653A1 (en) | 1998-11-05 |
AU7470898A (en) | 1998-11-24 |
JP3996155B2 (en) | 2007-10-24 |
GB9925874D0 (en) | 1999-12-29 |
US6329213B1 (en) | 2001-12-11 |
DE19882361T1 (en) | 2000-05-11 |
GB2339407B (en) | 2001-12-19 |
JP3705444B2 (en) | 2005-10-12 |
JP2001523364A (en) | 2001-11-20 |
JP2005115959A (en) | 2005-04-28 |
DE19882361T0 (en) | |
GB2339407A (en) | 2000-01-26 |
US6271801B2 (en) | 2001-08-07 |
US20010002826A1 (en) | 2001-06-07 |
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