EP1097479A1 - Integrated electronic micromodule and method for making same - Google Patents

Integrated electronic micromodule and method for making same

Info

Publication number
EP1097479A1
EP1097479A1 EP99925077A EP99925077A EP1097479A1 EP 1097479 A1 EP1097479 A1 EP 1097479A1 EP 99925077 A EP99925077 A EP 99925077A EP 99925077 A EP99925077 A EP 99925077A EP 1097479 A1 EP1097479 A1 EP 1097479A1
Authority
EP
European Patent Office
Prior art keywords
support plate
coil
chip
micromodule
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99925077A
Other languages
German (de)
French (fr)
Inventor
Jacek Kowalski
Didier Serra
Frédéric BERTHOLIO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wisekey Semiconductors SAS
Original Assignee
Inside Technologies SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inside Technologies SA filed Critical Inside Technologies SA
Publication of EP1097479A1 publication Critical patent/EP1097479A1/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745—Mounting details of integrated circuit chips
    • G06K19/07747—Mounting details of integrated circuit chips at least one of the integrated circuit chips being mounted as a module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G—PHYSICS
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    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
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Definitions

  • the present invention relates to an electronic micromodule comprising a support plate, an integrated circuit chip, and at least one flat winding forming an antenna coil.
  • an antenna coil comprising means for receiving or transmitting data by inductive coupling in the presence of a magnetic field emitted by a radio station. transmission and / or reception of data.
  • Such integrated circuits, or passive transponders make it possible to produce various portable electronic objects operating without contact, such as smart cards, electronic labels, electronic tokens, etc.
  • the present invention relates to the manufacture of such portable objects, and more particularly to the manufacture of the electronic part of these portable objects.
  • the most generally used method for producing the electronic part of a portable object operating without contact consists in providing a support plate on which a coil and a silicon chip are deposited. The coil is then connected to the chip and the assembly is covered with a protective resin.
  • the support board is a printed circuit board.
  • the coil is a copper wire bonded or an engraved copper strip. The coil / chip connection is ensured by metallic wires welded uitrasonically.
  • the assembly forms an electronic micromodule intended to be introduced into the body of a portable object (plastic card, token, sticker, key, etc.) or fixed to its surface.
  • This method has the disadvantage of requiring various stages of handling, of manipulation of the constituent elements ri ⁇ cromodules, assembly, wiring, control ... which add to the cost price of ir ⁇ cromodules and limit production rates.
  • the printed circuit board generally has a thickness of around 150 micrometers, the silicon chip a thickness of around 150 micrometers after chemical or mechanical abrasion of its rear face, and the height of the loops formed by the wiring wires is in the range of 120 micrometers.
  • the coating resin covers the wires to a thickness of 20 to 50 micrometers.
  • the thickness of a conventional micromodule is of the order of 400 to 500 micrometers.
  • a plastic card has a thickness of around 760 micrometers. It is therefore common for contactless smart cards incorporating this type of micromodule to have flatness defects.
  • an objective of the present invention is to provide a method for the collective production of thin micromodules comprising an integrated coil and an integrated circuit, without increasing the cost price of the integrated circuits and without requiring assembly steps two to two of individual components.
  • Another objective of the present invention is to provide a hybrid micromodule with two operating modes, namely a conventional operating mode by means of contact pads and a non-contact operating mode by via an antenna coil, which is compact and simple to make.
  • a process for the collective production of a plurality of electronic micromodules each comprising a support plate, an integrated circuit chip comprising electrical connection pads, and at least one coil, a process comprising the steps of assembling on a support plate for a plurality of integrated circuit chips; depositing on the surface of the support plate an electrically insulating layer covering all of the chips; making in the insulating layer a plurality of openings facing the connection pads of the chips; collectively produce, on the support plate, a plurality of flat windings forming coils; connect each coil to a corresponding chip; cut the support plate to individualize the micromodules.
  • connection of the coils to the chips is carried out by depositing a conductive material in the openings made in the insulating layer.
  • the conductive material deposited in the openings is the conductive material forming the coils.
  • the coil is produced on several conductive levels separated by insulating layers.
  • the support plate is made of silicon.
  • the step of depositing an insulating layer comprises a step of depositing a layer of polyimide and a step of depositing a layer of silicon oxide.
  • the coils are produced by electroplating and etching a layer of copper.
  • the step of cutting the support plate is preceded by a step of depositing a protective material on one of the support plate.
  • the present invention also relates to an electronic micromodule comprising a support plate, an integrated circuit chip and at least one flat winding forming a coil, in which the chip is buried in at least one layer.
  • electrically insulating comprising at least one layer of at least one insulating material, the coil being arranged on the insulating layer.
  • the coil is connected to the chip by means of metallized openings passing through the insulating layer to reach the electrical connection areas of the chip.
  • the chip is covered by at least two insulating co ⁇ .ches, one of the two insulating layers serves as a support for the winding forming a coil, and the other insulating layer serves as a support for a conductor connecting a end of the coil to a connection pad of the chip.
  • the chip is covered by at least two insulating layers and the coil comprises at least two flat windings arranged respectively on each of the insulating layers.
  • the present invention also relates to a hybrid micromodule comprising a support plate comprising on its front face contact pads, in which the support plate comprises on its rear face a micromodule according to the invention, the micromodule comprising an integrated circuit chip with two modes of operation, with or without contact, and an insulating layer comprising openings for connecting the chip to the contact pads.
  • FIGS. 1 and 2 illustrate a first step of the method according to the invention and represent respectively by a top view and a sectional view a support plate on which are deposited silicon chips
  • FIGS. 3A to 3D are partial sectional views of the support plate and illustrate other steps of the method according to the invention
  • FIG. 4 is a top view of a first embodiment of a micromodule according to the invention.
  • FIG. 5 is an overall view of a plurality of micromodules according to the invention, produced collectively on the aforementioned support plate,
  • FIGS. 6 and 7 represent respectively by a top view and a sectional view a second embodiment of a micromodule according to the invention
  • - Figures 8 and 9 respectively represent a top view and a sectional view a third embodiment of a micromodule according to the invention
  • - Figures 10A and 10B respectively represent a bottom view and a top view a hybrid micromodule comprising a micromodule according to the invention and contact pads, and
  • FIG. 11 is the electrical diagram in the form of blocks of an integrated circuit operating without contact and a data transmission / reception station.
  • the idea of the present invention is to collectively produce coils on a support on which integrated circuit chips have previously been arranged.
  • the support is distinct from the silicon wafer from which the integrated circuits were made and the process does not increase their cost price.
  • the coils are made using low cost technology. After cutting the support, integrated micromodules are thus obtained at low cost price.
  • a first step of the method according to the invention consists in arranging a plurality of silicon chips 1 on a support plate 2 preferably chosen to be rigid.
  • the chips are fixed to the support plate 2 by any conventional means, for example by gluing, and are arranged at a distance D predetermined from each other.
  • This step is preferably automated for obtaining precise positioning of the chips.
  • test patterns 3 can be provided on the support plate 2.
  • the silicon chips 1 are integrated circuits of the contactless type and include metallized areas 4 intended to be connected to a coil.
  • the chips come from a silicon wafer airtinced by a conventional, chemical or mechanical abrasion process.
  • the thickness of the chips can be chosen to be less than that of the chips mounted on printed circuit boards due to the rigidity of the support plate 2, and can be of the order of 50 to 150 micrometers.
  • a plurality of integrated coils will then be produced on the support plate 2 which, with the chips 1, will form integrated micromodules of small thickness.
  • the support plate 2 is here a virgin silicon wafer with a standard thickness of the order of 675 micro ⁇ iètres, which will be thinned during a final step of the manufacturing process.
  • FIGS. 3A to 3C are partial sectional views of the support plate 2 illustrating various steps of the method according to the invention. The thicknesses of the various elements are not reproduced to scale for the sake of readability of the figures.
  • the support plate 2 is covered by a layer 5 of polyimide.
  • the polyimide is deposited in the liquid phase, then distributed on the plate 2 by centrifugation and polymerized in an oven. Depending on the viscosity of the polyimide, several stages of deposition, centrifugation and polymerization may be necessary to obtain a layer 5 completely covering the silicon chips 1.
  • This step is followed by a conventional step of rectification ("planarization") of the polyimide layer 5, for example by mechanical abrasion.
  • the abrasion is continued until the thickness of the polyimide layer 5 above the silicon chips 1 is fairly small, for example of the order of 10 micrometers.
  • the next step consists in depositing on the rectified layer 5 a thin layer of silicon oxide 6, with a thickness of the order of 5 to 10 micrometers.
  • the oxide is deposited in a conventional manner, for example in the vapor phase according to the CVD ("Chemical Vapor Deposition") technique.
  • the layers of polyimide 5 and of silicon oxide 6 form only one and the same insulating layer 7 in which the chip 1 is buried. Indeed, the cumulative deposition of these two materials is a particularity of the process used here, the polyimide making it possible to produce in a short time a very thick insulating layer and the oxide serving as a support for a layer of copper deposited during a step described below.
  • the insulating layer 7 is perforated to reveal openings 8 facing the metallized areas 4 of the silicon chips 1.
  • the openings 8 are produced by chemical etching of the layer insulator 7, by means of an etching mask made of photosensitive resin which has previously been exposed and developed.
  • a particular embodiment of this etching step consists in first etching the oxide layer 6 by means of a first etching agent which is not aggressive for the polyimide, with the interposition of an etching mask.
  • the etched oxide layer is then used as an etching mask to etch the polyimide layer 5, by means of a second etching agent which is not aggressive for the oxide.
  • a copper layer 9 with a thickness of the order of 20 to 50 micrometers is deposited on the insulating layer 7, for example by electrolysis.
  • the copper layer 9 enters the openings 8 and adheres to the connection areas 4 of the chip 1.
  • the copper layer 9 is then etched so as to reveal flat windings in the form of coils 10, each winding being connected to a chip silicon 1.
  • FIG. 4 represents an example of a coil 10 produced according to the method of the invention, forming with a buried chip 1 an integrated micromodule 20.
  • the coil 10 overlaps the chip 1 in a substantially offset position making it possible to make the ends of the the internal turn and the external turn with the connection pads 4 of the chip 1.
  • FIG. 5 gives an overall view of the surface of the silicon wafer 2. It can be seen that one has collectively produced a plurality of micromodules 20. Before being cut into individual micromodules, the wafer 2 is preferably covered with 'a layer of protective resin, then thinned by abrasion of its rear face until a thickness of the order of 100 ri ⁇ crometers is obtained. In the end, the micromodules according to the invention have a small thickness, of the order of 200 to 300 micrometers.
  • the method according to the invention makes it possible to produce integrated micromodules comparable in terms of size to those produced in one prior art on silicon wafers comprising integrated circuits.
  • the surface occupied by the coils chosen according to the envisaged application, has no effect on the cost price of the integrated circuits which are produced here on an independent silicon wafer.
  • the manufacturing process of the coils being significantly less expensive than the manufacturing process of integrated circuits, the cost price of the ⁇ cromodules according to the invention does not increase prohibitively as a function of the surface occupied by the coils.
  • the production of a micromodule according to the invention requires in practice only 2 to 5 etching masks (depending on the embodiment chosen) while the manufacture of an integrated circuit conventionally requires around twenty engraving masks.
  • the precision required for making the coils is only of the order of 1 to 2 micrometers, whereas an integrated circuit is produced today with an accuracy of less than a micrometer.
  • the method according to the invention offers extensive possibilities in terms of the design of ⁇ crodules, thanks to the possibility of providing several conductive levels, here several copper levels separated by insulating layers.
  • several conductive levels can be provided to increase the number of windings of the coil.
  • a compromise can be made between an extension of the number of windings in the plane of the support plate and an extension of the number of windings on several conductive levels.
  • Figures 6 and 7, 8 and 9 show two other examples of embodiment of micromodules according to the invention.
  • the sculpture 30 illustrated in FIGS. 6 and 7 comprises a coil 31 of larger size than that of the micromodule of FIG. 4, the coil 31 surrounding here the silicon chip 1.
  • the connection of the external turn of the coil 31 to the 'one of the metallized areas 4 of the silicon chip is provided by a conductive track 32 made of copper arranged on a first insulating layer 33, the coil 31 being arranged on a second insulating layer 34.
  • the connection of the track 32 to the coil 31 is provided by an opening 35 in the layer 34 and its connection to the metallized area 4 is provided by an opening 36 in the layer 33.
  • the internal turn of the coil 3 is connected to the other metallized area 4 by via two superimposed openings 37, 38 made in the insulating layers 33, 34.
  • An alternative embodiment consists in inverting the relative positions of the coil 31 and the track 32 on each of the necks insulating shields.
  • the micromodule 40 shown in Figures 8 and 9 has two insulating layers 41, 42 and a coil 43 comprising two flat windings 44, 45 superimposed and connected in series.
  • the first winding 44 shown in dotted lines in FIG. 8, is deposited on the insulating layer 41.
  • One of its ends is connected to a metallized pad 4 of the chip 1 via an opening 46 formed in the first insulating layer 41.
  • the other end of the winding 44 is connected to one end of the second winding 45 via an opening 47 made in the second insulating layer 42.
  • the other end of the winding 45 is connected to the other metallized area 4 of the chip 1 by means of two superimposed openings 48, 49 made in the two insulating layers 41, 42.
  • FIGS. 10A and 10B respectively represent the rear face 60-1 and the front face 60-2 of a hybrid micromodule 60 for a smart card with two operating modes.
  • the micromodule 60 comprises a support plate 61 of small thickness, for example an epoxy plate.
  • a micromodule 50 according to the invention comprising a support wafer 2 and a coil 51 surrounding a silicon chip 52 buried in an insulating layer 53.
  • the coil 51 produced on two first levels of the insulating layer 53, is covered by a third level of the insulating layer 53 and / or by a protective resin.
  • the silicon chip 52 is an integrated circuit with two operating modes of a known type, for example that described in application WO 97/49059.
  • the chip 52 thus comprises two metallized areas 4 connected to the coil 51, for the contactless operating mode, and metallized areas 54 for the contacting operating mode.
  • the pads 54 are accessible through openings 55 leading to the open air, formed in the insulating layer 53 as well as, if necessary, in the protective resin.
  • the pads 54 are electrically connected, via wires 62 of aluminum or gold and orifices 63 made in the support plate 61, to contact pads C1 to C6 of the ISO 7816 type. arranged on the front face 60-2 of the ⁇ cror ⁇ odule hybrid 60 ( Figure 10B).
  • the micromodule 60 comprises two other areas C7 to C8 provided for by the above-mentioned standard but generally not used.
  • the integrated circuit 52 can be activated via the contact pads C1 to C6 or by electromagnetic induction.
  • the location occupied by the micromodule 50 on the rear face 60-1 is shown in dotted lines in FIG. 10B. It can be seen that the tracks C1 to C8 do not cover the corresponding location on the front face 60-2 so as not to form a screen for the circulation of a magnetic field in the coil 51.
  • the hybrid cromodule rr 60 according to the invention thus offers good magnetic permeability and the ranges C1 to C8 do not significantly decrease the communication distance.
  • the hybrid micromodule which has just been described can receive any type of micronxxrule according to the invention, for example the micromodule shown in FIG. 4 in which the coil overlaps the integrated circuit.
  • the insulating layers on which the upper conductive levels of a micromodule according to the invention rest may be simple oxide layers in order to limit the number of manufacturing steps, or include an alternation of oxide layers and polyimide / oxide layers.
  • the method according to the invention is not limited to the technological sector which has just been described and can be implemented with any technology making it possible to bury a silicon chip in an insulating layer, then to deposit or integrate a coil on or in the insulating layer.
  • FIG. 11 very schematically represents an example of architecture of an integrated circuit IC operating without contact, communicating by electromagnetic induction with a station RD for transmitting and / or receiving data.
  • the circuit IC and the station RD are each equipped with an antenna coil, respectively Lp, Ls.
  • the IC circuit includes an input capacity Cp, a central unit UC to microprocessor or wired logic, a MEM memory, a diode bridge Pd, a demodulator-decoder circuit DD and a modulator-coder circuit MC.
  • the input capacitance Cp forms with the coil Lp a resonant circuit LpCp of natural frequency Fp.
  • the demodulator DD, the modulator MC and the diode bridge Pd are connected in parallel with the antenna circuit LpCp.
  • the central unit UC communicates the data to be transmitted to the modulator circuit MC which modulates the load of the coil Lp according to the data which it receives, according to a predetermined coding.
  • the load modulations are reflected by inductive coupling on the coil Ls and are detected by the station Rd.
  • the extraction of the data received is ensured by an inverse demodulation and decoding operation.
  • the station RD modulates the amplitude of the magnetic field as a function of the data to be transmitted, according to a predetermined coding.
  • the circuit DD demodulates the voltage Vp, decodes the data received and sends them to the central unit UC, which can load them into the memory MEM.

Abstract

The invention concerns an electronic micromodule (30) comprising a support wafer (2), an integrated circuit chip (1) and at least a flat winding forming a coil (31). The invention is characterised in that the chip is embedded in at least one layer (34) of at least an insulating material, the coil (31) being arranged on the insulating layer.

Description

MIŒCH3DULE ELECTRONIQUE INTEGRE ET PROCEDE DE FABRICATION D'UN INTEGRATED ELECTRONIC MICROCHRON AND METHOD FOR MANUFACTURING A
TEL MICRCM3DULESUCH MICRCM3DULE
La présente invention concerne un micromodule électronique comprenant une plaquette support, une puce de circuit intégré, et au moins un enroulement plat formant une bobine d'antenne.The present invention relates to an electronic micromodule comprising a support plate, an integrated circuit chip, and at least one flat winding forming an antenna coil.
Ces dernières années, on a développé des circuits intégrés fonctionnant sans contact par l'intermédiaire d'une bobine d'antenne, comprenant des moyens pour recevoir ou émettre des données par couplage inductif en présence d'un champ magnétique émis par une station d'émission et/ou réception de données.In recent years, integrated circuits operating without contact have been developed via an antenna coil, comprising means for receiving or transmitting data by inductive coupling in the presence of a magnetic field emitted by a radio station. transmission and / or reception of data.
De tels circuits intégrés, ou transpondeurs passifs, permettent de réaliser divers objets portatifs électroniques fonctionnant sans contact comme des cartes à puce, des étiquettes électroniques, des jetons électroniques, ...Such integrated circuits, or passive transponders, make it possible to produce various portable electronic objects operating without contact, such as smart cards, electronic labels, electronic tokens, etc.
La présente invention concerne la fabrication de tels objets portatifs, et plus particulièrement la fabrication de la partie électronique de ces objets portatifs.The present invention relates to the manufacture of such portable objects, and more particularly to the manufacture of the electronic part of these portable objects.
Le procédé le plus généralement utilisé pour réaliser la partie électronique d'un objet portatif fonctionnant sans contact consiste à prévoir une plaquette support sur laquelle on dépose une bobine et une puce de silicium. La bobine est ensuite connectée à la puce et l'ensemble est recouvert d'une résine de protection. Généralement, la plaquette support est une plaquette de circuit imprimé. La bobine est un fil de cuivre rapporté par collage ou une bande de cuivre gravée. La connexion bobine/puce est assurée par des fils métalliques soudés uitrasoniquement . L'ensemble forme un micromodule électronique destiné à être introduit dans le corps d'un objet portatif (carte plastique, jeton, pastille, clef...) ou fixé à sa surface.The most generally used method for producing the electronic part of a portable object operating without contact consists in providing a support plate on which a coil and a silicon chip are deposited. The coil is then connected to the chip and the assembly is covered with a protective resin. Generally, the support board is a printed circuit board. The coil is a copper wire bonded or an engraved copper strip. The coil / chip connection is ensured by metallic wires welded uitrasonically. The assembly forms an electronic micromodule intended to be introduced into the body of a portable object (plastic card, token, sticker, key, etc.) or fixed to its surface.
Ce procédé présente 1 ' inconvénient de nécessiter diverses étapes de manutention, de manipulation des éléments constitutifs des riύcromodules, d'assemblage, de câblage, de contrôle... qui grèvent le prix de revient des irάcromodules et limitent les cadences de production.This method has the disadvantage of requiring various stages of handling, of manipulation of the constituent elements riύcromodules, assembly, wiring, control ... which add to the cost price of irάcromodules and limit production rates.
Par ailleurs, ce procédé ne permet pas de réaliser des micromodules de très faible épaisseur. Ainsi, la plaquette de circuit imprimé présente généralement une épaisseur de 1 ' ordre de 150 micromètres, la puce de silicium une épaisseur de l'ordre de 150 micromètres après abrasion chimique ou mécanique de sa face arrière, et la hauteur des boucles formées par les fils de câblage est de l'ordre de 120 micromètres. Enfin, la résine d'enrobage recouvre les fils sur une épaisseur de 20 à 50 micromètres. Au total, l'épaisseur d'un micromodule classique est de l'ordre de 400 à 500 micromètres. En comparaison, une carte plastique présente une épaisseur de 1 'ordre de 760 micromètres . Ainsi, il est fréquent, que des cartes à puce sans contact incorporant ce type de micromodule présentent des défauts de planéité.Furthermore, this method does not allow micromodules of very small thickness to be produced. Thus, the printed circuit board generally has a thickness of around 150 micrometers, the silicon chip a thickness of around 150 micrometers after chemical or mechanical abrasion of its rear face, and the height of the loops formed by the wiring wires is in the range of 120 micrometers. Finally, the coating resin covers the wires to a thickness of 20 to 50 micrometers. In total, the thickness of a conventional micromodule is of the order of 400 to 500 micrometers. In comparison, a plastic card has a thickness of around 760 micrometers. It is therefore common for contactless smart cards incorporating this type of micromodule to have flatness defects.
On connaît par ailleurs divers procédés permettant de réaliser collectivement une pluralité de bobines sur une tranche de silicium (wafer) comportant une pluralité de circuits intégrés, par exemple le procédé décrit dans le brevet US 4 857 893. Après découpe de la tranche de silicium, on obtient des micromodules intégrés de faible épaisseur. Les étapes de manutention, d'assemblage et de connexion des puces et des bobines sont supprimées.Various methods are also known which make it possible to collectively produce a plurality of coils on a silicon wafer comprising a plurality of integrated circuits, for example the method described in patent US 4,857,893. After cutting the silicon wafer, small, integrated micromodules are obtained. The steps for handling, assembling and connecting the chips and the coils are eliminated.
Cependant, la surface offerte par une puce de silicium, de quelques millimètres carrés, est insuffisante pour réaliser une bobine d' inductance élevée . Les circuits intégrés pourvus d'une bobine intégrée demeurent ainsi réservés à des applications dites "de proximité", où la distance de communication par induction électromagnétique est faible et de 1 ' ordre du millimètre .However, the surface offered by a silicon chip, of a few square millimeters, is insufficient to produce a high inductance coil. Integrated circuits provided with an integrated coil thus remain reserved for so-called "proximity" applications, where the communication distance by electromagnetic induction is small and of the order of a millimeter.
Il est par ailleurs envisageable de réaliser sur une tranche de silicium des bobines de plus grandes dimensions, par exemple des bobines entourant les zones où se trouvent les circuits intégrés. Cette solution présente toutefois 1 ' inconvénient de diminuer le nombre de circuits intégrés pouvant être réalisés collectivement sur une même tranche de silicium et d'augmenter leur prix de revient. Dans l'industrie du semiconducteur, le prix de revient d'une puce de silicium est en effet déterminé par le coût de production de la tranche de silicium divisé par le nombre de puces réalisées. Ainsi, parIt is also conceivable to produce on a silicon wafer coils of larger dimensions, for example coils surrounding the areas where the integrated circuits are located. However, this solution presents 1 drawback of reducing the number of integrated circuits which can be produced collectively on the same silicon wafer and of increasing their cost price. In the semiconductor industry, the cost price of a silicon chip is in fact determined by the production cost of the silicon wafer divided by the number of chips produced. So by
2 exemple, la réalisation de bobines de 6 mm sur une tranche de silicium comportant des circuits intégrés d'une surface de 2 mm multiplie par trois le prix de revient de chaque circuit intégré. En définitive, les procédés consistant à intégrer des circuits électroniques et des bobines sur une même tranche de silicium n'apparaissent pas avantageux malgré le gain de main d'oeuvre que représente la suppression des étapes d'assemblage et de câblage des bobines et des circuits intégrés. On connaît enfin diverses filières technologiques permettant de réaliser à faible coût et de façon collective des bobines intégrées, notamment la filière des multicouches polyimide/oxyde de silicium /cuivre sur tranche de silicium. Une fois individualisées, les bobines se présentent sous la forme de puces de faibles dimensions qui peuvent être assemblées et connectées à des puces de circuits intégrés. On retrouve toutefois les problèmes de main d'oeuvre dus à la nécessité de manipuler, assembler et connecter deux par deux des composants individuels de petite taille. Ainsi, un objectif de la présente invention est de prévoir un procédé permettant de fabriquer collectivement des micromodules de faible épaisseur comprenant une bobine intégrée et un circuit intégré, sans augmentation du prix de revient des circuits intégrés et sans nécessiter des étapes d'assemblage deux à deux de composants individuels.2 example, the production of coils of 6 mm on a silicon wafer comprising integrated circuits with a surface of 2 mm multiplies by three the cost price of each integrated circuit. Ultimately, the methods of integrating electronic circuits and coils on the same silicon wafer do not appear advantageous despite the saving in labor represented by the elimination of the steps of assembling and wiring the coils and circuits. integrated. Finally, various technological fields are known which allow integrated coils to be produced at low cost and collectively, in particular the polyimide / silicon oxide / copper multilayer sector on silicon wafer. Once individualized, the coils are in the form of small chips which can be assembled and connected to integrated circuit chips. However, there are labor problems due to the need to handle, assemble and connect two by two individual components of small size. Thus, an objective of the present invention is to provide a method for the collective production of thin micromodules comprising an integrated coil and an integrated circuit, without increasing the cost price of the integrated circuits and without requiring assembly steps two to two of individual components.
Un autre objectif de la présente invention est de prévoir un micromodule hybride à deux modes de fonctionnement, à savoir un mode de fonctionnement conventionnel par 1 ' intermédiaire de plages de contact et un mode de fonctionnement sans contact par l'intermédiaire d'une bobine d'antenne, qui soit de faible encombrement et simple à réaliser.Another objective of the present invention is to provide a hybrid micromodule with two operating modes, namely a conventional operating mode by means of contact pads and a non-contact operating mode by via an antenna coil, which is compact and simple to make.
Ces objectifs sont atteints grâce à un procédé de fabrication collective d'une pluralité de micromodules électroniques comprenant chacun une plaquette support, une puce de circuit intégré comportant des plages de connexion électrique, et au moins une bobine, procédé comprenant les étapes consistant à assembler sur une plaque support une pluralité de puces de circuits intégrés ; déposer à la surface de la plaque support une couche électriquement isolante recouvrant 1 ' ensemble des puces ; pratiquer dans la couche isolante une pluralité d'ouvertures en regard des plages de connexion des puces ; réaliser collectivement, sur la plaque support, une pluralité d'enroulements plats formant bobines ; connecter chaque bobine à une puce correspondante ; découper la plaque support pour individualiser les micromodules.These objectives are achieved by a process for the collective production of a plurality of electronic micromodules, each comprising a support plate, an integrated circuit chip comprising electrical connection pads, and at least one coil, a process comprising the steps of assembling on a support plate for a plurality of integrated circuit chips; depositing on the surface of the support plate an electrically insulating layer covering all of the chips; making in the insulating layer a plurality of openings facing the connection pads of the chips; collectively produce, on the support plate, a plurality of flat windings forming coils; connect each coil to a corresponding chip; cut the support plate to individualize the micromodules.
Avantageusement, la connexion des bobines aux puces est réalisée en déposant un matériau conducteur dans les ouvertures pratiquées dans la couche isolante. Avantageusement, le matériau conducteur déposé dans les ouvertures est le matériau conducteur formant les bobines.Advantageously, the connection of the coils to the chips is carried out by depositing a conductive material in the openings made in the insulating layer. Advantageously, the conductive material deposited in the openings is the conductive material forming the coils.
Selon un mode de réalisation, on réalise la bobine sur plusieurs niveaux conducteurs séparés par des couches isolantes.According to one embodiment, the coil is produced on several conductive levels separated by insulating layers.
Selon un mode de réalisation, la plaque support est en silicium. L'étape de dépôt d'une couche isolante comprend une étape de dépôt d'une couche de polyimide et une étape de dépôt d'une couche d'oxyde de silicium. Les bobines sont réalisées par dépôt électrolytique et gravure d'une couche de cuivre.According to one embodiment, the support plate is made of silicon. The step of depositing an insulating layer comprises a step of depositing a layer of polyimide and a step of depositing a layer of silicon oxide. The coils are produced by electroplating and etching a layer of copper.
Selon un mode de réalisation, l'étape de découpe de la plaque support est précédée d'une étape de dépôt d'une matière de protection sur 1 ' ensemble de la plaque support .According to one embodiment, the step of cutting the support plate is preceded by a step of depositing a protective material on one of the support plate.
La présente invention concerne également un micromodule électronique comprenant une plaquette support, une puce de circuit intégré et au moins un enroulement plat formant bobine, dans lequel la puce est enterrée dans au moins une couche électriquement isolante comprenant au moins une couche d'au moins un matériau isolant, la bobine étant agencée sur la couche isolante .The present invention also relates to an electronic micromodule comprising a support plate, an integrated circuit chip and at least one flat winding forming a coil, in which the chip is buried in at least one layer. electrically insulating comprising at least one layer of at least one insulating material, the coil being arranged on the insulating layer.
Selon un mode de réalisation, la bobine est connectée à la puce par l'intermédiaire d'ouvertures métallisées traversant la couché isolante pour atteindre des plages de connexion électrique de la puce.According to one embodiment, the coil is connected to the chip by means of metallized openings passing through the insulating layer to reach the electrical connection areas of the chip.
Selon un mode de réalisation, la puce est recouverte par au moins deux coυ.ches isolantes, l'une des deux couches isolantes sert de support à l'enroulement formant bobine, et l'autre couche isolante sert de support à un conducteur reliant une extrémité de la bobine à une plage de connexion de la puce.According to one embodiment, the chip is covered by at least two insulating coυ.ches, one of the two insulating layers serves as a support for the winding forming a coil, and the other insulating layer serves as a support for a conductor connecting a end of the coil to a connection pad of the chip.
Selon un mode de réalisation, la puce est recouverte par au moins deux couches isolantes et la bobine comprend au moins deux enroulements plats agencés respectivement sur chacune des couches isolantes.According to one embodiment, the chip is covered by at least two insulating layers and the coil comprises at least two flat windings arranged respectively on each of the insulating layers.
La présente invention concerne égalc-iment un micromodule hybride comprenant une plaquette support comportant sur sa face avant des plages de contact, dans lequel la plaquette support comporte sur sa face arrière un micromodule selon 1 ' invention, le micromodule comprenant une puce de circuit intégré à deux modes de fonctionnement, avec ou sans contact, et une couche isolante comportant des ouvertures pour connecter la puce aux plages de contact . Ces objets, caractéristiques et avantages ainsi que d'autres de la présente invention seront exposés plus en détail dans la description suivante du procédé de fabrication selonThe present invention also relates to a hybrid micromodule comprising a support plate comprising on its front face contact pads, in which the support plate comprises on its rear face a micromodule according to the invention, the micromodule comprising an integrated circuit chip with two modes of operation, with or without contact, and an insulating layer comprising openings for connecting the chip to the contact pads. These objects, characteristics and advantages as well as others of the present invention will be explained in more detail in the following description of the manufacturing process according to
1 ' invention et de divers exemples de réalisation de micromodules selon l'invention, en relation avec les figures jointes parmi lesquelles :1 invention and various exemplary embodiments of micromodules according to the invention, in relation to the attached figures among which:
- les figures 1 et 2 illustrent une première étape du procédé selon 1 ' invention et représentent respectivement par une vue de dessus et une vue en coupe une plaque support sur laquelle sont déposées des puces de silicium, - les figures 3A à 3D sont des vues partielles en coupe de la plaque support et illustrent d'autres étapes du procédé selon 1 ' invention,FIGS. 1 and 2 illustrate a first step of the method according to the invention and represent respectively by a top view and a sectional view a support plate on which are deposited silicon chips, FIGS. 3A to 3D are partial sectional views of the support plate and illustrate other steps of the method according to the invention,
- la figure 4 est une vue de dessus d'un premier exemple de réalisation d'un micromodule selon l'invention,FIG. 4 is a top view of a first embodiment of a micromodule according to the invention,
- la figure 5 est une vue d'ensemble d'une pluralité de micromodules selon l'invention, réalisés collectivement sur la plaque support susmentionnée,FIG. 5 is an overall view of a plurality of micromodules according to the invention, produced collectively on the aforementioned support plate,
- les figures 6 et 7 représentent respectivement par une vue de dessus et une vue en coupe un deuxième exemple de réalisation d'un micromodule selon l'invention,FIGS. 6 and 7 represent respectively by a top view and a sectional view a second embodiment of a micromodule according to the invention,
- les figures 8 et 9 représentent respectivement par une vue de dessus et une vue en coupe un troisième exemple de réalisation d'un micromodule selon l'invention, - les figures 10A et 10B représentent respectivement par une vue de dessous et une vue de dessus un micromodule hybride comprenant un micromodule selon 1 ' invention et des plages de contact, et- Figures 8 and 9 respectively represent a top view and a sectional view a third embodiment of a micromodule according to the invention, - Figures 10A and 10B respectively represent a bottom view and a top view a hybrid micromodule comprising a micromodule according to the invention and contact pads, and
- la figure 11 est le schéma électrique sous forme de blocs d'un circuit intégré fonctionnant sans contact et d'une station d'émission/réception de données.- Figure 11 is the electrical diagram in the form of blocks of an integrated circuit operating without contact and a data transmission / reception station.
De façon générale, l'idée de la présente invention est de réaliser collectivement des bobines sur un support sur lequel ont été préalablement agencées des puces de circuits intégrés. Le support est distinct de la tranche de silicium à partir de laquelle les circuits intégrés ont été fabriqués et le procédé n'entraîne pas une augmentation de leur prix de revient. Les bobines sont réalisées au moyen d'une technologie à faible coût. On obtient ainsi, après découpe du support, des micromodules intégrés à faible prix de revient .In general, the idea of the present invention is to collectively produce coils on a support on which integrated circuit chips have previously been arranged. The support is distinct from the silicon wafer from which the integrated circuits were made and the process does not increase their cost price. The coils are made using low cost technology. After cutting the support, integrated micromodules are thus obtained at low cost price.
Une première étape du procédé selon l'invention, illustrée par les figures 1 et 2, consiste à agencer une pluralité de puces de silicium 1 sur une plaque support 2 choisie de préférence rigide. Les puces sont fixées à la plaque support 2 par tout moyen classique, par exemple par collage, et sont agencées à une distance D prédéterminée les unes des autres. Cette étape est de préférence automatisée pour l'obtention d'un positionnement précis des puces. A cet effet, des mires 3 peuvent être prévues sur la plaque support 2. Les puces de silicium 1 sont des circuits intégrés du type fonctionnant sans contact et comportent des plages métallisées 4 prévues pour être connectées à une bobine. Les puces sont issues d'une tranche de silicium airtincie par un procédé d'abrasion classique, chimique ou mécanique. L'épaisseur des puces peut être choisie inférieure à celle des puces montées sur des plaquettes de circuit imprimé en raison de la rigidité de la plaque support 2, et être de l'ordre de 50 à 150 micromètres.A first step of the method according to the invention, illustrated by FIGS. 1 and 2, consists in arranging a plurality of silicon chips 1 on a support plate 2 preferably chosen to be rigid. The chips are fixed to the support plate 2 by any conventional means, for example by gluing, and are arranged at a distance D predetermined from each other. This step is preferably automated for obtaining precise positioning of the chips. To this end, test patterns 3 can be provided on the support plate 2. The silicon chips 1 are integrated circuits of the contactless type and include metallized areas 4 intended to be connected to a coil. The chips come from a silicon wafer airtinced by a conventional, chemical or mechanical abrasion process. The thickness of the chips can be chosen to be less than that of the chips mounted on printed circuit boards due to the rigidity of the support plate 2, and can be of the order of 50 to 150 micrometers.
Selon l'invention, on va ensuite fabriquer sur la plaque support 2 une pluralité de bobines intégrées qui formeront avec les puces 1 des micromodules intégrés de faible épaisseur.According to the invention, a plurality of integrated coils will then be produced on the support plate 2 which, with the chips 1, will form integrated micromodules of small thickness.
Dans ce qui suit, on décrira un exemple de mise en oeuvre du procédé selon 1 ' invention faisant appel à la technologie polyimide/oxyde de silicium/cuivre sur substrat de silicium, utilisée dans l'art antérieur pour réaliser des bobines intégrées. Ainsi, la plaque support 2 est ici une tranche vierge de silicium d'une épaisseur standard de l'ordre de 675 microπiètres, qui sera amincie au cours d'une étape finale du procédé de fabrication.In what follows, an example of implementation of the method according to the invention will be described using the polyimide / silicon oxide / copper technology on silicon substrate, used in the prior art to produce integrated coils. Thus, the support plate 2 is here a virgin silicon wafer with a standard thickness of the order of 675 microπiètres, which will be thinned during a final step of the manufacturing process.
Les figures 3A à 3C sont des vues partielles en coupe de la plaque support 2 illustrant diverses étapes du procédé selon 1 ' invention. Les épaisseurs des divers éléments ne sont pas reproduites à l'échelle dans un souci de lisibilité des figures.FIGS. 3A to 3C are partial sectional views of the support plate 2 illustrating various steps of the method according to the invention. The thicknesses of the various elements are not reproduced to scale for the sake of readability of the figures.
Au cours de l'étape illustrée par la figure 3A, la plaque support 2 est recouverte par une couche 5 de polyimide. De façon classique, le polyimide est déposé en phase liquide, puis réparti sur la plaque 2 par centrifugation et polymérisé dans une étuve. Selon la viscosité du polyimide, plusieurs étapes de dépôt, centrifugation et polymérisation peuvent être nécessaires pour l'obtention d'une couche 5 recouvrant entièrement les puces de silicium 1. Cette étape est suivie d'une étape classique de rectification ( "planarisation" ) de la couche polyimide 5, par exemple par abrasion mécanique. De préférence, on poursuit l'abrasion jusqu'à ce que l'épaisseur de la couche de polyimide 5 au dessus des puces de silicium 1 soit assez faible, par exemple de l'ordre de 10 micromètres.During the step illustrated in FIG. 3A, the support plate 2 is covered by a layer 5 of polyimide. Conventionally, the polyimide is deposited in the liquid phase, then distributed on the plate 2 by centrifugation and polymerized in an oven. Depending on the viscosity of the polyimide, several stages of deposition, centrifugation and polymerization may be necessary to obtain a layer 5 completely covering the silicon chips 1. This step is followed by a conventional step of rectification ("planarization") of the polyimide layer 5, for example by mechanical abrasion. Preferably, the abrasion is continued until the thickness of the polyimide layer 5 above the silicon chips 1 is fairly small, for example of the order of 10 micrometers.
L'étape suivante, illustrée par la figure 3B, consiste à déposer sur la couche rectifiée 5 une fine couche d'oxyde de silicium 6, d'une épaisseur de l'ordre de 5 à 10 micromètres. L'oxyde est déposé de façon classique, par exemple en phase vapeur selon la technique CVD ("Chemical Vapor Déposition") .The next step, illustrated in FIG. 3B, consists in depositing on the rectified layer 5 a thin layer of silicon oxide 6, with a thickness of the order of 5 to 10 micrometers. The oxide is deposited in a conventional manner, for example in the vapor phase according to the CVD ("Chemical Vapor Deposition") technique.
On considérera maintenant dans un souci de simplicité que les couches de polyimide 5 et d'oxyde de silicium 6 ne forment qu'une seule et même couche isolante 7 dans laquelle la puce 1 est enterrée. En effet le dépôt cumulé de ces deux matières est une particularité du procédé utilisé ici, le polyimide permettant de réaliser en peu de temps une couche isolante de forte épaisseur et l'oxyde servant de support à une couche de cuivre déposée au cours d'une étape décrite plus loin. Au cours de l'étape illustrée par la figure 3C, on perfore la couche isolante 7 pour faire apparaître des ouvertures 8 en regard des plages métallisées 4 des puces de silicium 1. De préférence, les ouvertures 8 sont réalisées par gravure chimique de la couche isolante 7, au moyen d'un masque de gravure en résine photosensible que l'on a préalablement insolé et développé. Un mode de réalisation particulier de cette étape de gravure consiste à graver tout d'abord la couche d'oxyde 6 au moyen d'un premier agent de gravure non agressif pour le polyimide, avec interposition d'un masque de gravure. On utilise ensuite la couche d'oxyde gravée comme masque de gravure pour graver la couche de polyimide 5, au moyen d'un deuxième agent de gravure non agressif pour l'oxyde.It will now be considered for the sake of simplicity that the layers of polyimide 5 and of silicon oxide 6 form only one and the same insulating layer 7 in which the chip 1 is buried. Indeed, the cumulative deposition of these two materials is a particularity of the process used here, the polyimide making it possible to produce in a short time a very thick insulating layer and the oxide serving as a support for a layer of copper deposited during a step described below. During the step illustrated in FIG. 3C, the insulating layer 7 is perforated to reveal openings 8 facing the metallized areas 4 of the silicon chips 1. Preferably, the openings 8 are produced by chemical etching of the layer insulator 7, by means of an etching mask made of photosensitive resin which has previously been exposed and developed. A particular embodiment of this etching step consists in first etching the oxide layer 6 by means of a first etching agent which is not aggressive for the polyimide, with the interposition of an etching mask. The etched oxide layer is then used as an etching mask to etch the polyimide layer 5, by means of a second etching agent which is not aggressive for the oxide.
Au cours de l'étape illustrée par la figure 3D, on dépose sur la couche isolante 7 une couche cuivre 9 d'une épaisseur de l'ordre de 20 à 50 micromètres, par exemple par électrolyse. La couche de cuivre 9 pénètre dans les ouvertures 8 et adhère aux plages 4 de connexion de la puce 1. La couche de cuivre 9 est ensuite gravée de manière à faire apparaître des enroulements plats en forme de bobines 10, chaque enroulement étant connecté à une puce de silicium 1.During the step illustrated in FIG. 3D, a copper layer 9 with a thickness of the order of 20 to 50 micrometers is deposited on the insulating layer 7, for example by electrolysis. The copper layer 9 enters the openings 8 and adheres to the connection areas 4 of the chip 1. The copper layer 9 is then etched so as to reveal flat windings in the form of coils 10, each winding being connected to a chip silicon 1.
La figure 4 représente un exemple de bobine 10 réalisée selon le procédé de 1 ' invention, formant avec une puce enterrée 1 un micromodule intégré 20. Ici, la bobine 10 chevauche la puce 1 dans une position sensiblement décalée permettant de faire coïncider les extrémités de la spire interne et de la spire externe avec les plages de connexion 4 de la puce 1.FIG. 4 represents an example of a coil 10 produced according to the method of the invention, forming with a buried chip 1 an integrated micromodule 20. Here, the coil 10 overlaps the chip 1 in a substantially offset position making it possible to make the ends of the the internal turn and the external turn with the connection pads 4 of the chip 1.
La figure 5 donne une vue d'ensemble de la surface de la plaque de silicium 2. On voit que 1 'on a réalisé collectivement une pluralité micromodules 20. Avant d'être découpée en micromodules individuels, la plaque 2 est de préférence recouverte d'une couche de résine de protection, puis amincie par abrasion de sa face arrière jusqu'à l'obtention d'une épaisseur de l'ordre de 100 riύcromètres . Au final, les micromodules selon l'invention présentent une faible épaisseur, de l'ordre de 200 à 300 micromètres.FIG. 5 gives an overall view of the surface of the silicon wafer 2. It can be seen that one has collectively produced a plurality of micromodules 20. Before being cut into individual micromodules, the wafer 2 is preferably covered with 'a layer of protective resin, then thinned by abrasion of its rear face until a thickness of the order of 100 riύcrometers is obtained. In the end, the micromodules according to the invention have a small thickness, of the order of 200 to 300 micrometers.
Ainsi, le procédé selon l'invention permet de réaliser des micromodules intégrés comparables en termes d'encombrement à ceux réalisés dans 1 ' art antérieur sur des tranches de silicium comportant des circuits intégrés. Toutefois, la surface occupée par les bobines, choisie en fonction de l'application envisagée, n ' a pas d' incidence sur le prix de revient des circuits intégrés qui sont réalisés ici sur une tranche de silicium indépendante. Le processus de fabrication des bobines étant nettement moins coûteux que le processus de fabrication des circuits intégrés, le prix de revient des πύcromodules selon l'invention n'augmente pas de façon rédhibitoire en fonction de la surface occupée par les bobines. En effet, la réalisation d'un micromodule selon 1 ' invention ne nécessite en pratique que 2 à 5 masques de gravure (selon le mode de réalisation choisi) alors que la fabrication d'un circuit intégré nécessite classiquement une vingtaine de masques de gravure. En outre, la précision requise pour la réalisation des bobines n'est que de l'ordre de 1 à 2 micromètres alors qu'un circuit intégré est réalisé aujourd'hui avec une précision inférieure au micromètre. D'autre part, le procédé selon l'invention offre des possibilités étendues en termes de conception des π cro odules, grâce à la possibilité de prévoir plusieurs niveaux conducteurs, ici plusieurs niveaux de cuivre séparés par des couches isolantes. De façon générale, plusieurs niveaux conducteurs peuvent être prévus pour démultiplier le nombre d'enroulements de la bobine. Un compromis peut être fait entre une extension du nombre d'enroulements dans le plan de la plaque support et une extension du nombre d'enroulements sur plusieurs niveaux conducteurs . Pour fixer les idées, les figures 6 et 7, 8 et 9 représentent deux autres exemples de réalisation de micromodules selon l'invention.Thus, the method according to the invention makes it possible to produce integrated micromodules comparable in terms of size to those produced in one prior art on silicon wafers comprising integrated circuits. However, the surface occupied by the coils, chosen according to the envisaged application, has no effect on the cost price of the integrated circuits which are produced here on an independent silicon wafer. The manufacturing process of the coils being significantly less expensive than the manufacturing process of integrated circuits, the cost price of the πύcromodules according to the invention does not increase prohibitively as a function of the surface occupied by the coils. Indeed, the production of a micromodule according to the invention requires in practice only 2 to 5 etching masks (depending on the embodiment chosen) while the manufacture of an integrated circuit conventionally requires around twenty engraving masks. In addition, the precision required for making the coils is only of the order of 1 to 2 micrometers, whereas an integrated circuit is produced today with an accuracy of less than a micrometer. On the other hand, the method according to the invention offers extensive possibilities in terms of the design of π crodules, thanks to the possibility of providing several conductive levels, here several copper levels separated by insulating layers. In general, several conductive levels can be provided to increase the number of windings of the coil. A compromise can be made between an extension of the number of windings in the plane of the support plate and an extension of the number of windings on several conductive levels. To fix the ideas, Figures 6 and 7, 8 and 9 show two other examples of embodiment of micromodules according to the invention.
Le iriicromodule 30 illustré sur les figures 6 et 7 comporte une bobine 31 de plus grande taille que celle du micromodule de la figure 4, la bobine 31 entourant ici la puce de silicium 1. La connexion de la spire externe de la bobine 31 à l'une des plages métallisées 4 de la puce de silicium est assurée par une piste conductrice 32 en cuivre agencée sur une première couche isolante 33, la bobine 31 étant agencée sur une deuxième couche isolante 34. La connexion de la piste 32 à la bobine 31 est assurée par une ouverture 35 pratiquée dans la couche 34 et sa connexion à la plage métallisée 4 est assurée par une ouverture 36 pratiquée dans la couche 33. Enfin, la spire interne de la bobine 3 est connectée à l'autre plage métallisée 4 par l'intermédiaire de deux ouvertures superposées 37, 38 pratiquées dans les couches isolantes 33, 34. Une variante de réalisation consiste à intervertir les positions relatives de la bobine 31 et de la piste 32 sur chacune des couches isolantes.The iriicromodule 30 illustrated in FIGS. 6 and 7 comprises a coil 31 of larger size than that of the micromodule of FIG. 4, the coil 31 surrounding here the silicon chip 1. The connection of the external turn of the coil 31 to the 'one of the metallized areas 4 of the silicon chip is provided by a conductive track 32 made of copper arranged on a first insulating layer 33, the coil 31 being arranged on a second insulating layer 34. The connection of the track 32 to the coil 31 is provided by an opening 35 in the layer 34 and its connection to the metallized area 4 is provided by an opening 36 in the layer 33. Finally, the internal turn of the coil 3 is connected to the other metallized area 4 by via two superimposed openings 37, 38 made in the insulating layers 33, 34. An alternative embodiment consists in inverting the relative positions of the coil 31 and the track 32 on each of the necks insulating shields.
Le micromodule 40 représenté sur les figures 8 et 9 comporte deux couches isolantes 41, 42 et une bobine 43 comprenant deux enroulements plats 44, 45 superposés et connectés en série. Le premier enroulement 44, représenté en traits pointillés sur la figure 8, est déposé sur la couche isolante 41. L'une de ses extrémités est connectée à une plage métallisée 4 de la puce 1 par l'intermédiaire d'une ouverture 46 pratiquée dans la première couche isolante 41. L'autre extrémité de 1 ' enroulement 44 est connectée à une extrémité du deuxième enroulement 45 par l'intermédiaire d'une ouverture 47 pratiquée dans la deuxième couche isolante 42. Enfin, l'autre extrémité de 1 ' enroulement 45 est connectée à 1 ' autre plage métallisée 4 de la puce 1 par l'intermédiaire de deux ouvertures superposées 48, 49 pratiquées dans les deux couches isolantes 41, 42.The micromodule 40 shown in Figures 8 and 9 has two insulating layers 41, 42 and a coil 43 comprising two flat windings 44, 45 superimposed and connected in series. The first winding 44, shown in dotted lines in FIG. 8, is deposited on the insulating layer 41. One of its ends is connected to a metallized pad 4 of the chip 1 via an opening 46 formed in the first insulating layer 41. The other end of the winding 44 is connected to one end of the second winding 45 via an opening 47 made in the second insulating layer 42. Finally, the other end of the winding 45 is connected to the other metallized area 4 of the chip 1 by means of two superimposed openings 48, 49 made in the two insulating layers 41, 42.
Les figures 10A et 10B représentent respectivement la face arrière 60-1 et la face avant 60-2 d'un micromodule hybride 60 pour carte à puce à deux modes de fonctionnement. Le micromodule 60 comprend une plaquette support 61 de faible épaisseur, par exemple une plaquette en époxy. Sur la face arrière 60-1 de la plaquette 61 est collé un micromodule 50 selon 1 ' invention, du type décrit en relation avec les figures 6 ou 8, comprenant une plaquette support 2 et une bobine 51 entourant une puce de silicium 52 enterrée dans une couche isolante 53. La bobine 51, réalisée sur deux premiers niveaux de la couche isolante 53, est recouverte par un troisième niveau de la couche isolante 53 et/ou par une résine de protection. La puce de silicium 52 est un circuit intégré à deux modes de fonctionnement d'un type connu, par exemple celui décrit dans la demande WO 97/49059. La puce 52 comporte ainsi deux plages métallisées 4 connectées à la bobine 51, pour le mode de fonctionnement sans contact, et des plages métallisées 54 pour le mode de fonctionnement avec contact. Les plages 54 sont accessibles grâce à des ouvertures 55 débouchant à l'air libre, pratiquées dans la couche isolante 53 ainsi que, le cas échéant, dans la résine de protection. Les plages 54 sont reliées électriquement, par l'intermédiaire de fils 62 d'aluminium ou d'or et d'orifices 63 pratiqués dans la plaquette support 61, à des plages de contact Cl à C6 du type ISO 7816 agencées sur la face avant 60-2 du ιτ crorτιodule hybride 60 (figure 10B) . Sur la face avant 60-1, le micromodule 60 comporte deux autres plages C7 à C8 prévues par la norme précitée mais généralement non utilisées. Ainsi, le circuit intégré 52 peut être activé par 1 ' intermédiaire des plages de contact Cl à C6 ou par induction électromagnétique. L'emplacement occupé par le micromodule 50 sur la face arrière 60-1 est représenté en traits pointillés sur la figure 10B. On voit que les plages Cl à C8 ne recouvrent pas l'emplacement correspondant sur la face avant 60-2 afin de ne pas former écran à la circulation d'un champ magnétique dans la bobine 51. Le rr cromodule hybride 60 selon l'invention offre ainsi une bonne perméabilité magnétique et les plages Cl à C8 ne dirninuent pas de façon sensible la distance de communication. Bien entendu, le micromodule hybride qui vient d'être décrit peut recevoir tout type de micronxxrule selon 1 ' invention, par exemple le micromodule représenté en figure 4 dans lequel la bobine chevauche le circuit intégré.FIGS. 10A and 10B respectively represent the rear face 60-1 and the front face 60-2 of a hybrid micromodule 60 for a smart card with two operating modes. The micromodule 60 comprises a support plate 61 of small thickness, for example an epoxy plate. On the rear face 60-1 of the wafer 61 is stuck a micromodule 50 according to the invention, of the type described in relation to FIGS. 6 or 8, comprising a support wafer 2 and a coil 51 surrounding a silicon chip 52 buried in an insulating layer 53. The coil 51, produced on two first levels of the insulating layer 53, is covered by a third level of the insulating layer 53 and / or by a protective resin. The silicon chip 52 is an integrated circuit with two operating modes of a known type, for example that described in application WO 97/49059. The chip 52 thus comprises two metallized areas 4 connected to the coil 51, for the contactless operating mode, and metallized areas 54 for the contacting operating mode. The pads 54 are accessible through openings 55 leading to the open air, formed in the insulating layer 53 as well as, if necessary, in the protective resin. The pads 54 are electrically connected, via wires 62 of aluminum or gold and orifices 63 made in the support plate 61, to contact pads C1 to C6 of the ISO 7816 type. arranged on the front face 60-2 of the ιτ crorτιodule hybrid 60 (Figure 10B). On the front face 60-1, the micromodule 60 comprises two other areas C7 to C8 provided for by the above-mentioned standard but generally not used. Thus, the integrated circuit 52 can be activated via the contact pads C1 to C6 or by electromagnetic induction. The location occupied by the micromodule 50 on the rear face 60-1 is shown in dotted lines in FIG. 10B. It can be seen that the tracks C1 to C8 do not cover the corresponding location on the front face 60-2 so as not to form a screen for the circulation of a magnetic field in the coil 51. The hybrid cromodule rr 60 according to the invention thus offers good magnetic permeability and the ranges C1 to C8 do not significantly decrease the communication distance. Of course, the hybrid micromodule which has just been described can receive any type of micronxxrule according to the invention, for example the micromodule shown in FIG. 4 in which the coil overlaps the integrated circuit.
En pratique, les couches isolantes sur lesquelles reposent les niveaux conducteurs supérieurs d'un micromodule selon l'invention peuvent être de simples couches d'oxyde afin de limiter le nombre d'étapes de fabrication, ou comporter une alternance de couches d'oxyde et de couches polyimide/oxyde.In practice, the insulating layers on which the upper conductive levels of a micromodule according to the invention rest may be simple oxide layers in order to limit the number of manufacturing steps, or include an alternation of oxide layers and polyimide / oxide layers.
De façon générale, le procédé selon l'invention n'est pas limité à la filière technologique qui vient d'être décrite et peut être mis en oeuvre avec toute technologie permettant d'enterrer une puce de silicium dans une couche isolante, puis de déposer ou intégrer une bobine sur ou dans la couche isolante.In general, the method according to the invention is not limited to the technological sector which has just been described and can be implemented with any technology making it possible to bury a silicon chip in an insulating layer, then to deposit or integrate a coil on or in the insulating layer.
A titre de rappel, la figure 11 représente très schématiquement un exemple d'architecture de circuit intégré IC fonctionnant sans contact, communiquant par induction électromagnétique avec une station RD d'émission et/ou de réception de données. Le circuit IC et la station RD sont équipés chacun d'une bobine d'antenne, respectivement Lp, Ls. Le circuit IC comprend une capacité d'entrée Cp, une unité centrale UC à microprocesseur ou à logique câblée, une mémoire MEM, un pont de diodes Pd, un circuit démodulateur-décodeur DD et un circuit modulateur-codeur MC. La capacité d'entrée Cp forme avec la bobine Lp un circuit résonant LpCp de fréquence propre Fp. Le démodulateur DD, le modulateur MC et le pont de diodes Pd sont connectés en parallèle avec le circuit d'antenne LpCp.As a reminder, FIG. 11 very schematically represents an example of architecture of an integrated circuit IC operating without contact, communicating by electromagnetic induction with a station RD for transmitting and / or receiving data. The circuit IC and the station RD are each equipped with an antenna coil, respectively Lp, Ls. The IC circuit includes an input capacity Cp, a central unit UC to microprocessor or wired logic, a MEM memory, a diode bridge Pd, a demodulator-decoder circuit DD and a modulator-coder circuit MC. The input capacitance Cp forms with the coil Lp a resonant circuit LpCp of natural frequency Fp. The demodulator DD, the modulator MC and the diode bridge Pd are connected in parallel with the antenna circuit LpCp.
En présence d'un chaπp magnétique alternatif émis par la bobine Ls de la station RD, une tension induite Vp apparaît aux bornes du circuit d'antenne LpCp. Cette tension Vp est redressée par le pont Pd pour fournir au circuit IC une tension continue d'alimentation Vcc. Pour la transmission de données numériques à la station RD, l'unité centrale UC communique les données à émettre au circuit modulateur MC qui module la charge de la bobine Lp en fonction des données qu'il reçoit, selon un codage prédéterminé. Les modulations de charge se répercutent par couplage inductif sur la bobine Ls et sont détectées par la station Rd. L'extraction des données reçues est assurée par une opération inverse de démodulation et de décodage. Pour la transmission de données numériques vers la puce IC, la station RD module l'amplitude du champ magnétique en fonction des données à émettre, selon un codage prédéterminé. Dans la puce IC, le circuit DD démodule la tension Vp, décode les données reçues et les envoie à l'unité centrale UC, qui peut les charger dans la mémoire MEM. In the presence of an alternating magnetic chain emitted by the coil Ls of the station RD, an induced voltage Vp appears at the terminals of the antenna circuit LpCp. This voltage Vp is rectified by the bridge Pd to supply the circuit IC with a direct supply voltage Vcc. For the transmission of digital data to the station RD, the central unit UC communicates the data to be transmitted to the modulator circuit MC which modulates the load of the coil Lp according to the data which it receives, according to a predetermined coding. The load modulations are reflected by inductive coupling on the coil Ls and are detected by the station Rd. The extraction of the data received is ensured by an inverse demodulation and decoding operation. For the transmission of digital data to the IC chip, the station RD modulates the amplitude of the magnetic field as a function of the data to be transmitted, according to a predetermined coding. In the IC chip, the circuit DD demodulates the voltage Vp, decodes the data received and sends them to the central unit UC, which can load them into the memory MEM.

Claims

REVENDICATIONS
1. Procédé de fabrication collective d'une pluralité de π cromodules électroniques (20, 30, 40) comprenant chacun une plaquette support, une puce de circuit intégré (1) comportant des plages de connexion électrique (4) , et au moins une bobine (10, 31, 43), caractérisé en ce qu'il comprend les étapes consistant à assembler sur une plaque support (2) une pluralité de puces de circuits intégrés (1) ; déposer à la surface de la plaque support (2) une couche électriquement isolante (5, 6, 7, 33, 34, 41, 42) recouvrant l'ensemble des puces ; pratiquer dans la couche isolante une pluralité d'ouvertures (8, 36, 37, 38, 46, 48, 49) en regard des plages (4) de connexion des puces ; réaliser collectivement, sur la plaque support, une pluralité d'enroulements plats formant bobines (10, 31, 43, 44, 45) ; connecter chaque bobine à une puce correspondante, et découper la plaque support (2) pour individualiser les πύcromodules .1. Method for the collective production of a plurality of π electronic cromodules (20, 30, 40) each comprising a support plate, an integrated circuit chip (1) comprising electrical connection pads (4), and at least one coil (10, 31, 43), characterized in that it comprises the steps consisting in assembling on a support plate (2) a plurality of integrated circuit chips (1); depositing on the surface of the support plate (2) an electrically insulating layer (5, 6, 7, 33, 34, 41, 42) covering all the chips; making in the insulating layer a plurality of openings (8, 36, 37, 38, 46, 48, 49) facing the pads (4) of connection of the chips; collectively produce, on the support plate, a plurality of flat windings forming coils (10, 31, 43, 44, 45); connect each coil to a corresponding chip, and cut the support plate (2) to individualize the πύcromodules.
2. Procédé selon la revendication 1, dans lequel la connexion des bobines aux puces est réalisée en déposant un matériau conducteur dans les ouvertures pratiquées dans la couche isolante . 2. Method according to claim 1, in which the connection of the coils to the chips is carried out by depositing a conductive material in the openings made in the insulating layer.
3. Procédé selon la revendication 2, dans lequel le matériau conducteur déposé dans les ouvertures est le matériau conducteur formant les bobines.3. The method of claim 2, wherein the conductive material deposited in the openings is the conductive material forming the coils.
4. Procédé selon 1 'une des revendications 1 à 3 , dans lequel on réalise la bobine (31, 32, 43, 44, 45) sur plusieurs niveaux conducteurs séparés par des couches isolantes (33, 34, 41, 42) .4. Method according to one of claims 1 to 3, in which the coil (31, 32, 43, 44, 45) is produced on several conductive levels separated by insulating layers (33, 34, 41, 42).
5. Procédé selon 1 'une des revendications 1 à 4, dans lequel la plaque support (2) est en silicium, l'étape de dépôt d'une couche isolante comprend une étape de dépôt d'une couche de polyimide et une étape de dépôt d'une couche d'oxyde de silicium, et les bobines sont réalisées par dépôt électrolytique et gravure d'une couche de cuivre. 5. Method according to one of claims 1 to 4, in which the support plate (2) is made of silicon, the step of depositing an insulating layer comprises a step of depositing a layer of polyimide and a step of deposition of a layer of silicon oxide, and the coils are produced by electrolytic deposition and etching of a layer of copper.
6. Procédé selon l'une des revendications l à 5, dans lequel l'étape de découpe de la plaque support est précédée d'une étape de dépôt d'une matière de protection sur l'ensemble de la plaque support. 7. Micromodule électronique (20, 30, 40, 50) comprenant une plaquette support (2) , une puce de circuit intégré (1, 52) et au moins un enroulement plat formant bobine (10, 31, 43, 44, 45, 51) , caractérisé en ce que la puce est enterrée dans au moins une couche électriquement isolante (5, 6, 6. Method according to one of claims l to 5, wherein the step of cutting the support plate is preceded by a step of depositing a protective material on the entire support plate. 7. Electronic micromodule (20, 30, 40, 50) comprising a support plate (2), an integrated circuit chip (1, 52) and at least one flat winding forming a coil (10, 31, 43, 44, 45, 51), characterized in that the chip is buried in at least one electrically insulating layer (5, 6,
7, 33, 34, 41, 42, 53) comprenant au moins une couche d'au moins un matériau isolar-t, et en ce que la bobine est agencée sur la couche isolante.7, 33, 34, 41, 42, 53) comprising at least one layer of at least one isolar-t material, and in that the coil is arranged on the insulating layer.
8. Micromodule selon la revendication 7, dans lequel la bobine est connectée à la puce par 1 ' intermédiaire d' ouvertures8. Micromodule according to claim 7, in which the coil is connected to the chip by means of openings.
(8, 36, 37, 38, 46, 47, 48, 49) métallisées traversant la couche isolante pour atteindre des plages (4) de connexion électrique de la puce.(8, 36, 37, 38, 46, 47, 48, 49) metallized passing through the insulating layer to reach areas (4) of electrical connection of the chip.
9. Micromodule (30) selon l'une des revendications 7 et 8, dans lequel :9. Micromodule (30) according to one of claims 7 and 8, in which:
- la puce est recouverte par au moins deux couches isolantes (33, 34, 41, 42) ,- the chip is covered by at least two insulating layers (33, 34, 41, 42),
- l'une des deux couches isolantes (34, 42) sert de support à l'enroulement formant bobine, et l'autre couche isolante (33, 41) sert de support à un conducteur (32, 44, 73) reliant une extrémité de la bobine à une plage (4) de connexion de la puce.- one of the two insulating layers (34, 42) is used to support the coil winding, and the other insulating layer (33, 41) is used to support a conductor (32, 44, 73) connecting one end from the coil to a connection area (4) of the chip.
10. Micromodule (40) selon l'une des revendications 7 à 9, dans lequel la puce est recouverte par au moins deux couches isolantes (41, 42) et la bobine (43) comprend au moins deux enroulements plats (44, 45) agencés respectivement sur chacune des couches isolantes.10. Micromodule (40) according to one of claims 7 to 9, in which the chip is covered by at least two insulating layers (41, 42) and the coil (43) comprises at least two flat windings (44, 45) arranged respectively on each of the insulating layers.
11. Micromodule selon l'une des revendications 7 à 10, dans lequel la plaquette support (2) est en silicium et la couche isolante (7) comprend une couche de polyimide (5) et une couche d'oxyde de silicium (6} . 11. Micromodule according to one of claims 7 to 10, in which the support plate (2) is made of silicon and the insulating layer (7) comprises a layer of polyimide (5) and a layer of silicon oxide (6} .
12. Micromodule hybride (60) comprenant une plaquette support (61) comportant sur sa face avant (60-2) des plages de contact (C1-C8) , caractérisé en ce que la plaquette support (61) comporte sur sa face arrière (60-1) un micromodule (50) selon l'une des revendications 7 à 11, le micromodule (50) comprenant une puce de circuit intégré (52) à deux modes de fonctionnement, avec ou sans contact, et une couche isolante (33) comportant des ouvertures (55) pour connecter la puce (52) aux plages de contact (C1-C8) . 12. Hybrid micromodule (60) comprising a support plate (61) comprising on its front face (60-2) contact pads (C1-C8), characterized in that the support plate (61) comprises on its rear face ( 60-1) a micromodule (50) according to one of claims 7 to 11, the micromodule (50) comprising an integrated circuit chip (52) with two operating modes, with or without contact, and an insulating layer (33 ) comprising openings (55) for connecting the chip (52) to the contact pads (C1-C8).
EP99925077A 1998-06-29 1999-06-14 Integrated electronic micromodule and method for making same Withdrawn EP1097479A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR9808426A FR2780551B1 (en) 1998-06-29 1998-06-29 INTEGRATED ELECTRONIC MICROMODULE AND METHOD FOR MANUFACTURING SUCH A MICROMODULE
FR9808426 1998-06-29
PCT/FR1999/001405 WO2000001013A1 (en) 1998-06-29 1999-06-14 Integrated electronic micromodule and method for making same

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US (1) US6319827B1 (en)
EP (1) EP1097479A1 (en)
JP (1) JP2002519866A (en)
CN (1) CN100342536C (en)
AU (1) AU4268799A (en)
FR (1) FR2780551B1 (en)
WO (1) WO2000001013A1 (en)

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JP2002519866A (en) 2002-07-02
CN1315056A (en) 2001-09-26
WO2000001013A1 (en) 2000-01-06
CN100342536C (en) 2007-10-10
FR2780551A1 (en) 1999-12-31
FR2780551B1 (en) 2001-09-07
US6319827B1 (en) 2001-11-20

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