JPH0714876A - Integrated circuit device and manufacture thereof - Google Patents
Integrated circuit device and manufacture thereofInfo
- Publication number
- JPH0714876A JPH0714876A JP5145930A JP14593093A JPH0714876A JP H0714876 A JPH0714876 A JP H0714876A JP 5145930 A JP5145930 A JP 5145930A JP 14593093 A JP14593093 A JP 14593093A JP H0714876 A JPH0714876 A JP H0714876A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- thin film
- integrated circuit
- circuit device
- main surface
- Prior art date
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- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、集積回路装置及びその
製造方法に関し、特に、通信機器などに用いられる高周
波用ＩＣやＬＳＩなどの集積回路装置及びその製造方法
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device and a manufacturing method thereof, and more particularly to an integrated circuit device such as a high frequency IC and LSI used in communication equipment and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】従来の集積回路装置を図４に基づいて説
明する。2. Description of the Related Art A conventional integrated circuit device will be described with reference to FIG.
【０００３】図４は、特公平３−７３１４５号公報に示
される３次元構造を有する高周波用アナログＩＣの断面
構造を示している。FIG. 4 shows a cross sectional structure of a high frequency analog IC having a three-dimensional structure disclosed in Japanese Patent Publication No. 3-73145.
【０００４】従来の３次元構造を有する高周波用アナロ
グＩＣは、図４に示すように、半絶縁性ＧａＡｓ基板か
らなる支持側基板１１とシリコン基板からなる貼付け側
基板１２とから構成される２重構造を有している。支持
側基板１１と貼付け側基板１２とは、貼付け側基板１２
に設けられた連結孔１３に例えばＡｕＳｎなどからなる
導電性の連結粒１４を挿入して互いに固着することによ
り１つの集積回路装置を形成する。As shown in FIG. 4, a conventional high-frequency analog IC having a three-dimensional structure is a double layer composed of a support side substrate 11 made of a semi-insulating GaAs substrate and a sticking side substrate 12 made of a silicon substrate. It has a structure. The supporting side substrate 11 and the attaching side substrate 12 are the attaching side substrate 12
One integrated circuit device is formed by inserting the conductive connecting particles 14 made of AuSn or the like into the connecting holes 13 provided in and fixing them to each other.
【０００５】支持側基板１１にはイオン注入法によりト
ランジスタ１６が形成されており、また、貼付け側基板
１２には例えば二酸化ケイ素等の絶縁膜１５を介して金
属−絶縁膜−金属型（Metal-Insulator-Metal 型）のコ
ンデンサ１７やインダクタ１８などの受動素子が形成さ
れている。A transistor 16 is formed on the supporting side substrate 11 by an ion implantation method, and a metal-insulating film-metal type (Metal-type) is formed on the attaching side substrate 12 via an insulating film 15 such as silicon dioxide. Passive elements such as an Insulator-Metal type capacitor 17 and an inductor 18 are formed.
【０００６】[0006]
【発明が解決しようとする課題】ところで、貼付け側基
板１２を何枚も貼り合わせる場合、貼り合わせた枚数分
だけ集積回路装置のトータルの厚さが増す。例えば厚さ
１００μｍの貼付け側基板１２を１０枚貼り合わせると
すると、集積回路装置の厚さは、厚さ３００μｍの支持
側基板と合わせておよそ１．３ｍｍになる。このため、
集積可能な貼付け側基板１２の枚数は高々十数枚程度に
ならざるを得ないという問題がある。By the way, when a number of the bonding-side substrates 12 are bonded together, the total thickness of the integrated circuit device increases by the number of bonded substrates. For example, if 10 pieces of the sticking side substrate 12 having a thickness of 100 μm are stuck together, the thickness of the integrated circuit device becomes about 1.3 mm including the supporting side board having a thickness of 300 μm. For this reason,
There is a problem that the number of sticking-side substrates 12 that can be stacked is at most about ten.
【０００７】また、仮に、そのような枚数の貼付け側基
板１２を貼り合わしたとしても、そのような厚さの集積
回路装置を削り出すダイシングの時間は、１枚の支持側
基板のダイシング時間に比べて数倍よけいにかかるとい
う問題がある。Even if such a number of the bonding side substrates 12 are bonded, the dicing time for cutting out the integrated circuit device having such a thickness is equal to the dicing time for one supporting side substrate. There is a problem that it takes several times as much as the comparison.
【０００８】図５は、貼付け側基板１２の拡大図であ
り、シリコン基板１２ａの上に絶縁膜１５が堆積され、
絶縁膜１５の上に配線１９やコンデンサ１７が形成され
ている。このような構造では絶縁膜１５におけるコンデ
ンサ１７と配線１９との間には近似的にＣｉの容量が寄
生し、また、基板１２におけるコンデンサ１７と配線１
９との間にはＣｓｕｂの容量が寄生する。絶縁膜１５の
誘電率に比べてシリコン基板１２ａの誘電率は３倍高い
ので、シリコン基板１２ａによる寄生効果は大きく無視
することはできない。このような寄生容量は、シリコン
基板１２ａ上に配置された隣接する素子間のいたるとこ
ろで発生すると共に寄生効果は受動素子のレイアウトに
より異なるため、設計毎に寄生効果を計算する必要が生
じるという問題がある。FIG. 5 is an enlarged view of the attachment-side substrate 12, in which an insulating film 15 is deposited on the silicon substrate 12a,
The wiring 19 and the capacitor 17 are formed on the insulating film 15. In such a structure, a capacitance of Ci is approximately parasitic between the capacitor 17 in the insulating film 15 and the wiring 19, and the capacitor 17 and the wiring 1 in the substrate 12 are also parasitic.
A capacitance of Csub is parasitic between 9 and 9. Since the dielectric constant of the silicon substrate 12a is three times higher than that of the insulating film 15, the parasitic effect of the silicon substrate 12a cannot be ignored. Such a parasitic capacitance is generated everywhere between the adjacent elements arranged on the silicon substrate 12a, and the parasitic effect differs depending on the layout of the passive elements. Therefore, it is necessary to calculate the parasitic effect for each design. is there.
【０００９】上記に鑑み、本発明は、支持側基板に少な
くとも１枚の貼付け側基板が貼り合わされてなる集積回
路装置の厚さを薄くし、該集積回路装置を削り出すダイ
シング時間を短縮し、且つ貼付け側基板におけるシリコ
ン基板による寄生効果を低減することを目的とする。In view of the above, the present invention reduces the thickness of an integrated circuit device in which at least one attachment side substrate is attached to a support side substrate, and shortens the dicing time for cutting out the integrated circuit device, Moreover, it is intended to reduce the parasitic effect of the silicon substrate on the attachment side substrate.
【００１０】[0010]
【課題を解決するための手段】上記の目的を達成するた
め、請求項１の発明は、貼付け側基板を構成する支持基
板として絶縁性薄膜を用いるものであって、具体的に
は、半導体集積回路装置を、一主面に素子が形成された
支持側基板と一主面に素子が形成された絶縁性薄膜とか
らなり、上記支持側基板と上記絶縁性薄膜とは、それぞ
れの一主面同士が互いに対向し且つ互いに電気的に接続
された状態で接着されているという構成とするものであ
る。In order to achieve the above-mentioned object, the invention of claim 1 uses an insulating thin film as a supporting substrate which constitutes a pasting side substrate. Specifically, it is a semiconductor integrated circuit. The circuit device comprises a support side substrate having an element formed on one main surface and an insulating thin film having an element formed on the one main surface, wherein the support side substrate and the insulating thin film have respective main surfaces. It is configured such that they are bonded to each other while facing each other and electrically connected to each other.
【００１１】請求項２の発明は、請求項１の発明に係る
半導体集積回路装置の製造方法であって、支持側基板の
一主面に素子を形成すると共に、貼付け用基板の一主面
に絶縁性薄膜を形成した後に該絶縁性薄膜の一主面に素
子を形成する工程と、上記支持側基板と上記貼付け用基
板とを上記支持側基板の一主面と上記絶縁性薄膜の一主
面とが互いに対向し且つ互いに電気的に接続されるよう
に接着する工程と、上記貼付け用基板をエッチングによ
り除去する工程とを含む構成である。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor integrated circuit device according to the first aspect of the present invention, in which elements are formed on one main surface of a supporting substrate and one main surface of a sticking substrate is formed. A step of forming an element on one main surface of the insulating thin film after forming the insulating thin film, and the supporting-side substrate and the sticking substrate on the one main surface of the supporting-side substrate and one main surface of the insulating thin film. The structure includes a step of adhering the surfaces so as to face each other and to be electrically connected to each other, and a step of removing the sticking substrate by etching.
【００１２】[0012]
【作用】請求項１の構成により、一主面に素子が形成さ
れた支持側基板と一主面に素子が形成された絶縁性薄膜
とが、一主面同士が対向し且つ電気的に接続された状態
で接着されており、貼付け側基板の支持基板としては絶
縁性薄膜が用いられているので、貼付け側基板の支持基
板の厚さが極めて薄いものとなる。According to the structure of claim 1, the support-side substrate having the element formed on the one main surface and the insulating thin film having the element formed on the one main surface face each other and are electrically connected. Since the insulating thin film is used as the support substrate of the attachment side substrate, the support substrate of the attachment side substrate is extremely thin.
【００１３】請求項２の構成により、支持側基板と貼付
け用基板とを支持側基板の一主面と絶縁性薄膜の一主面
とが対向し且つ電気的に接続されるように接着した後、
貼付け用基板をエッチングにより除去するので、貼付け
側基板の支持基板としては絶縁性薄膜が用いられること
になり、貼付け側基板の支持基板の厚さは極めて薄いも
のとなる。According to the structure of claim 2, after the supporting side substrate and the sticking substrate are adhered so that one main surface of the supporting side substrate and one main surface of the insulating thin film face each other and are electrically connected. ,
Since the sticking substrate is removed by etching, an insulating thin film is used as the support substrate of the sticking side substrate, and the thickness of the sticking side substrate supporting substrate becomes extremely thin.
【００１４】また、貼付け用基板の一主面に絶縁性薄膜
が形成されているため、貼付け用基板をエッチングによ
り除去する際に、絶縁性薄膜が停止層の役割を果たすの
で、絶縁性薄膜の一主面に形成された素子を損なうこと
なく貼付け用基板をエッチングできる。Further, since the insulating thin film is formed on one main surface of the sticking substrate, the insulating thin film serves as a stop layer when the sticking substrate is removed by etching. The sticking substrate can be etched without damaging the element formed on the one main surface.
【００１５】[0015]
【実施例】以下、本発明の実施例について説明する。EXAMPLES Examples of the present invention will be described below.
【００１６】図１は、本発明の一実施例に係る集積回路
装置の断面斜視図であって、半導体基板上に形成された
集積回路を示している。FIG. 1 is a sectional perspective view of an integrated circuit device according to an embodiment of the present invention, showing an integrated circuit formed on a semiconductor substrate.
【００１７】集積回路装置は、例えば半絶縁性ＧａＡｓ
基板１の一主面にトランジスタ２などの素子が形成され
てなる支持側基板Ａと、例えば二酸化ケイ素薄膜３の一
主面にコンデンサ４やインダクタ５などの受動素子、第
１層配線６Ａ及び第２層配線６Ｂが形成されてなる貼付
け側基板Ｂとから構成されている。支持側基板Ａと貼付
け側基板Ｂとは、半絶縁性ＧａＡｓ基板１の一主面と二
酸化ケイ素薄膜３の一主面とが互いに対向した状態で電
気的な接続を兼ねたバンプ７により接着されており、全
体として１つの集積回路装置を構成している。The integrated circuit device is, for example, a semi-insulating GaAs.
A support-side substrate A having elements such as transistors 2 formed on one main surface of the substrate 1, passive elements such as capacitors 4 and inductors 5, first layer wiring 6A and It is composed of a sticking side substrate B on which a two-layer wiring 6B is formed. The supporting side substrate A and the sticking side substrate B are adhered to each other by bumps 7 which also serve as electrical connections in a state where one main surface of the semi-insulating GaAs substrate 1 and one main surface of the silicon dioxide thin film 3 face each other. And constitutes one integrated circuit device as a whole.
【００１８】以下、上記集積回路装置の製造方法につい
て説明する。The method of manufacturing the integrated circuit device will be described below.
【００１９】図２（ａ）〜（ｃ）は、上記の集積回路装
置の貼り合わせ前の貼付け側基板Ｂの製造工程を示す拡
大断面図である。2 (a) to 2 (c) are enlarged cross-sectional views showing the manufacturing process of the bonding side substrate B before bonding the above integrated circuit device.
【００２０】まず、図２（ａ）に示すように、厚さ３０
０μｍの貼付け用基板としてのシリコン基板８の上に厚
さ５００ｎｍの二酸化ケイ素薄膜３を例えば常圧ＣＶＤ
法により堆積した後、図２（ｂ）に示すように、二酸化
ケイ素薄膜３の上に例えば厚さ５００ｎｍのＡｕ／Ｔｉ
の金属膜からなる第１層配線６Ａを形成する。その後、
図２（ｃ）に示すように、誘電体を兼ねる層間絶縁膜と
して窒化ケイ素薄膜９を４００ｎｍの厚さで堆積した
後、窒化ケイ素薄膜９の上に厚さ８００ｎｍの第２層配
線６Ｂを形成し、最後に、ＡｕＳｎメッキにより高さ１
μｍのバンプ７を形成する。First, as shown in FIG. 2A, the thickness 30
A silicon dioxide thin film 3 having a thickness of 500 nm is formed on a silicon substrate 8 as a bonding substrate having a thickness of 0 μm by, for example, atmospheric pressure CVD.
After being deposited by the method, as shown in FIG. 2B, for example, Au / Ti having a thickness of 500 nm is formed on the silicon dioxide thin film 3.
The first-layer wiring 6A made of the metal film is formed. afterwards,
As shown in FIG. 2C, after depositing a silicon nitride thin film 9 with a thickness of 400 nm as an interlayer insulating film that also serves as a dielectric, a second layer wiring 6B with a thickness of 800 nm is formed on the silicon nitride thin film 9. Finally, AuSn plating height 1
A bump 7 of μm is formed.
【００２１】次に、図３（ａ）に示すように、トランジ
スタ２などの素子が形成された半絶縁性ＧａＡｓ基板１
と図２（ｃ）に示すシリコン基板８とを両面整合技術に
より貼り合わせた後、図３（ｂ）に示すように、例えば
ＳＦ6 ガスを用いたドライエッチング法によりシリコン
基板８を裏面側から除去する。この際、二酸化ケイ素薄
膜３に対するシリコン基板８の選択性により、二酸化ケ
イ素薄膜３及び該二酸化ケイ素薄膜３の表面に形成され
たコンデンサ４やインダクタ５は半絶縁性ＧａＡｓ基板
１に貼り合わせた状態で残される。Next, as shown in FIG. 3A, a semi-insulating GaAs substrate 1 on which elements such as a transistor 2 are formed.
2C and the silicon substrate 8 shown in FIG. 2C by the double-sided alignment technique, and then, as shown in FIG. 3B, the silicon substrate 8 from the back surface side by a dry etching method using SF 6 gas, for example. Remove. At this time, due to the selectivity of the silicon substrate 8 with respect to the silicon dioxide thin film 3, the silicon dioxide thin film 3 and the capacitor 4 and the inductor 5 formed on the surface of the silicon dioxide thin film 3 are bonded to the semi-insulating GaAs substrate 1. Left behind.
【００２２】本実施例によると、貼付け側基板Ｂの厚さ
はおよそ２．２μｍであり、従来の貼付け側基板の厚さ
の１／４０程度に薄くすることができた。また、貼付け
側基板における寄生容量は従来のシリコン基板を用いた
場合に比べて１／３程度に抑制することができた。According to the present embodiment, the thickness of the sticking side substrate B is about 2.2 μm, which can be reduced to about 1/40 of the thickness of the conventional sticking side substrate. Further, the parasitic capacitance of the attachment-side substrate could be suppressed to about 1/3 of that in the case of using the conventional silicon substrate.
【００２３】尚、本実施例は、支持側基板Ａと貼付け側
基板Ｂとからなる２枚の基板の貼り合わせの場合である
が、貼り合わせる基板の枚数が３枚以上でも同様であ
る。In this embodiment, the two substrates consisting of the supporting side substrate A and the pasting side substrate B are bonded together, but the same applies when the number of substrates to be bonded is three or more.
【００２４】また、本実施例においては、支持側基板Ａ
の支持基板として半絶縁性ＧａＡｓ基板１を用いている
が、これに代えてシリコン基板を用いても同一の効果が
得られるのは言うまでもないし、さらに、貼付け側基板
Ｂにおいては、絶縁性薄膜として二酸化ケイ素薄膜３を
用いているが、これに代えて、窒化ケイ素薄膜の単独又
は二酸化ケイ素薄膜と窒化ケイ素薄膜の積層膜でも差支
えがない。Further, in this embodiment, the supporting side substrate A
Although the semi-insulating GaAs substrate 1 is used as the supporting substrate of the above, it is needless to say that the same effect can be obtained even if a silicon substrate is used instead of the semi-insulating GaAs substrate 1. Although the silicon dioxide thin film 3 is used, a silicon nitride thin film alone or a laminated film of a silicon dioxide thin film and a silicon nitride thin film may be used instead.
【００２５】[0025]
【発明の効果】以上説明したように、請求項１の発明に
係る集積回路装置によると、一主面に素子が形成された
支持側基板と一主面に素子が形成された絶縁性薄膜と
が、一主面同士が対向し且つ電気的に接続された状態で
接着されているため、貼付け側基板の支持基板としては
厚さが極めて薄い絶縁性薄膜が用いられているので、集
積回路装置の厚さが薄くなる。As described above, according to the integrated circuit device of the first aspect of the present invention, the supporting side substrate having the element formed on one main surface and the insulating thin film having the element formed on the one main surface are provided. However, since the main surfaces are adhered in a state where they are opposed to each other and are electrically connected to each other, an extremely thin insulating thin film is used as the supporting substrate of the attachment side substrate, and therefore, the integrated circuit device Becomes thinner.
【００２６】また、集積回路装置の削り出し工程におい
て、絶縁性薄膜の除去はドライエッチングによりできる
ため、支持側基板のみをダイシングするだけでよいの
で、集積回路装置を削り出すダイシング時間が大きく短
縮される。Further, in the step of shaving the integrated circuit device, since the insulating thin film can be removed by dry etching, only the supporting side substrate needs to be diced, so that the dicing time for shaving the integrated circuit device is greatly shortened. It
【００２７】さらに、貼付け側基板において支持基板と
してシリコン基板が用いられていないために寄生効果が
大きく低減する。Further, since the silicon substrate is not used as the supporting substrate on the attachment side substrate, the parasitic effect is greatly reduced.
【００２８】請求項２の発明に係る集積回路装置による
と、支持側基板と貼付け用基板とを支持側基板の一主面
と絶縁性薄膜の一主面とが対向し且つ電気的に接続され
るように接着した後、貼付け用基板をエッチングにより
除去する工程において、貼付け用基板をエッチングによ
り除去する際に絶縁性薄膜が停止層の役割を果たすの
で、絶縁性薄膜の一主面に形成された素子を損なうこと
なく該貼付け用基板をエッチングすることができるの
で、請求項１の発明に係る集積回路装置を簡易且つ確実
に製造することができる。According to the integrated circuit device of the second aspect of the present invention, the supporting side substrate and the sticking substrate are electrically connected so that one main surface of the supporting side substrate and one main surface of the insulating thin film face each other. After adhering as in the above, in the step of removing the sticking substrate by etching, the insulating thin film acts as a stop layer when the sticking substrate is removed by etching, so it is formed on one main surface of the insulating thin film. Since the bonding substrate can be etched without damaging the element, the integrated circuit device according to the first aspect of the invention can be easily and reliably manufactured.
【図１】本発明の一実施例に係る集積回路装置の構造を
示す断面図である。FIG. 1 is a sectional view showing a structure of an integrated circuit device according to an embodiment of the present invention.
【図２】上記集積回路装置の製造方法の各製造工程を示
す断面図である。FIG. 2 is a cross-sectional view showing each manufacturing step of the method for manufacturing the integrated circuit device.
【図３】上記集積回路装置の製造方法の各製造工程を示
す断面図である。FIG. 3 is a cross-sectional view showing each manufacturing step of the method for manufacturing the integrated circuit device.
【図４】従来の集積回路装置の構造を示す断面図であ
る。FIG. 4 is a sectional view showing the structure of a conventional integrated circuit device.
【図５】従来の集積回路装置における貼付け側基板の拡
大断面図である。FIG. 5 is an enlarged cross-sectional view of a pasting side substrate in a conventional integrated circuit device.
Ａ 支持側基板 Ｂ 貼合せ側基板 １ 半絶縁性ＧａＡｓ基板 ２ トランジスタ（素子） ３ 二酸化ケイ素薄膜（絶縁性薄膜） ４ コンデンサ（素子） ５ インダクタ（素子） ６Ａ 第１層配線 ６Ａ 第２層配線 ７ バンプ ８ シリコン基板（貼付け用基板） ９ 窒化ケイ素薄膜 １１ 支持側基板 １２ 貼付け側基板 １３ 連結孔 １４ 連結粒 １５ 絶縁膜 １６ トランジスタ １７ コンデンサ １８ インダクタ １９ 配線 A support side substrate B bonding side substrate 1 semi-insulating GaAs substrate 2 transistor (element) 3 silicon dioxide thin film (insulating thin film) 4 capacitor (element) 5 inductor (element) 6A first layer wiring 6A second layer wiring 7 Bump 8 Silicon substrate (sticking substrate) 9 Silicon nitride thin film 11 Supporting side substrate 12 Sticking side substrate 13 Connecting hole 14 Connecting grain 15 Insulating film 16 Transistor 17 Capacitor 18 Inductor 19 Wiring
Claims (2)
一主面に素子が形成された絶縁性薄膜とからなり、上記
支持側基板と上記絶縁性薄膜とは、それぞれの一主面同
士が互いに対向し且つ互いに電気的に接続された状態で
接着されていることを特徴とする集積回路装置。1. A support-side substrate having an element formed on one main surface and an insulating thin film having an element formed on one main surface, wherein the support-side substrate and the insulating thin film each have a main surface. An integrated circuit device characterized in that the surfaces are opposed to each other and are electrically connected to each other.
共に、貼付け用基板の一主面に絶縁性薄膜を形成した後
に該絶縁性薄膜の一主面に素子を形成する工程と、上記
支持側基板と上記貼付け用基板とを上記支持側基板の一
主面と上記絶縁性薄膜の一主面とが互いに対向し且つ互
いに電気的に接続されるように接着する工程と、上記貼
付け用基板をエッチングにより除去する工程とを含むこ
とを特徴とする集積回路装置の製造方法。2. A step of forming an element on one main surface of a supporting substrate, forming an insulating thin film on one main surface of a bonding substrate, and then forming an element on one main surface of the insulating thin film, A step of adhering the support-side substrate and the sticking substrate so that one main surface of the support-side substrate and one main surface of the insulating thin film face each other and are electrically connected to each other; And a step of removing the substrate for etching by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5145930A JPH0714876A (en) | 1993-06-17 | 1993-06-17 | Integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5145930A JPH0714876A (en) | 1993-06-17 | 1993-06-17 | Integrated circuit device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0714876A true JPH0714876A (en) | 1995-01-17 |
Family
ID=15396371
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5145930A Withdrawn JPH0714876A (en) | 1993-06-17 | 1993-06-17 | Integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0714876A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL1003207C2 (en) * | 1995-05-30 | 1997-06-24 | Motorola Inc | A method of manufacturing a flip chip semiconductor device with an inductor. |
| FR2780551A1 (en) * | 1998-06-29 | 1999-12-31 | Inside Technologies | Simultaneous production of several electronic micro modules or passive transponders useful for portable electronic equipment, labels, tokens, etc. |
| WO2002001638A3 (en) * | 2000-06-30 | 2004-05-13 | Jds Uniphase Corp | Microelectronic packages including reactive components, and methods of fabricating the same |
| JP2005522861A (en) * | 2002-04-11 | 2005-07-28 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Manufacturing method of electronic device |
| JP2008053712A (en) * | 2006-08-23 | 2008-03-06 | Dongbu Hitek Co Ltd | Semiconductor element, and manufacturing method thereof |
| JP2008053711A (en) * | 2006-08-23 | 2008-03-06 | Dongbu Hitek Co Ltd | Semiconductor element, and manufacturing method thereof |
| JP2008219052A (en) * | 2008-06-13 | 2008-09-18 | Fujitsu Ltd | Method of manufacturing semiconductor device |
-
1993
- 1993-06-17 JP JP5145930A patent/JPH0714876A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL1003207C2 (en) * | 1995-05-30 | 1997-06-24 | Motorola Inc | A method of manufacturing a flip chip semiconductor device with an inductor. |
| FR2780551A1 (en) * | 1998-06-29 | 1999-12-31 | Inside Technologies | Simultaneous production of several electronic micro modules or passive transponders useful for portable electronic equipment, labels, tokens, etc. |
| WO2000001013A1 (en) * | 1998-06-29 | 2000-01-06 | Inside Technologies | Integrated electronic micromodule and method for making same |
| US6319827B1 (en) | 1998-06-29 | 2001-11-20 | Inside Technologies | Integrated electronic micromodule and method for making same |
| WO2002001638A3 (en) * | 2000-06-30 | 2004-05-13 | Jds Uniphase Corp | Microelectronic packages including reactive components, and methods of fabricating the same |
| JP2005522861A (en) * | 2002-04-11 | 2005-07-28 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Manufacturing method of electronic device |
| JP2008053712A (en) * | 2006-08-23 | 2008-03-06 | Dongbu Hitek Co Ltd | Semiconductor element, and manufacturing method thereof |
| JP2008053711A (en) * | 2006-08-23 | 2008-03-06 | Dongbu Hitek Co Ltd | Semiconductor element, and manufacturing method thereof |
| JP2008219052A (en) * | 2008-06-13 | 2008-09-18 | Fujitsu Ltd | Method of manufacturing semiconductor device |
| JP4641551B2 (en) * | 2008-06-13 | 2011-03-02 | 富士通株式会社 | Manufacturing method of semiconductor device |
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