US9559703B2 - System ready in a clock distribution chip - Google Patents

System ready in a clock distribution chip Download PDF

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US9559703B2
US9559703B2 US14/613,123 US201514613123A US9559703B2 US 9559703 B2 US9559703 B2 US 9559703B2 US 201514613123 A US201514613123 A US 201514613123A US 9559703 B2 US9559703 B2 US 9559703B2
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phase
clock signals
signal
output clock
ready
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US20150222274A1 (en
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Tunc Mahmut Cenger
Gordon John Allan
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Hittite Microwave LLC
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/64—Hybrid switching systems
    • H04L12/6418—Hybrid transport

Definitions

  • the disclosed technology relates to electronic systems, and more particularly, to electronic systems that generate clock signals.
  • Clock generation circuits can be implemented in communication systems to provide multiple clock signals for an electronic system.
  • One or more phase locked loops are typically used to recover a noisy reference clock signal, also referred to as a reference signal, and to create stable, low jitter signals.
  • PLLs can be used in, for example, frequency synthesizers, telecommunications systems, chip-to-chip communication systems, the like, or any combination thereof.
  • Clock generation circuits frequently include a PLL to lock an output clock signal generated by the PLL's voltage controlled oscillator to the phase of an incoming reference clock signal.
  • a high precision tunable voltage controlled oscillator can be phase-locked to a noisy reference clock signal, and the PLL can operate to suppress phase noise and to attenuate jitter.
  • Clock generation circuits can provide multiple low jitter clock signals derived from a selection of noisy reference clocks in an integrated circuit.
  • the one or more state machines can comprise a separate state machine corresponding to each output clock signal.
  • the system ready circuit can be configured to toggle the system ready signal in response to each of the separate state machines being in a done state. Alternatively or additionally, the system ready circuit can be configured to toggle the system ready signal in response to each of the separate state machines ceasing to request a system clock signal having a lower frequency than the reference clock signal.
  • the divider and phase control circuit can comprise a plurality of programmable dividers and a plurality of phase control circuits.
  • the plurality of programmable dividers can each be configured to frequency divide the reference signal.
  • the plurality of phase control circuits can each be configured to receive an output from a respective one of the programmable dividers and adjust a phase of the output from the respective divider.
  • the output clock signals can each be frequency divided relative to the reference clock signal by an integer divisor.
  • the system ready circuit and the divider and phase control circuit can be embodied within a single chip.
  • the apparatus can be configured to provide the system ready signal to an output contact of the single chip.
  • the apparatus can further comprise a phase-locked loop.
  • the phase-locked loop can provide the reference clock signal to the divider and phase control circuit.
  • the apparatus can comprise a second divider and phase control circuit and a second system ready circuit.
  • the second divider and phase control circuit can be configured to receive a first clock signal of the output clock signals from the phase control circuit and to provide second output clock signals.
  • the second output clock signals are frequency divided relative to the first output clock signal of the output clock signals, and each has a set phase relative to another of the second output clock signals when ready.
  • the second system ready circuit can be configured to toggle a second system ready signal in response to an indication that each of the second output clock signals is ready.
  • a clock distribution chip comprising a phase-locked loop, a divider and phase control circuit, and a controller.
  • the phase-locked loop is configured to generate a reference clock signal.
  • the divider and phase control circuit is configured to receive the reference clock signal from the phase-locked loop and to provide output clock signals that are frequency divided relative to the reference clock signal. Each of the output clock signals has a set phase when ready.
  • the controller is configured to provide, external to the clock distribution chip, a system ready signal indicative of whether each of the output clock signals is ready.
  • the controller can be configured to receive a lock detect signal from the phase locked loop and to provide a control signal to the divider and phase control circuit responsive to the lock detect signal indicating that the phase locked loop is locked.
  • the clock distribution chip can further comprise an other phase locked loop configured to provide an input to the phase locked loop.
  • Another aspect of this disclosure is an electronically implemented method of detecting that output clock signals are ready.
  • the method comprises receiving a request to provide output clock signals having desired frequencies and known phases.
  • the method also comprises controlling a divider and phase control circuit such that the divider and phase control circuit generates the output clock signals having the desired frequencies and the known phases.
  • the divider and phase control circuit generates the output clock signals using a reference signal.
  • the method comprises monitoring whether the output clock signals are ready and toggling a system ready signal.
  • the system ready signal is toggled in response to determining that each of the output clock signals are ready.
  • the method can further comprise detecting that a phase locked loop is locked, wherein the phase locked loop provides the reference signal, and wherein controlling is initiated in response to detecting that the phase locked loop is locked.
  • the method can further comprise detecting that an other phase locked loop is locked, wherein the other phase locked loop provides an input to the phase locked loop, and wherein controlling is initiated in response to detecting that the phase locked loop and the other phase locked loop are both locked.
  • Monitoring whether the output clock signals are ready can comprise detecting whether one or more state machines of the divider and phase control circuit are in a done state and/or detecting whether one or more state machines have ceased to request a system clock signal, the system clock signal having a lower frequency than the reference signal.
  • FIG. 1 is a schematic diagram of a communication system including a clock generation circuit according to one embodiment.
  • FIG. 2 is a schematic diagram of a clock generation circuit having a controller and a divider and phase control circuit according to one embodiment.
  • FIG. 3 is a schematic diagram showing a controller and a divider and phase control circuit from a clock generation circuit according to one embodiment.
  • FIG. 4 is a schematic diagram showing a cascaded implementation of multiple divider and phase control circuits of a clock generation circuit according to an embodiment.
  • FIG. 6 is a flow diagram of a process of determining that output clock signals are ready according to one embodiment.
  • the synchronous reference clock signal is typically recovered locally as a local reference clock signal having relatively lower noise and jitter.
  • the local reference clock signal in turn, can provide a relatively stable clean source which is phase locked, by a PLL, to the synchronous reference clock signal. This can provide a reference clock signal at a desired phase and frequency but with better short term jitter and noise.
  • Sub-systems within the communication system often operate at higher frequencies than the local reference clock signal, but typically operate at integer multiples of the reference clock signal and at known phases.
  • the known phases can be relative to the reference clock signal and/or relative to other local reference clock signals.
  • the known phases can be deterministic.
  • a high frequency voltage control oscillator can be used to generate the other higher frequency clock signals for the sub-systems.
  • a reference clock signal generated from the high frequency voltage controlled oscillator can in turn be divided down by frequency divider circuits to provide a plurality of output clock signals having frequencies typically at integer sub-multiples of the reference clock signal clock frequency.
  • the phase of the plurality of output clock signals preferably can be controlled and set with respect to a system reference signal having lower frequency than each of the plurality of output clock signals.
  • the system reference signal can be provided within the communication system.
  • the system reference signal which can also be referred to as a golden reference signal, is typically an integer sub-multiple of the reference clock signal clock frequency.
  • the reference clock signal can be provided with a frequency of approximately 122.55 MHz, whereas the system reference signal can be provided with a frequency of approximately 8 kHz.
  • the plurality of output clock signals can be controlled by a system controller.
  • the system controller can be part of a monolithic integrated circuit chip that includes a divider and phase control circuit that provides the output clock signals.
  • the monolithic integrated circuit can also include one or more phase locked loops.
  • the divider and phase control circuit providing the plurality of output clock signals can be configured by the controller to control both phase and frequency of the output clock signals.
  • the divider and phase control circuity can provide output clock signals have programmable frequencies and deterministic phases.
  • the controller and/or the divider and phase control circuit can include finite state machines (FSMs) to set phase and frequency of the plurality of output clock signals, one at a time and/or in groups.
  • FSMs finite state machines
  • the controller initiates instructions to configure the output frequencies and phases of the output clock signals, the changes are not implemented instantaneously. Rather, a period of time elapses before the output clock signals have the desired frequencies and phases.
  • the time period can include time for internal data transfers, finite state machine cycles, calibrations, the like, or any combination thereof. The time period can be treated as the transient time prior to reaching a steady state condition.
  • An external system receiving the output clock signals is typically unaware when output clock signals from a clock distribution circuit are ready.
  • the period of time from requesting output clock signals having desired frequencies and a known phase relationship until the output clock signals are ready can be application specific and/or can be unknown.
  • the output clock signals can have programmable frequencies and it can take different amounts of time for the output clocks having different frequency and phase combinations to settle at the desired frequencies and phases. Accordingly, it can be difficult to know how much time is required to configure, settle and propagate all signals related to completing the task of setting phase and frequency of the plurality of output clock signals. Problems can arise within the system if one or more of the sub-systems are enabled during the period of time to implement the changes.
  • the system ready signal can provide an indication of whether the output clock signals from a clock distribution circuit have a desired frequency and known phase relationship.
  • Clock distribution circuits discussed herein can notify an external user, by way of a system ready signal, which can also be referred to as a system ready flag.
  • the system ready flag can be a real time hardware output to a logic pin or other output contact of the clock distribution chip, or it can be an internal flag, which is set in a register within the clock distribution system for observation or polling by a state machine and/or system controller.
  • the system ready flag can notify a user when the system is configured and the plurality of output clocks are ready or not ready for distribution.
  • the clock distribution circuit can also include features to distribute the plurality of output clock signals with well-defined and/or deterministic phase relationships.
  • FIG. 1 is a schematic diagram of a communication system 100 that includes a clock generation circuit according to one embodiment.
  • the communication system 100 includes a clock generation circuit 102 , a clock and data recovery (CDR) circuit 104 , a first input reference clock generator 106 , a second input reference clock generator 108 , a third input reference clock generator 110 , a high precision tunable oscillator or VCXO 112 , a serializer/deserializer (SerDes) circuit 114 , a field programmable gate array (FPGA)/digital signal processor (DSP) 116 , analog-to-digital converter (ADC) circuits 118 , digital-to-analog converter (DAC) circuits 120 , downstream dividers 122 , a first mixer 124 , and a second mixer 126 .
  • CDR clock and data recovery
  • the communication system 100 can be used in a variety of applications, including, for example, cellular infrastructure applications.
  • the communication system 100 can represent a portion of a base station.
  • the clock generation circuit 102 receives a plurality of input clock reference clock signals including a first input reference clock signal RCLK 0 , a second input reference clock signal RLCK 1 , and a third input reference clock signal RCLKN.
  • FIG. 1 illustrates the clock generation circuit 102 as receiving three reference clock signals, the clock generation circuit 102 can receive more or fewer input reference clock signals.
  • the clock generation circuit 102 receives N input reference clock signals, where N is an integer selected to be in the range from about 2 to about 4.
  • the reference clock signals are derived from the CDR circuit 104 .
  • the input reference clock signals can correspond to recovered clock signals from clock and data recovery operations of the CDR circuit 104 on a data stream (DATA).
  • DATA data stream
  • the reference clock signals include at least one input reference clock signal generated using a reference oscillator, such a free-running oscillator that operates open-loop.
  • the clock generation circuit 102 can generate output clock signals based on a selected or active reference clock signal chosen from the reference clock signals RCLK 0 -RCLKN.
  • the clock generation circuit 102 can use one active or primary reference signal, for example, the first reference clock signal RCLK 0 , which is used to generate the output clock signals.
  • the other reference clock signals RCLK 1 -RCLKN can serve as back-up clock reference signals should the first reference clock signal RCLK 0 become invalid or dropped.
  • the clock generation circuit includes a PLL system 143 , a divider and phase control circuit 145 , and a finite state machine controller 147 .
  • the clock generation circuit 102 can include more elements than illustrated and/or a subset of the illustrated elements.
  • the PLL system 143 can provide a reference clock signal to the divider and phase control circuit 145 .
  • the PLL 143 can include one or more PLLs. In one embodiment the PLL system 143 can include two PLLs.
  • the state machine controller 147 can communicate with the divider and phase control circuit 145 to provide inputs to request that output clock signals have desired frequencies.
  • the state machine controller 147 can determine when the output clock signals provided by the clock generation circuit 102 are ready and provide a system ready signal indicative of whether the output clock signals are ready.
  • the output clock signals can be ready when they are in a steady-state in which they have a desired frequency and known phase.
  • FIG. 2 is a schematic diagram of a clock generation circuit 102 having a control module 252 and a divider and phase control circuit 254 according to one embodiment.
  • the clock generation circuit 102 of FIG. 2 further includes a first PLL 204 a and a second PLL 204 b .
  • the clock generation circuit 102 of FIG. 2 is an example of the clock generation circuit 102 of FIG. 1 .
  • the first PLL 204 a and the second PLL 204 b can be included in, the control module 252 can implement the state machine controller 147 of FIG. 1 , and the divider and phase control circuit 254 can implement the divider and phase control circuit 145 of FIG. 1 .
  • the output node of the first reference clock divider 203 a , the output node of the second reference clock divider 203 b , and the output node of the third reference clock divider 203 c are electrically coupled to provide the OR connected signal RCX to an input of the PLL control circuit 205 .
  • the illustrated configuration illustrates one example of clock signal conditioning that can occur on one or more reference clock signals before they are provided to a PLL control circuit.
  • the teachings herein are applicable to other configurations, including implementations in which one or more of the reference clock signals are not conditioned.
  • the PLL control circuit 205 generates a first PLL input clock signal RC 1 , which is provided as an input to a first input frequency divider 206 a to produce a divided reference signal REF.
  • the PLL control circuit 205 can further be used to monitor when the OR connected signal RCX is unreliable.
  • the first PLL 204 a generates a local clock signal LCLK from the first PLL input clock signal RC 1 .
  • the first PLL 204 a can be implemented to have a relatively low loop bandwidth to provide a relatively high amount of jitter attenuation.
  • first PLL input clock signal RC 1 can be a noisy and/or intermittent signal, and implementing the first PLL 204 a with relatively low loop bandwidth can decrease jitter of the local clock signal LCLK.
  • the second PLL 204 b uses a buffered version of the local clock signal LCLK as a reference clock signal for frequency synthesis.
  • FIG. 2 illustrates a configuration using a cascade of two PLLs, the teachings herein are applicable to clock generation circuits using more or fewer PLLs.
  • the charge pump output switch 217 a receives a tristate signal TM, which is used to selectively disable the feedback loop of the first PLL 204 a .
  • the output of the holdover circuit 240 is also electrically connected to the input of the first loop filter 208 a via a holdover switch 217 b.
  • the first loop filter 208 a generates a first tuning voltage Vtune, which is provided as an input to the VCXO 216 a .
  • the VCXO 216 a generates the local clock signal LCLK, which can have a frequency of oscillation that changes with a voltage level of the tuning voltage Vtune.
  • the second PLL 204 b can be a high frequency PLL designed to receive the buffered input clock BCLK of low frequency, for instance approximately 122.88 MHz, and to provide a second local clock signal LCLK 2 of higher frequency, for instance approximately 2457.6 MHz, to the dividing and phasing block 282 .
  • the dividing and phasing block 282 can generate clock signals that are frequency divided relative to the output of the second PLL 204 b and have a known phase.
  • Clock buffers 284 a - 284 d can buffer the clock signals generated by the dividing and phase block 282 .
  • the second PLL 204 b includes a second VCXO divider 215 , a second input clock divider 206 b , a second PFD/CP 207 b , a second loop filter 208 b , a voltage controlled oscillator 216 b , and a second feedback divider 218 b .
  • the general operation of the second PLL 204 b can be similar to that of the first PLL 204 a except it does not use the holdover circuit with a holdover switch nor does it use a charge pump output switch.
  • the control module 252 and the divider and phase control circuit 254 can determine when the output clock signals OCLK 1 to OCLKn are ready. Before the output clock signals OCLK 1 to OCLKn can be provided within the system, both the first PLL 204 a and the second PLL 204 b should achieve phase lock and operate in a steady state condition.
  • the control module 252 can receive a first lock detect signal XLD 1 from a first lock detect circuit 280 a of the first PLL 204 a and a second lock detect signal XLD 2 from a second lock detect circuit 280 b of the second PLL 204 b .
  • a controller 278 within the control module 252 can disable the divider and phase control circuit 254 or set the divider and phase control circuit 254 to a waiting state.
  • Information communicated between the divider and phase control circuit 254 and the control module 252 can occur via a bus that carries internal control signals XINT.
  • the clock detect signals XLD 1 and XLD 2 can be provided to circuity in the dividing and phasing block 282 and such circuity can provide an indication of whether both of the PLLs are locked.
  • the internal control signals XINT can carry information between the controller 278 and finite state machines of the dividing and phasing block 282 .
  • the internal control signals XINT can provide information to the finite state machines to set one or more of the output clock signals at desired frequency and/or an indication as to whether one or more of the finite state machines have completed operations such that the output clock signals have desired frequencies and known phases.
  • the controller 278 can change the state of a system ready signal SysReady to indicate that the output clock signals OCLK 1 to OCLKn are ready.
  • the system ready signal SysReady can be provided by a system ready circuit 279 of the controller 278 .
  • Completion of all operations defined by the output clock configuration operations can define when the system is ready.
  • Communication between the controller 278 and the divider and phase control circuit 254 can allow the controller 278 to detect whether all of the output clocks OCLK 1 to OCLKn are ready and to change the state of the system ready signal SysReady.
  • the system ready signal SysReady can provide an indication to components or system blocks external to the clock generation circuit 102 that the output clock signals are ready. This can be advantageous in a variety of contexts and, particularly, in clock distribution systems that include data converter and processing blocks.
  • the system ready signal SysReady can be used with systems which support JESD204B signaling standard. In this protocol the system ready signal SysReady can enhance the efficiency for transmitting the status of clock outputs across the system.
  • the controller 278 within the control module 252 can also receive signals external to the clock generation circuit 102 .
  • the controller 278 can support serial port interface (SPI) communication, other types of interrupts, general purpose input output (GPIO) communication, the like, or any combination thereof
  • a divider and phase control circuit 254 is configured to receive a reference clock signal LCLK 2 and to provide output clock signals OCLK 1 to OCLKn.
  • the output clock signals OCLK 1 to OCLKn are frequency divided relative to the reference clock signal LCLK 2 .
  • the output clock signals OCLK 1 to OCLKn each have a set phase relative to another output clock signal of the output clock signals when ready.
  • a system ready circuit 279 of the control module 252 is in communication with the divider and phase control circuit 254 .
  • the system ready 279 is circuit configured to provide a system ready signal SysReady indicative of whether all of the output clock signals OCLK 1 to OCLKn are ready. Accordingly, the system ready signal SysReady can be provided external to a clock distribution chip to indicate when all of the output clocks OCLK 1 to OCLKn are ready.
  • the divider and phase control circuit 254 receives the reference clock signal LCLK 2 and provides the output clock signals OCLK 1 , OCLK 2 , and OCLKn. As discussed in connection with FIG. 2 , the output clock signals OCLK 1 , OCLK 2 , and OCLKn can be provided at the outputs of the clock buffers 284 a to 284 d, respectively. In addition, the divider and phase control block 254 can receive control signals from the control module 252 for setting the frequency and/or the phase of the output clock signals OCLK 1 , OCLK 2 , and OCLKn.
  • FIG. 3 illustrates a configuration in which the divider and phase control circuit 254 can generate three output clock signals
  • the teachings herein are applicable to divider and phase control circuit circuits that that generate more or fewer output clock signals.
  • the divider and phase control circuit 254 of FIG. 3 includes the dividing and phasing block 282 .
  • the illustrated dividing and phasing block 282 includes three parallel signal paths: a first signal path having a first output divider 290 a which receives the reference clock signal LCLK 2 and provides a frequency divided version of the reference clock signal, and a first output phasing circuit 292 a which receives the frequency divided version of the reference clock signal and provides an input of the first clock buffer 284 a having a phase adjusted relative to the frequency divided version of the reference clock signal; a second signal path having a second output divider 290 b which receives the reference clock signal LCLK 2 and provides a second frequency divided version of the reference clock signal, and a second output phasing circuit 292 b which receives the second frequency divided version of the reference clock signal and provides an input of the second clock buffer 284 b having a phase adjusted relative to the second frequency divided version of the reference clock signal; and a third signal path having a third output
  • FIG. 3 illustrates a configuration in which the dividing and phasing block 282 shows three parallel signal paths
  • teachings herein are applicable to dividing and phasing blocks that include more or fewer signal paths.
  • the dividing and phasing block 282 can include a first finite state machine 294 a , a second finite state machine 294 b , and a third finite state machine 294 c .
  • Each of these finite state machines can receive one or more control signals from the controller 278 .
  • the first finite state machine 294 a can send one or more control signals to the first output divider 290 a and to the first output phasing circuit 292 a to control frequency and phase of the first output clock signal OCLK 1 .
  • the output dividers 290 a to 290 c can be controlled by finite state machines 290 a to 294 c , respectively, to cause both the frequency and phase of the output clock signals OCLK 1 to OCLKn, respectively, to be adjusted as will be discussed in more detail below.
  • one or more of the finite state machines can be physically implemented in the controller 278 .
  • the controller 278 can use the low frequency reference signal SysRef having a frequency that is lower than the reference clock signal LCLK 2 .
  • the controller 278 can communicate with the first finite state machine 294 a , the second finite state machine 294 b , and the third finite state machine 294 c to perform various output clock configurationoperations.
  • Output clock configuration operations can include changing a frequency division factor for a set period of time or skipping a fixed number of cycles for a set period time.
  • the controller 278 can communicate with the first finite state machine 294 a to control the phase of the first output clock signal OCLK 1 relative to the low frequency reference signal SysRef using variable frequency division. For a fixed period of time, the controller 278 can control the first finite state machine 294 a to cause the first output frequency divider 290 a to frequency divide the reference signal LCKL 2 by a factor of M, where M is an integer such as 11, and then the controller 278 can control the first FSM 2 294 a to cause the first output frequency divider 290 a to frequency divide the reference signal LCKL 2 by a factor of L, where L is a different integer such as 10 and L corresponds to a divisor that will result in the first output clock signal OCLK 1 having a desired output frequency.
  • the output clock signals OCLK 1 , OCLK 2 , and OCLKn should be in the steady state.
  • the controller 278 can use the end-of-cycle or a completion flag from the first finite state machine 294 a , the second finite state machine 294 b , and the third finite state machine 294 c to cause the system ready signal SysReady to change to a ready state.
  • the system ready circuit 279 can toggle the system ready signal SysReady responsive to each of the finite state machines being in a done state.
  • the output dividers 290 a - 290 c , the phase control circuits 292 a - 292 c, and/or the clock buffers 284 a , 284 b , and 284 d may be controlled individually and/or in groups by the controller 278 .
  • any command which changes the state of the divider and phase control circuit 254 can result in a delay before implementation is complete. In this situation, the controller 278 will indicate a not ready state via a state of the system ready signal SysReady.
  • the controller 278 may be configured to indicate a ready status on a dedicated hardware pin (e.g., a GPIO pin), other contact of a chip (e.g., a bump in a flip-chip implementation), or by way of a register 310 that is accessible to an external host system.
  • a dedicated hardware pin e.g., a GPIO pin
  • other contact of a chip e.g., a bump in a flip-chip implementation
  • a register 310 that is accessible to an external host system.
  • the third system ready flag SysReady 3 can indicate when the output clock configuration operations of the third set of output clocks OCLK 1 B, OCLK 2 B, and OCLKnB have completed.
  • signal paths of the divider and phase control circuit 254 b receive the n-th output clock signal OCLKn from the output clock signals OCLK 1 to OCLKn.
  • the n-th output clock signal OCLKn undergoes frequency division and phase shifting relative to the third output clock signal OCLK 3 in providing the output clock signals OCLK 1 B, OCLK 2 B, and OCLK 4 n.
  • the controller 278 can change the system ready signal SysReady to transition to the second state 604 , the “not ready” state.
  • the return to the initial state 604 from the second state 604 occurs if there is no request for modifying a phase or a frequency of an output clock signal of the output clock signals OCLK 1 to OCLKn of FIG. 3 .
  • the controller 278 can communicate with finite state machines within the divider and phase control circuit 254 to start the change and to enter state 606 .
  • the state 606 is a state during which the output clock configuration operations are performed with finite state machines within the divider and phase control circuit 254 .
  • the state 606 can be maintained until the first finite state machine 294 a , the second finite state machine 294 b , and the third finite state machine 294 c of the divider and phase control circuit 254 indicate that output clock configuration operations are complete.
  • the controller 278 can change state to state 608 , which is a “ready state” where the controller 278 toggles the system ready signal SysReady to indicate that the output clock signals are ready.
  • state 608 is a “ready state” where the controller 278 toggles the system ready signal SysReady to indicate that the output clock signals are ready.
  • the sequence of states can cycle back to the state 602 and the controller 278 can wait for a next command.
  • FIG. 6 is a flow diagram of a process 700 of determining that output clock signals of a clock generation circuit are ready according to one embodiment.
  • the process can determine whether one or more phase locked loops are locked. For instance, electronic circuity can determine that the first lock detect signal XLD 1 and the second lock detect signal XLD 2 of FIG. 2 each indicate that a respective phase locked loop is locked.
  • the process 700 can continue to monitor whether the phase locked loops are locked at block 702 . On the other hand, when the phase locked loop(s) are locked, the process 700 can proceed to block 704 . For instance, if both the first lock detect signal XLD 1 and the second lock detect signal XLD 2 of FIG. 2 are asserted, then the process 700 can proceed to block 704 .
  • the progress of re-phasing can be monitored at block 706 . This can monitor whether the output clock signals are ready. If the output clock signals are not determined to be ready, the progress of re-phase can continue to be monitored at block 706 .
  • the system ready flag can be toggled at block 708 .
  • the rephrasing complete decision can correspond to checking if each finite state machine 294 a to 294 c is in a done state or has ceased to request a clock signal for a threshold period of time.
  • the controller 278 changes the state of the system ready signal SysReady to indicate a ready condition.
  • Devices employing one or more of the above described clock generation circuits can be implemented into various electronic devices.
  • Examples of the electronic devices can include, but are not limited to, consumer electronic products, parts of the consumer electronic products, electronic test equipment, etc.
  • Examples of the electronic devices can also include circuits of optical networks or other communication networks.
  • the consumer electronic products can include, but are not limited to, a phone such as a smart phone, a laptop computer, a tablet computer, an automobile, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multifunctional peripheral device, etc.
  • the electronic device can include unfinished products, including those for industrial, medical and automotive applications.

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  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11469765B1 (en) * 2021-09-08 2022-10-11 National Technology & Engineering Solutions Of Sandia, Llc Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency
US11533059B1 (en) * 2021-06-29 2022-12-20 Infineon Technologies Ag Frequency generation with dynamic switching between closed-loop operation and open-loop operation

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9148153B2 (en) * 2013-12-30 2015-09-29 Intel Corporation Systems and methods for frequency domain calibration and characterization
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US9425808B1 (en) * 2015-06-05 2016-08-23 Texas Instruments Incorporated Frequency detector
US10050632B2 (en) 2016-12-30 2018-08-14 Texas Instruments Incorporated Counter-based SYSREF implementation
US10224978B1 (en) * 2017-08-16 2019-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. Clock and data recovery circuit
JP2020010206A (ja) * 2018-07-10 2020-01-16 セイコーエプソン株式会社 回路装置、発振器、クロック信号生成装置、電子機器及び移動体
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CN115102682B (zh) * 2022-06-17 2023-12-29 万东百胜(苏州)医疗科技有限公司 一种用于超声系统的adc自动同步方法及设备

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179303A (en) * 1991-10-24 1993-01-12 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
EP0753808A2 (fr) 1995-07-14 1997-01-15 Oki Electric Industry Co., Ltd. Circuit de distribution d'horloge
WO1998037656A2 (fr) 1997-02-06 1998-08-27 Rambus, Inc. Circuit a boucles a retard de phase servant a regler un retard d'horloge
US6259290B1 (en) * 1998-06-30 2001-07-10 Kabushiki Kaisha Toshiba Delay locked loop having a mis-lock detecting circuit
US20010028276A1 (en) * 2000-03-22 2001-10-11 Beomsup Kim Self-calibration device and method for calibrating phase offset between output waveforms of ring osciliator
US6970047B1 (en) * 2003-07-28 2005-11-29 Lattice Semiconductor Corporation Programmable lock detector and corrector
US20080164917A1 (en) * 2007-01-10 2008-07-10 Floyd Brian A Circuits and methods for implementing sub-integer-n frequency dividers using phase rotators
US20090261862A1 (en) * 2008-04-17 2009-10-22 Altera Corporation Techniques For Measuring Voltages in a Circuit
US20090284318A1 (en) * 2007-09-17 2009-11-19 Mipsabg Chipidea, Lda. High speed pll clock multiplier
US7683679B2 (en) * 2007-11-14 2010-03-23 Texas Instruments Incorporated AFSM circuit and method for low jitter PLL CMOS programmable divider
US20110221486A1 (en) 2010-03-12 2011-09-15 Hirata Erick M Digitally calibrated high speed clock distribution
US20130195157A1 (en) * 2012-01-31 2013-08-01 Innophase Inc. Transceiver Architecture and Methods for Demodulating and Transmitting Phase Shift Keying Signals
US20150004919A1 (en) * 2011-12-07 2015-01-01 Telefonaktiebolaget L M Ericsson (Publ) Analog Phase-Locked Loop with Enhanced Acquisition
US20150222274A1 (en) * 2014-02-04 2015-08-06 Hittite Microwave Corporation System ready in a clock distribution chip
US20160105189A1 (en) * 2014-10-10 2016-04-14 Fujitsu Limited Delay circuit, delay locked loop circuit including delay circuit and processor including delay locked loop circuit
US20160241249A1 (en) * 2013-11-19 2016-08-18 Intel Corporation Clock calibration using asynchronous digital sampling

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121816A (en) * 1999-04-23 2000-09-19 Semtech Corporation Slave clock generation system and method for synchronous telecommunications networks

Patent Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179303A (en) * 1991-10-24 1993-01-12 Northern Telecom Limited Signal delay apparatus employing a phase locked loop
EP0753808A2 (fr) 1995-07-14 1997-01-15 Oki Electric Industry Co., Ltd. Circuit de distribution d'horloge
WO1998037656A2 (fr) 1997-02-06 1998-08-27 Rambus, Inc. Circuit a boucles a retard de phase servant a regler un retard d'horloge
US6259290B1 (en) * 1998-06-30 2001-07-10 Kabushiki Kaisha Toshiba Delay locked loop having a mis-lock detecting circuit
US20010028276A1 (en) * 2000-03-22 2001-10-11 Beomsup Kim Self-calibration device and method for calibrating phase offset between output waveforms of ring osciliator
US6970047B1 (en) * 2003-07-28 2005-11-29 Lattice Semiconductor Corporation Programmable lock detector and corrector
US20080164917A1 (en) * 2007-01-10 2008-07-10 Floyd Brian A Circuits and methods for implementing sub-integer-n frequency dividers using phase rotators
US20090284318A1 (en) * 2007-09-17 2009-11-19 Mipsabg Chipidea, Lda. High speed pll clock multiplier
US7683679B2 (en) * 2007-11-14 2010-03-23 Texas Instruments Incorporated AFSM circuit and method for low jitter PLL CMOS programmable divider
US20090261862A1 (en) * 2008-04-17 2009-10-22 Altera Corporation Techniques For Measuring Voltages in a Circuit
US20110221486A1 (en) 2010-03-12 2011-09-15 Hirata Erick M Digitally calibrated high speed clock distribution
US20150004919A1 (en) * 2011-12-07 2015-01-01 Telefonaktiebolaget L M Ericsson (Publ) Analog Phase-Locked Loop with Enhanced Acquisition
US20130195157A1 (en) * 2012-01-31 2013-08-01 Innophase Inc. Transceiver Architecture and Methods for Demodulating and Transmitting Phase Shift Keying Signals
US20160241249A1 (en) * 2013-11-19 2016-08-18 Intel Corporation Clock calibration using asynchronous digital sampling
US20150222274A1 (en) * 2014-02-04 2015-08-06 Hittite Microwave Corporation System ready in a clock distribution chip
US20160105189A1 (en) * 2014-10-10 2016-04-14 Fujitsu Limited Delay circuit, delay locked loop circuit including delay circuit and processor including delay locked loop circuit

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Analog Devices, "AD9514 Data Sheet: 1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs," Rev. 0, Jul. 2005, 28 pages.
Boyd, Barrie, "High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516," Texas Instruments, Sep. 1998, 22 pages.
Chou, Ju-Ming, "High-Precision Multi-Phase Clock Generation", A Dissertation submitted to Department of Electronics Engineering and Institute of Electronics College of Electrical and Computer Engineering National Chiao-Tung University in partial Fulfillment of the requirements for the Degree of Doctor of Philosophy in Electronics Engineering, Jun. 2007.
Extended European Search Report dated Jun. 24, 2015 for European Patent Application No. 15152946.8 filed Jan. 28, 2015, 7 pages.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11533059B1 (en) * 2021-06-29 2022-12-20 Infineon Technologies Ag Frequency generation with dynamic switching between closed-loop operation and open-loop operation
US11469765B1 (en) * 2021-09-08 2022-10-11 National Technology & Engineering Solutions Of Sandia, Llc Multi-channel high-speed converter clock synchronization with autonomous coherent deterministic latency

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CN104821824B (zh) 2018-02-16

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