US9460783B2 - Determining soft data - Google Patents

Determining soft data Download PDF

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US9460783B2
US9460783B2 US14/294,802 US201414294802A US9460783B2 US 9460783 B2 US9460783 B2 US 9460783B2 US 201414294802 A US201414294802 A US 201414294802A US 9460783 B2 US9460783 B2 US 9460783B2
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memory cell
sense operation
soft data
sense
single stepped
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US20150348619A1 (en
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Violante Moschiano
Andrea D'Alessandro
Andrea Giovanni Xotta
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US Bank NA
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Micron Technology Inc
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Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: D'ALESSANDRO, ANDREA, MOSCHIANO, VIOLANTE, XOTTA, ANDREA GIOVANNI
Priority to PCT/US2015/033475 priority patent/WO2015187530A1/fr
Priority to JP2016569399A priority patent/JP2017520074A/ja
Priority to EP15802530.4A priority patent/EP3152764B1/fr
Priority to KR1020177000169A priority patent/KR101796426B1/ko
Priority to CN201580029112.2A priority patent/CN106463176B/zh
Priority to TW104118009A priority patent/TWI601409B/zh
Publication of US20150348619A1 publication Critical patent/US20150348619A1/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
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Priority to US15/266,271 priority patent/US10573379B2/en
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Priority to US16/791,860 priority patent/US11170848B2/en
Priority to US17/453,517 priority patent/US11688459B2/en
Priority to US18/339,168 priority patent/US20240029788A1/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction

Definitions

  • the present disclosure relates generally to semiconductor memory and methods, and more particularly, to determining soft data.
  • Memory devices are typically provided as internal, semiconductor, integrated circuits and/or external removable devices in computers or other electronic devices.
  • memory can include volatile and non-volatile memory.
  • Volatile memory can require power to maintain its data and can include random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others.
  • RAM random-access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • Non-volatile memory can retain stored data when not powered and can include NAND flash memory, NOR flash memory, phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM), among others.
  • NAND flash memory NAND flash memory
  • NOR flash memory NAND flash memory
  • PCRAM phase change random access memory
  • RRAM resistive random access memory
  • MRAM magnetic random access memory
  • SSD solid state drive
  • An SSD can include non-volatile memory (e.g., NAND flash memory and/or NOR flash memory), and/or can include volatile memory (e.g., DRAM and/or SRAM), among various other types of non-volatile and volatile memory.
  • Flash memory devices can include memory cells storing data in a charge storage structure such as a floating gate, for instance, and may be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices may use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
  • Memory cells in an array architecture can be programmed to a target (e.g., desired) state. For instance, electric charge can be placed on or removed from the charge storage structure (e.g., floating gate) of a memory cell to program the cell to a particular data state.
  • the stored charge on the charge storage structure of the memory cell can indicate a threshold voltage (Vt) of the cell.
  • a single level cell can be programmed to a targeted one of two different data states, which can be represented by the binary units 1 or 0.
  • Some flash memory cells can be programmed to a targeted one of more than two data states (e.g., 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110).
  • Such cells may be referred to as multi state memory cells, multiunit cells, or multilevel cells (MLCs).
  • MLCs can provide higher density memories without increasing the number of memory cells since each cell can represent more than one digit (e.g., more than one bit).
  • a state of a flash memory cell can be determined by sensing the stored charge on the charge storage structure (e.g., the Vt) of the cell.
  • a number of mechanisms such as read disturb, program disturb, and/or charge loss (e.g., charge leakage), for example, can cause the Vt of the memory cell to change.
  • an error may occur when the state of the cell is sensed.
  • the cell may be sensed to be in a state other than the target state (e.g., a state different than the state to which the cell was programmed).
  • ECC error correction code
  • LDPC low-density parity-check
  • FIG. 1 illustrates a schematic diagram of a portion of a memory array in accordance with a number of embodiments of the present disclosure.
  • FIG. 2 illustrates a diagram of a number of threshold voltage distributions, sensing voltages, and data assignments associated with a sensing operation.
  • FIG. 3 illustrates a schematic diagram of sense circuitry in accordance with a number of embodiments of the present disclosure.
  • FIG. 4A illustrates an example of a timing diagram associated with a single sense operation in accordance with a number of embodiments of the present disclosure.
  • FIG. 4B illustrates an additional example of a timing diagram associated with a single sense operation in accordance with a number of embodiments of the present disclosure.
  • FIG. 5 illustrates a block diagram of an apparatus in the form of a memory device in accordance with a number of embodiments of the present disclosure.
  • the present disclosure includes apparatuses and methods for determining soft data.
  • a number of embodiments include determining soft data associated with a data state of a memory cell, wherein the soft data is determined by performing a single stepped sense operation on the memory cell.
  • Hard data can refer to a binary data value stored in one or more memory cells and provided to a host responsive to a sense (e.g., read) operation, for example.
  • soft data associated with the sensed data state (e.g., with the hard data) of the memory cell can also be determined.
  • the soft data can, for example, indicate the quality and/or confidence of the hard data (e.g., information regarding the probability of the cell storing the read hard data or of the cell storing different data). Accordingly, soft data can provide benefits such as increased accuracy and/or reliability (e.g., decreased error rate), and/or increased memory life, among other benefits.
  • Embodiments of the present disclosure can determine soft data associated with the data state (e.g., with the hard data) of a memory cell by performing a single (e.g., only one) sense operation on the cell.
  • the same sense operation can be used to determine both a hard data value and a number of soft data values.
  • multiple (e.g., more than one) separate sense operations may need to be performed on the cell to determine the soft data.
  • the soft data may be determined by performing one or more sense operations on the cell that are in addition to (e.g., separate from) the sense operation that determines the hard data.
  • embodiments of the present disclosure can determine soft data by performing a single sense operation, embodiments of the present disclosure can determine the soft data faster than previous approaches that use multiple sense operations to determine the soft data, which can increase the efficiency and/or performance (e.g., speed) of the memory as compared with such previous approaches.
  • a number of something can refer to one or more such things.
  • a number of memory cells can refer to one or more memory cells.
  • the designators “N” and “M”, as used herein, particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included with a number of embodiments of the present disclosure.
  • FIG. 1 illustrates a schematic diagram of a portion of a memory array 100 in accordance with a number of embodiments of the present disclosure.
  • the embodiment of FIG. 1 illustrates a NAND architecture non-volatile memory array.
  • memory array 100 includes access lines (e.g., word lines 105 - 1 , . . . , 105 -N) and data lines (e.g., bit lines) 107 - 1 , 107 - 2 , 107 - 3 , . . . , 107 -M.
  • access lines e.g., word lines 105 - 1 , . . . , 105 -N
  • data lines e.g., bit lines
  • bit lines 107 - 1 , 107 - 2 , 107 - 3 , . . . , 107 -M can be some power of two (e.g., 256 word lines by 4,096 bit lines).
  • Memory array 100 includes NAND strings 109 - 1 , 109 - 2 , 109 - 3 , . . . , 109 -M.
  • Each NAND string includes non-volatile memory cells 111 - 1 , . . . , 111 -N, each communicatively coupled to a respective word line 105 - 1 , . . . , 105 -N.
  • Each NAND string (and its constituent memory cells) is also associated with a bit line 107 - 1 , 107 - 2 , 107 - 3 , . . . , 107 -M.
  • each NAND string 109 - 1 , 109 - 2 , 109 - 3 , . . . , 109 -M are connected in series between a source select gate (SGS) (e.g., a field-effect transistor (FET)) 113 , and a drain select gate (SGD) (e.g., FET) 119 .
  • SGS source select gate
  • SGD drain select gate
  • Each source select gate 113 is configured to selectively couple a respective NAND string to a common source 123 responsive to a signal on source select line 117
  • each drain select gate 119 is configured to selectively couple a respective NAND string to a respective bit line responsive to a signal on drain select line 115 .
  • a source of source select gate 113 is connected to a common source 123 .
  • the drain of source select gate 113 is connected to memory cell 111 - 1 of the corresponding NAND string 109 - 1 .
  • the drain of drain select gate 119 is connected to bit line 107 - 1 of the corresponding NAND string 109 - 1 at drain contact 121 - 1 .
  • the source of drain select gate 119 is connected to memory cell 111 -N (e.g., a floating-gate transistor) of the corresponding NAND string 109 - 1 .
  • construction of non-volatile memory cells 111 - 1 , . . . , 111 -N includes a charge storage structure such as a floating gate, and a control gate.
  • Non-volatile memory cells 111 - 1 , . . . , 111 -N have their control gates coupled to a word line, 105 - 1 , . . . , 105 -N respectively.
  • a “row” of the non-volatile memory cells are those memory cells commonly coupled to a given word line 105 - 1 , . . . , 105 -N.
  • the use of the terms “column” and “row” is not meant to imply a particular linear (e.g., vertical and/or horizontal) orientation of the non-volatile memory cells.
  • a NOR array architecture would be similarly laid out, except that the string of memory cells would be coupled in parallel between the select gates.
  • Subsets of cells coupled to a selected word line can be programmed and/or sensed (e.g., read) together (e.g., at the same time).
  • a program operation e.g., a write operation
  • a sense operation such as a read or program verify operation, can include sensing a voltage and/or current change of a bit line coupled to a selected cell in order to determine the data state (e.g., hard data value) of the selected cell.
  • the sense operation e.g., the same sense operation used to determine the hard data value of the selected cell
  • the sense operation can also be used to determine soft data associated with the data state of the selected cell, as will be further described herein.
  • the sense operation can include providing a voltage to (e.g., biasing) a bit line (e.g., bit line 107 - 1 ) associated with a selected memory cell above a voltage (e.g., bias voltage) provided to a source (e.g., source 123 ) associated with the selected memory cell.
  • a sense operation could alternatively include precharging the bit line followed with discharge when a selected cell begins to conduct, and sensing the discharge. Examples of sense operations in accordance with embodiments of the present disclosure will be further described herein.
  • Sensing the state of a selected cell can include providing a number of stepped sensing signals (e.g., stepped sensing signals that include different read voltage levels) to a selected word line while providing a number of pass signals (e.g., read pass voltages) to the word lines coupled to the unselected cells of the string sufficient to place the unselected cells in a conducting state independent of the Vt of the unselected cells.
  • the bit line corresponding to the selected cell being read and/or verified can be sensed to determine whether or not the selected cell conducts in response to the particular sensing voltage applied to the selected word line.
  • the data state of the selected cell, and the soft data associated with the data state can be determined based on the current of the bit line corresponding to the selected cell, as will be further described herein.
  • FIG. 2 illustrates a diagram 201 of a number of threshold voltage (Vt) distributions, sensing voltages, and data (e.g., hard and soft data) assignments associated with a sensing operation.
  • the two Vt distributions 225 - 1 and 225 - 2 shown in FIG. 2 can correspond to two-bit (e.g., four-state) multilevel memory cells.
  • a two-bit memory cell would include two additional Vt distributions (e.g., one corresponding to each of the four data states).
  • Vt distributions corresponding to data states L 1 and L 2 are shown.
  • Embodiments of the present disclosure are not limited to two-bit memory cells.
  • Vt distributions 225 - 1 and 225 - 2 represent two target data states (e.g., L 1 and L 2 , respectively) to which the memory cells can be programmed.
  • Each target data state has a lower page data value and an upper page data value corresponding thereto.
  • data state L 1 corresponds to data “11” (e.g., a lower page data value of 1 and an upper page data value of 1)
  • data state L 2 corresponds to data “01” (e.g., a lower page data value of 1 and an upper page data value of 0). That is, the hard data values of the upper pages of target states L 1 and L 2 are 1 and 0, respectively.
  • the hard data values of the lower pages of target states L 1 and L 2 are each 1. Embodiments of the present disclosure, however, are not limited to these particular data assignments.
  • Vt distributions 225 - 1 and 225 - 2 can represent a number of memory cells that are programmed to the corresponding target states (e.g., L 1 and L 2 , respectively), with the height of a Vt distribution curve indicating a number of cells programmed to a particular voltage within the Vt distribution (e.g., on average).
  • the width of the Vt distribution curve indicates the range of voltages that represent a particular target state (e.g., the width of the Vt distribution curve 225 - 2 for L 2 represents the range of voltages that correspond to a hard data value of 01).
  • a sensing (e.g., read) voltage located between Vt distributions 225 - 1 and 225 - 2 can be used to distinguish between states L 1 and L 2 .
  • the unselected memory cells of the string can be biased with a pass voltage so as to be in a conducting state.
  • current can flow between the source contact at one end of the string and a drain line contact at the other end of the string.
  • the data state of the selected cell can be determined based on the current sensed on a bit line corresponding to a particular string when the selected cell begins to conduct (e.g., in response to the particular read voltage applied to the control gate of the cell (via a selected word line)), as will be further described herein.
  • Each data state (e.g., L 1 , and L 2 ) of the memory cells can have soft data associated therewith.
  • the Vt distribution (e.g., 225 - 1 or 225 - 2 ) associated with each data state can have soft data values (e.g., bits) assigned thereto.
  • soft data values e.g., bits assigned thereto.
  • two bits are used to provide soft data (e.g., quality and/or confidence information) associated with the data states.
  • Soft data (e.g., the soft data values) associated with a data state of a memory cell can indicate a location of the Vt associated with the memory cell within the Vt distribution associated with the data state of the memory cell.
  • soft data 00 associated with data state L 2 indicates that the Vt of the memory cell is located at a voltage greater than reference voltage R 5 within Vt distribution 225 - 2 (e.g., that the Vt of the memory cell is located toward the middle of Vt distribution 225 - 2 )
  • soft data 00 associated with data state L 1 indicates that the Vt of the memory cell is located at a voltage less than reference voltage R 1 within Vt distribution 225 - 1 (e.g., that the Vt of the memory cell is located toward the middle of Vt distribution 225 - 1 ).
  • soft data 10 associated with data state L 2 indicates that the Vt of the memory cell is located at a voltage between reference voltages R 4 and R 5 within Vt distribution 225 - 2
  • soft data 10 associated with data state L 1 indicates that the Vt of the memory cell is located at a voltage between reference voltages R 1 and R 2
  • soft data 11 associated with data state L 2 indicates that the Vt of the memory cell is located at a voltage between reference voltages R 3 and R 4
  • soft data 11 associated with data state L 1 indicates that the Vt of the memory cell is located at a voltage between reference voltages R 2 and R 3 .
  • soft data 11 may indicate a lower confidence that the hard data matches the target state to which the cell was originally programmed.
  • Soft data (e.g., the soft data values) associated with a data state of a memory cell can also indicate a probability of whether the Vt associated with the memory cell corresponds to the data state of the memory cell.
  • soft data 00 associated with the data state L 2 indicates a strong probability that the Vt of the memory cell corresponds to data state L 2 (e.g., upper page hard data 0)
  • soft data 10 associated with the data state L 2 indicates a moderate probability (e.g., a probability that is less than the strong probability) that the Vt of the memory cell corresponds to data state L 2
  • soft data 11 associated with data state L 2 indicates a weak probability (e.g., a probability that is less than the moderate probability) that the Vt of the memory cell corresponds to data state L 2 .
  • soft data 00 associated with the data state L 1 indicates a strong probability that the Vt of the memory cell corresponds to data state L 1 (e.g., upper page hard data 1)
  • soft data 10 associated with data state L 1 indicates a moderate probability that the Vt of the memory cell corresponds to data state L 1
  • soft data 11 associated with data state L 1 indicates a weak probability that the Vt of the memory cell corresponds to data state L 1 .
  • Embodiments of the present disclosure are not limited to the reference voltages and/or soft data assignments shown in FIG. 2 .
  • a greater number of soft data assignments can be used to indicate a more precise Vt location within a Vt distribution and/or a more precise probability of whether a Vt corresponds to a data state.
  • five reference voltages and six soft data values e.g., six different soft data possibilities representing six different hard data quality and/or confidence levels have been illustrated in FIG. 2 .
  • the soft data values (e.g., at least two soft data values) associated with the data state of a memory cell can be determined by performing a single (e.g., only one) sense operation on the memory cell, as will be further described herein.
  • the soft data values associated with the data state of a memory cell can be determined using the same sense operation used to determine the data state of the cell, as will be further described herein.
  • multiple (e.g., more than one) separate sense operations may need to be performed on a memory cell to determine the soft data associated with the data state of the cell.
  • the soft data may be determined by performing one or more sense operations on the cell that are in addition to (e.g., separate from) the sense operation that determines the hard data. Because embodiments of the present disclosure can determine soft data by performing a single sense operation, embodiments of the present disclosure can determine the soft data faster than previous approaches that use multiple sense operations to determine the soft data, which can increase the efficiency and/or performance (e.g., speed) of the memory as compared with such previous approaches.
  • FIG. 3 illustrates a schematic diagram of sense circuitry 302 in accordance with a number of embodiments of the present disclosure.
  • Sense circuitry 302 can perform a single (e.g., only one) sense operation on a memory cell (e.g., a memory cell 111 - 1 , . . . , 111 -N previously described in connection with FIG. 1 ) to determine the data state of the cell (e.g., a hard data value) and associated soft data (e.g., soft data values).
  • a memory cell e.g., a memory cell 111 - 1 , . . . , 111 -N previously described in connection with FIG. 1
  • the data state of the cell e.g., a hard data value
  • associated soft data e.g., soft data values
  • the single sense operation can be, for example, an active sense operation, such as an active bit line sense operation (e.g., a sense operation in which a single bit line, which can be referred to as the active bit line, is selectively coupled to sense circuitry 302 ). That is, sense circuitry 302 can be active bit line sense circuitry (e.g. circuitry that can be selectively coupled to a single bit line).
  • an active sense operation such as an active bit line sense operation (e.g., a sense operation in which a single bit line, which can be referred to as the active bit line, is selectively coupled to sense circuitry 302 ).
  • sense circuitry 302 can be active bit line sense circuitry (e.g. circuitry that can be selectively coupled to a single bit line).
  • embodiments of the present disclosure are not limited to a particular type of sense circuitry or sense operation.
  • sense circuitry 302 can be coupled (e.g., selectively coupled) to a bit line and a source of a memory array, such as bit lines 107 - 1 , 107 - 2 , 107 - 3 , . . . , 107 -M and source 123 of memory array 100 previously described in connection with FIG. 1 .
  • a single sensing signal e.g., read voltage
  • the word line e.g., word line 105 - 1 , . . . , 105 -N previously described in connection with FIG.
  • the single sense operation can be performed using only a single sensing signal.
  • the single sensing signal can be, for example, a stepped sensing signal, as will be further described herein (e.g., in connection with FIGS. 4A and 4B ).
  • sense circuitry 302 can sense the current on the bit line (e.g., the active bit line) to which the selected cell is coupled. That is, the single sense operation can sense only a single value associated with the selected memory cell (e.g., the current on the bit line to which the selected cell is coupled). This single value (e.g., the sensed bit line current) can be directly correlated to the threshold voltage of the selected cell. Accordingly, the data state of the selected cell, and the soft data associated therewith, can be determined based on the sensed single value (e.g., based on the sensed bit line current).
  • sense circuitry 302 can include transistor 334 and capacitance 336 (e.g., a discrete capacitor or parasitic capacitance) coupled to the bit line to which the selected cell is coupled, transistor 332 (e.g., bit line pre-charge transistor) coupled to a supply voltage node 330 (e.g., Vcc), and transistor 338 (e.g., bit line clamp transistor) coupled to transistors 332 and 334 .
  • transistor 334 can be operated to float capacitance 336 , and the current on the bit line to which the selected cell is coupled (e,g., the bit line current) can flow through, and be sensed via, transistors 338 and 332 .
  • Transistors 332 and 338 can be operated to sink the bit line current, which can sink the charge from capacitance 336 .
  • sense circuitry 302 can include an analog-to-digital (ADC) converter 342 coupled to capacitance 336 and the bit line to which the selected cell is coupled, and/or a boost driver 344 coupled to capacitance 336 (e.g., to the plate of capacitance 336 that is opposite from the plate coupled to ADC converter 342 ).
  • ADC analog-to-digital
  • ADC converter 342 and/or boost driver 344 can convert (e.g., perform an ADC conversion of) the voltage across capacitance 336 during the sense operation to a digital value that corresponds to the data state of the selected cell and the associated soft data (e.g., the digital values previously described in connection with FIG. 2 ). That is, ADC converter 342 and/or boost driver 344 can code the data state of the selected cell and the soft data associated therewith by performing an ADC conversion (e.g., translation) of the voltage across capacitance 336 during the sense operation.
  • ADC converter 342 and/or boost driver 344 can be, for example, inverters, such as PMOS inverters. However, embodiments of the present disclosure are not limited to a particular type of ADC converter or boost driver.
  • FIG. 4A illustrates an example of a timing diagram 403 associated with a single sense operation in accordance with one or more embodiments of the present disclosure.
  • FIG. 4B illustrates an additional example of a timing diagram 404 associated with a single sense operation in accordance with one or more embodiments of the present disclosure.
  • the single sense operation can be performed on an array of memory cells (e.g., array 100 previously described in connection with FIG. 1 ) to determine the data state of a selected cell and the associated soft data values, as previously described herein.
  • the single sense operation can be a multilevel cell sense operation (e.g., a sense operation that determines the data state, and the soft data associated therewith, of a multilevel memory cell).
  • Timing diagrams 403 and 404 illustrate a number of waveforms (e.g., waveforms 451 , 453 , 458 , and 460 ) associated with a single sense operation in accordance with the present disclosure.
  • Waveform 451 represents a pass signal provided to the unselected word lines of the array (e.g., the word lines coupled to the unselected memory cells of the string that includes the selected cell).
  • the unselected word lines are increased to pass voltage (e.g., read pass voltage) 452 , as shown in FIGS. 4A and 4B .
  • pass voltage e.g., read pass voltage
  • FIGS. 4A and 4B Providing the pass signal to the unselected word lines (e.g., increasing the unselected word lines to pass voltage 452 ) can place the unselected cells in a conducting state, as previously described herein.
  • Waveforms 453 and 460 each represent a single sensing signal provided to the selected word line of the array (e.g., the word line coupled to the selected cell). Providing the single sensing signal to the selected word line can apply the single sensing signal to the selected cell (e.g., to the control gate of the cell), as previously described herein.
  • the single sensing signal is a stepped sensing signal.
  • the stepped sensing signal steps down. That is, at initial time t 0 , the selected word line is increased to voltage level 454 .
  • the selected word line is then stepped down (e.g., decreased) to voltage level 455 at time t 2 , further stepped down to voltage level 456 at time t 4 , and further stepped down to voltage level 457 at time t 6 , as shown in FIG. 4A .
  • the stepped sensing signal steps up. That is, at initial time t 0 , the selected word line is increased to voltage level 461 .
  • the selected word line is then stepped up (e.g., increased) to voltage level 462 at time t 2 , further stepped up to voltage level 463 at time t 4 , and further stepped up to voltage level 464 at time t 6 .
  • Embodiments of the present disclosure are not limited to the stepped sensing signals illustrated in FIGS. 4A and 4B .
  • Waveform 458 represents a signal provided to transistor 334 previously described in connection with FIG. 3 .
  • the signal can be provided to transistor 334 while the single sensing signal is being provided to the selected word line (e.g., after the sensing signal steps down or up through the respective different voltage levels), but may not be provided to transistor 334 (e.g., may be decreased to voltage level 459 or turned off) while the sensing signal steps up or down from the respective different voltage levels of the sensing signal.
  • the signal can be provided to transistor 334 while the single sensing signal is being provided to the selected word line (e.g., after the sensing signal steps down or up through the respective different voltage levels), but may not be provided to transistor 334 (e.g., may be decreased to voltage level 459 or turned off) while the sensing signal steps up or down from the respective different voltage levels of the sensing signal.
  • the sensing signal steps up or down from the respective different voltage levels of the sensing signal.
  • the signal can be provided to transistor 334 while voltages 454 , 455 , 456 , and 457 are being provided to the selected word line (e.g., from time t 1 to time t 2 , from time t 3 to time t 4 , from time t 5 to time t 6 , and from time t 7 to time t 8 ), but not while the sensing signal steps down from voltage level 454 to voltage level 455 (e.g., from time t 2 to time t 3 ), while the sensing signal steps down from voltage level 455 to 456 (e.g., from time t 4 to time t 5 ), while the sensing signal steps down from voltage level 456 to 457 (e.g., from time t 6 to time t 7 ), or while the sensing signal steps down from voltage level 457 (e.g., from time t 8 to time t 9 ).
  • the selected word line e.g., from time t 1 to time t 2 , from time t 3 to
  • the signal can be provided to transistor 334 while voltages 461 , 462 , 463 , and 464 are being provided to the selected word line (e.g., from time t 1 to time t 2 , from time t 3 to time t 4 , from time t 5 to time t 6 , and from time t 7 to time t 8 ), but not while the sensing signal steps up from voltage level 461 to voltage level 462 (e.g., from time t 2 to time t 3 ), while the sensing signal steps up from voltage level 462 to 463 (e.g., from time t 4 to time t 5 ), while the sensing signal steps up from voltage level 463 to 464 (e.g., from time t 6 to time t 7 ), or while the sensing signal steps down from voltage level 464 (e.g., from time t 8 to time t 9 ).
  • Providing the signal to transistor 334 can float capacitance 336 , as previously
  • the current on the bit line to which the selected cell is coupled can be sensed while the signal represented by waveform 458 is provided to transistor 334 (e.g., while the respective different voltage levels of the single sensing signal represented by waveforms 453 and 460 is being provided to the selected word line).
  • the bit line current can be sensed from time t 1 to time t 2 , from time t 3 to time t 4 , from time t 5 to time t 6 , and from time t 7 to time t 8 .
  • the bit line current can sensed by, for example, sense circuitry 302 previously described in connection with FIG. 3 .
  • the data state of the selected cell, and the soft data associated therewith can be determined based on the sensed bit line current, as previously described herein (e.g., in connection with FIG. 3 ).
  • the data state and the associated soft data can be determined while the signal represented by waveform 458 is not being provided to transistor 334 (e.g., while the single sensing signal represented by waveforms 453 and 460 steps up or down through the respective voltage levels).
  • the data state and the soft data can be determined from time t 2 to time t 3 , from time t 4 to time t 5 , from time t 6 to time t 7 , and from time t 8 to time t 9 .
  • embodiments of the present disclosure can determine the soft data faster than previous approaches (e.g., approaches that use multiple distinct sense operations using different discrete read voltages to determine the soft data). Accordingly, determining the soft data while the single sensing signal steps up or down through different respective voltage levels in accordance with embodiments of the present disclosure can increase the efficiency and/or performance (e.g., speed) of memory as compared with such previous approaches.
  • Soft data obtained in accordance with embodiments described herein can be used by error detection/correction components (e.g., LDPC) to detect and/or correct errors in a more efficient manner as compared to previous approaches.
  • error detection/correction components e.g., LDPC
  • FIG. 5 illustrates a block diagram of an apparatus in the form of a memory device 570 in accordance with a number of embodiments of the present disclosure.
  • an “apparatus” can refer to, but is not limited to, any of a variety of structures or combinations of structures, such as a circuit or circuitry, a die or dice, a module or modules, a device or devices, or a system or systems, for example.
  • memory device 570 includes a controller 572 and sense circuitry 502 coupled to a memory array 500 .
  • Sense circuitry 502 can be, for example, sense circuitry 302 previously described in connection with FIG. 3 .
  • sense circuitry 302 can determine the data state of a memory cell of memory array 500 , and the soft data (e.g., soft data values) associated therewith, by performing a single sense operation, as previously described herein.
  • Memory array 500 can be, for example, memory array 100 previously described in connection with FIG. 1 . Although one memory array is shown in FIG. 5 , embodiments of the present disclosure are not so limited (e.g., memory device 570 can include more than one memory array coupled to controller 572 ).
  • Controller 572 can include, for example, control circuitry and/or logic (e.g., hardware and/or firmware).
  • controller 572 can include error correction code (ECC) component 574 , as illustrated in FIG. 5 .
  • ECC component 574 can utilize the soft data determined by sense circuitry 302 to correct errors that occur when the data state of the memory cells of memory array 500 are sensed.
  • ECC component 574 can utilize the soft data in a low-density parity-check (LDPC) ECC scheme to correct the errors. That is, ECC component 574 can be an LDPC ECC component.
  • LDPC low-density parity-check
  • Controller 572 can be included on the same physical device (e.g., the same die) as memory array 500 , or can be included on a separate physical device that is communicatively coupled to the physical device that includes memory array 500 .
  • components of controller 572 can be spread across multiple physical devices (e.g., some components on the same die as the array, and some components on a different die, module, or board).
  • Controller 572 can operate sense circuitry 502 to perform sense operations in accordance with a number of embodiments of the present disclosure to determine the data state, and soft data associated therewith, of the memory cells in memory array 500 .
  • controller 572 can operate sense circuitry 502 to determine the soft data values associated with the data state of the cells by performing a single sense operation on the cells in accordance with a number of embodiments of the present disclosure.
  • memory device 570 can include address circuitry to latch address signals provided over I/O connectors through I/O circuitry. Address signals can be received and decoded by a row decoder and a column decoder, to access memory array 500 .

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