US9450546B2 - System, method and device for power amplification of a signal in an integrated circuit - Google Patents

System, method and device for power amplification of a signal in an integrated circuit Download PDF

Info

Publication number
US9450546B2
US9450546B2 US14/165,251 US201414165251A US9450546B2 US 9450546 B2 US9450546 B2 US 9450546B2 US 201414165251 A US201414165251 A US 201414165251A US 9450546 B2 US9450546 B2 US 9450546B2
Authority
US
United States
Prior art keywords
power
primary
power amplifier
winding
primary winding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US14/165,251
Other languages
English (en)
Other versions
US20150214907A1 (en
Inventor
Apu Sivadas
Alok Joshi
Krishnaswamy Thiagarajan
Rakesh Kumar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Priority to US14/165,251 priority Critical patent/US9450546B2/en
Assigned to TEXAS INSTRUMENTS INCORPORATED reassignment TEXAS INSTRUMENTS INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: THIAGARAJAN, KRISHNASWAMY, JOSHI, ALOK, KUMAR, RAKESH, SIVADAS, APU
Priority to JP2016548635A priority patent/JP6741370B2/ja
Priority to CN201580009878.4A priority patent/CN106031029B/zh
Priority to PCT/US2015/013148 priority patent/WO2015113069A1/en
Publication of US20150214907A1 publication Critical patent/US20150214907A1/en
Application granted granted Critical
Publication of US9450546B2 publication Critical patent/US9450546B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/537—A transformer being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/541—Transformer coupled at the output of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/20—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F2203/21—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F2203/211—Indexing scheme relating to power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H03F2203/21145—Output signals are combined by switching a plurality of paralleled power amplifiers to a common output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7221—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the output of the amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7236—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)

Definitions

  • the present disclosure relates generally to amplifying electric and electronic signal and more specifically to a system, method and device for power amplification of a signal.
  • Power of a signal is often amplified to meet certain requirements in an integrated circuit.
  • an integrated circuit is implemented to amplify power of a radio frequency (RF) signal to increase the transmission range.
  • RF radio frequency
  • large size transistors/devices such as complementary metal oxide semiconductor (CMOS) are fabricated to support larger power gain.
  • CMOS complementary metal oxide semiconductor
  • multiple power amplifiers of smaller gain are implemented thereby reducing the size of the transistors. The outputs of the multiple power amplifiers are then combined to achieve the desired power level of the signal.
  • a set of power amplifiers are used to amplify power of a signal for transmission.
  • the signal powers from a set of power amplifiers are coupled to set of primary windings which are commonly coupled to a secondary winding such that the powers on the primary windings are additive in the secondary winding.
  • a current path on the primary windings side is provided for flow of a current that is induced on at least one primary winding by a current flowing in the secondary winding when a power amplifier coupled to that primary winding is in “off” state. As a result, the induced current is prevented from flowing into the power amplifiers that are in “on” state. Further, the current path isolates the power amplifiers from each other thereby enabling the power amplifiers to operate at the rated efficiency.
  • the current path is provided using a resistor network.
  • FIG. 1 is an example environment in which various aspect of the present disclosure are seen.
  • FIG. 2 is a block diagram of an example conventional transmitter device.
  • FIG. 3 is block diagram of an example integrated circuit illustrating the implementation of power amplifier in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an example power combiner in one embodiment of the present disclosure.
  • FIG. 5 is a layout portion of an integrated circuit depicting an example combiner.
  • FIG. 6 is a block diagram illustrating manner in which the power amplifiers are isolated from each other, in one embodiment.
  • FIG. 7 is an example circuit diagram illustrating the manner in which the counter current path may be introduced on the primary winding side providing isolation to the power amplifiers, in one embodiment.
  • FIG. 8A is an example resistor network that may be connected to the combiner 400 for providing the counter current path in the primary windings, in one embodiment.
  • FIG. 8B is an example combiner in one embodiment.
  • FIG. 1 is an example environment in which various aspect of the present disclosure are seen. As shown, the FIG. 1 comprises a transmitting device 110 , communication network 120 , and receiving device 130 . Each block is described in further detail below.
  • the transmitting device 110 is an electronic device/integrated circuit (IC) configured to transmit signals (for example radio frequency signal).
  • the transmitting device 110 comprises frequency multiplier, data encoder, power amplifiers, filters, matching networks and transmit antenna, for example.
  • Various parameters such as the frequency of operation, type of modulation, gain of the power amplifiers and impedance matching etc., are adjusted in the transmitting device 110 meeting/complying to a desired transmission standard.
  • the communication network 120 enables communication between transmitting device 110 and receiving device 130 .
  • the communication network may comprise a radio frequency channel such as VHF, UHF, GSM, CDMA etc., and physical channel such as cable, optical cable etc.
  • the receiving device 130 is an electronic device/IC configured to receive a signal from the communication network 120 .
  • the receiver device 130 may be configured to operate in conjunction with the transmitter device 110 to receive and extract the signal transmitted by the transmitter device 110 .
  • the receiver device 130 may comprise an antenna, tuner, mixer, decoder, radio frequency (RF) receiver, detector, one or more tuned radio frequency amplifiers, etc.
  • the receiving device 130 may employ electronic filters to separate the desired signal (occupying a frequency range) from other signals received by the antenna from the communication network 120 .
  • the receiving device 130 may employ power amplifier to increase the power of the received signal for further processing. The manner in which the power amplifiers and other signal processing elements are implemented in conventional devices is described below.
  • FIG. 2 is a block diagram of an example conventional transmitter device. As shown, the transmitter/transmitting device 201 comprises signal processors 230 and a power amplifier 240 .
  • the signal processer 230 is an IC implemented with a small size devices (transistors, diodes, capacitors etc.,) using corresponding fabrication technology. Signal processer 230 is configured to process the signal at a low power (signal level) and may comprise compressor, expanders, limiters, encoder, modulator up-convertor etc. The processed signal is provided to power amplifier 240 .
  • the power amplifier 240 is an IC configured to amplify the power of the signal received from the signal processor 230 .
  • the power amplifier 240 is constructed with devices (for example, transistors) of large size capable of handling large power/current.
  • the transistors in the power amplifier 240 may be implemented with larger channel width compared to the transistors in the signal processor 230 .
  • the conventional transmitter 201 is implemented with two ICs fabricated using different fabrication techniques. Accordingly, conventional transmitters are not cost effective due to use of multiple ICs/fabrication techniques. Further the gain of the power amplifier may not be substantially varied in the conventional power amplifiers.
  • FIG. 3 is block diagram of an example integrated circuit illustrating the implementation of power amplifier in an embodiment of the present disclosure.
  • the integrated circuit 300 comprises signal processer 310 , power amplifier unit 330 and an antenna 370 . Each block is described below in further detail.
  • the signal processor 310 is configured to process the signal at a low power (signal level) and may comprise compressor, expanders, limiters, encoder, modulator up-convertor etc.
  • the processed signal is provided to power amplifier unit 330 on path 313 .
  • the antenna 370 converts electric power into electromagnetic radiation.
  • the antenna 370 is implemented as part of the integrated circuit 300 .
  • the antenna 370 may represent a load connected to the power combiner 360 .
  • the power amplifier unit 330 amplifies the power of the signal on path 313 by a desired gain factor (gain).
  • the amplified signal is provided to the antenna 370 .
  • the power amplifier unit 330 is shown comprising the power amplifiers 340 A through 340 D and power combiner 360 .
  • Each power amplifier 340 A through 340 D is configured to amplify the power by a fraction of the total desired amplification (gain).
  • gain the total desired amplification
  • each power amplifier 340 A through 340 D is configured to handle a fraction of the overall output power or current on the path 367 .
  • power amplifiers 340 A through 340 D are implemented as complementary metal-oxide-semiconductor (CMOS).
  • CMOS complementary metal-oxide-semiconductor
  • each power amplifier 340 A through 340 D handles only a fraction of the total power required, the amplifiers 340 A through 340 D are implemented using the small size devices. Accordingly, the signal processing unit 310 and the amplifier unit 330 are implemented on a single substrate using same fabrication technology in one IC.
  • the power combiner 360 combines output power of the power amplifiers 340 A through 340 D thereby delivering a signal with a desired power to the antenna 370 .
  • the manner in which the combiner may be implemented on the integrated circuit 300 is further described below.
  • FIG. 4 is a schematic diagram of an example power combiner in one embodiment of the present disclosure.
  • combiner 400 comprises primary windings 410 , 420 , 430 and 440 , and the secondary windings 490 .
  • the primary windings 410 , 420 , 430 and 440 and secondary windings 490 are inductively/electromagnetically coupled (for example, as in case of transformers) to transfer energy (current) in the primary windings 410 , 420 , 430 and 440 to the secondary winding 490 .
  • the windings are arranged such that the energy (current) transferred from each primary winding 410 , 420 , 430 and 440 is additive in the secondary 490 .
  • the output of the each power amplifier 340 A through 340 D is respectively coupled to the primary windings 410 through 440 .
  • the current (power) on each primary winding is proportional to the output power of corresponding power amplifier 340 A through 340 D.
  • the power on the secondary winding 490 is sum of the power (or cumulative addition) of the power transferred to secondary winding 490 from each primary winding 410 through 440 .
  • FIG. 5 is a layout portion of an integrated circuit depicting an example combiner.
  • the square track 510 , 520 , 530 and 540 are conductive tracks etched on one of the metal layer (for example on a metal layer 6 ).
  • the square track 510 , 520 , 530 and 540 represent the primary windings 410 , 420 , 430 and 440 .
  • Each square track 510 , 520 , 530 and 540 has openings (marked “+” and “ ⁇ ”) configured to receive power amplifier outputs.
  • the square track 590 is a conductive track etched on the periphery formed by the square track 510 , 520 , 530 and 540 .
  • the square track 590 represents the secondary winding 490 .
  • the square track 590 may be etched on the redistribution layer (RDL) of the ICT.
  • the square track 590 may operate as RF antenna and radiate the signal, in one embodiment.
  • the primary and the secondary square tracks are inductively/magnetically coupled to each other and transfer energy when the current flows in the primary square track 510 , 520 , 530 and 540 .
  • each primary winding induces the current in the secondary winding 590 that is equal to the current injected by the respective power amplifier.
  • the length of the primary square track 510 through 540 and secondary square track 590 may be adjusted to match impedance level of the power amplifiers 340 A through 340 D.
  • the secondary winding 590 may act as an antenna and may be matched to 50 Ohms impedance, in an embodiment.
  • the total energy transferred to the secondary winding 490 may be controlled by turning off (or turning on) the desired number of power amplifiers.
  • the power amplifier unit 330 is configured to provide a power P when all the power amplifiers are turned on, the power delivered to the antenna (or as output power of the unit 330 ) may be reduced 0.5*P by turning off (or disconnecting the power amplifier from the primary windings) half the number of power amplifiers in the power amplifier unit 330 (in the particular example, two power amplifiers may be turned off).
  • turning some of the power amplifier to “off” state may load the power amplifiers that are in “on” state. Such loading of the power amplifier in “on” state may affect the intended power delivered to the primary by the respective “on” state power amplifiers. Alternately, the “on” state power amplifier may operate at much lower efficiency thus, delivering a power much less than the peak power achievable otherwise. For example, if each power amplifier is configured to deliver 1 ⁇ 4 of the total power (P), then when one of the power amplifiers is turned off, each amplifier may deliver power less than the intended 1 ⁇ 4 P due to the loading.
  • P total power
  • the combiner is configured to provide isolation to the power amplifiers at the primary from each other and thereby deliver substantially the intended power to the corresponding primary when some of the power amplifiers are turned off or disconnected.
  • FIG. 6 is a block diagram illustrating manner in which the power amplifiers are isolated from each other, in one embodiment.
  • the power combiner 360 couples power from a set of power amplifiers to corresponding set of primary windings.
  • the power combiner 360 may receive power in the form of amplified output current or voltage from power amplifiers 340 A through 340 D.
  • the power combiner 360 couples power on the set of primary windings to a secondary winding such that the powers on the primary windings are additive in the secondary winding.
  • the combiner 360 may employ suitable winding ratio. In one embodiment, the ratio is maintained at 1:1 such that substantially a same power on each primary winding is transferred to secondary. For example the current flowing through each of the primary winding 410 through 440 induces a same current in the secondary winding 490 . The induced current adds up in the secondary winding 490 and produces desired high output power at the output terminal of the secondary winding 490 .
  • the power combiner 360 provides a current path on the set of primary windings side for flow of current induced on the at least one primary winding by the current flowing in the secondary winding (for example, 410 through 440 ).
  • the current is induced in the primary when the corresponding power amplifier is in “off” state.
  • the (counter) current path reduces flow of induced counter current into the power amplifier connected to the primary windings.
  • substantially a zero current is made to flow into the power amplifier that is turned off.
  • no (counter) current is flown into the power amplifiers that are in “on” state.
  • the power amplifiers are isolated from each other. The manner in which an alternative current path may be provided is described in further detail below.
  • FIG. 7 is an example circuit diagram illustrating the manner in which the (counter) current path may be introduced on the primary winding side providing isolation to the power amplifiers, in one embodiment.
  • the circuit diagram is shown comprising two primary windings 710 and 720 , and a secondary winding 730 .
  • the isolation resistor 740 is connected between the terminals 711 and 721 of the primary windings 710 and 720 respectively.
  • isolation resistor 750 is connected in between the terminals 712 and 722 of the primary windings 710 and 720 respectively.
  • the terminals 712 and 722 (positive terminals) are configured to receive the current from the two power amplifiers.
  • the terminals 711 and 712 (negative terminals) are configured to provide current return path to the respective power amplifier.
  • the power amplifier connected to the primary winding 720 is turned off. Accordingly, as shown in FIG. 7 , current 780 received on terminal 712 flows through the primary winding 710 . The current flowing through the primary winding 710 induces a current 770 in the secondary winding 730 . The current 770 in the secondary winding 730 induces a voltage or EMF (electromagnetic field) across the primary winding 720 .
  • EMF electromagnettic field
  • the resistors 740 and 750 provide a path enabling the current 790 to flow through the resistor 740 and 750 .
  • the resistors 740 and 750 provide a path enabling the current 790 to flow through the resistor 740 and 750 .
  • the power amplifier connected to the primary winding 710 may experience enhanced loading resulting in the possible operation of the power amplifier at a reduced efficiency.
  • FIG. 8A is an example resistor network that may be connected to the combiner 400 for providing the counter current path in the primary windings, in one embodiment.
  • the FIG. 8A is shown comprising the resistor network 810 comprising resistors 811 through 814 and resistor network 820 comprising 821 through 824 .
  • the resistor network 810 one end of each resistor 811 through 814 is connected to the common terminal 801 and in the resistor network 820 , one end of each resistor 821 through 824 is connected to the common terminal 802 .
  • the other end of the resistors 811 through 814 (marked +) are connected to the positive terminals of the corresponding ones of the primary winding.
  • the other end of the resistors 821 through 824 (marked ⁇ ) are connected to the negative terminals of the corresponding ones of the primary windings.
  • An example connections of the resistor networks 801 and 802 are further illustrated in FIG. 8B .
  • FIG. 8B is an example combiner in one embodiment.
  • the combiner comprises primary windings 840 , 850 , 860 and 870 coupled to the secondary winding 780 .
  • Each primary winding 840 , 850 , 860 and 870 are configured to connect to the corresponding ones of the power amplifiers (for example, 340 A through 340 D) outputs. Thus, combining the power at the secondary 880 .
  • Resistor network 801 comprising resistors 811 through 814 , is connected to the + terminal of each primary winding.
  • resistor network 802 comprising resistors 821 through 824 , is connected to the - terminal of each primary winding.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Amplifiers (AREA)
  • Transmitters (AREA)
US14/165,251 2014-01-27 2014-01-27 System, method and device for power amplification of a signal in an integrated circuit Active 2034-05-12 US9450546B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US14/165,251 US9450546B2 (en) 2014-01-27 2014-01-27 System, method and device for power amplification of a signal in an integrated circuit
JP2016548635A JP6741370B2 (ja) 2014-01-27 2015-01-27 集積回路における信号の電力増幅のためのシステム、方法、及びデバイス
CN201580009878.4A CN106031029B (zh) 2014-01-27 2015-01-27 用于集成电路中的信号的功率放大的系统、方法及装置
PCT/US2015/013148 WO2015113069A1 (en) 2014-01-27 2015-01-27 System, method and device for power amplification of a signal in an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/165,251 US9450546B2 (en) 2014-01-27 2014-01-27 System, method and device for power amplification of a signal in an integrated circuit

Publications (2)

Publication Number Publication Date
US20150214907A1 US20150214907A1 (en) 2015-07-30
US9450546B2 true US9450546B2 (en) 2016-09-20

Family

ID=53680038

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/165,251 Active 2034-05-12 US9450546B2 (en) 2014-01-27 2014-01-27 System, method and device for power amplification of a signal in an integrated circuit

Country Status (4)

Country Link
US (1) US9450546B2 (enExample)
JP (1) JP6741370B2 (enExample)
CN (1) CN106031029B (enExample)
WO (1) WO2015113069A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12482915B2 (en) 2023-04-18 2025-11-25 Apple Inc. Transformer based series Doherty power amplifier

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10128875B1 (en) * 2018-03-30 2018-11-13 Mitsubishi Electric Research Laboratories, Inc. Methods and system of a digital transmitter with reduced quantization noise
WO2022259892A1 (ja) * 2021-06-10 2022-12-15 株式会社村田製作所 増幅回路及び高周波回路
WO2023162655A1 (ja) * 2022-02-24 2023-08-31 株式会社村田製作所 ドハティ増幅回路
WO2025243345A1 (ja) * 2024-05-20 2025-11-27 株式会社ソシオネクスト 出力合成用トランス回路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1189010A (en) 1966-07-29 1970-04-22 Thomson Houston Comp Francaise Improvements in Transistorised Power Amplifiers
RU2117381C1 (ru) 1997-03-12 1998-08-10 Научно-производственное предприятие "Полет" Усилитель мощности радиопередатчика
US6294955B1 (en) 2000-04-07 2001-09-25 Harris Corporation Apparatus and method for use in disconnecting and/or replacing one of a plurality of power amplifiers in a transmitter while the transmitter is operating
US8912865B2 (en) * 2011-04-04 2014-12-16 Samsung Electro-Mechanics Co., Ltd. Power combiner, power amplifying module having the same, and signal transceiving module

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5992608A (ja) * 1982-11-19 1984-05-28 Oki Electric Ind Co Ltd 電力増幅回路
US4965530A (en) * 1989-09-26 1990-10-23 General Electric Company Parallelled amplifier with switched isolation resistors
AU746940B2 (en) * 1998-04-02 2002-05-09 Ericsson Inc. Hybrid chireix/doherty amplifiers power waveform synthesis
GB2439997A (en) * 2006-07-07 2008-01-16 Cambridge Semiconductor Ltd Estimating the output current of a switch mode power supply
US7952433B2 (en) * 2008-11-25 2011-05-31 Samsung Electro-Mechanics Company Power amplifiers with discrete power control
BRPI1011433A2 (pt) * 2009-05-08 2016-03-15 Federal Mogul Ignition Co "circuito amplificador de potência, sistema de ignição corona, e, motor de combustão interna"
JP5459169B2 (ja) * 2010-09-30 2014-04-02 富士通株式会社 増幅回路
US9306502B2 (en) * 2011-05-09 2016-04-05 Qualcomm Incorporated System providing switchable impedance transformer matching for power amplifiers
JP5719259B2 (ja) * 2011-09-06 2015-05-13 ルネサスエレクトロニクス株式会社 高周波電力増幅装置
JP5319006B2 (ja) * 2012-10-10 2013-10-16 ルネサスエレクトロニクス株式会社 電力増幅回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1189010A (en) 1966-07-29 1970-04-22 Thomson Houston Comp Francaise Improvements in Transistorised Power Amplifiers
RU2117381C1 (ru) 1997-03-12 1998-08-10 Научно-производственное предприятие "Полет" Усилитель мощности радиопередатчика
US6294955B1 (en) 2000-04-07 2001-09-25 Harris Corporation Apparatus and method for use in disconnecting and/or replacing one of a plurality of power amplifiers in a transmitter while the transmitter is operating
US8912865B2 (en) * 2011-04-04 2014-12-16 Samsung Electro-Mechanics Co., Ltd. Power combiner, power amplifying module having the same, and signal transceiving module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12482915B2 (en) 2023-04-18 2025-11-25 Apple Inc. Transformer based series Doherty power amplifier

Also Published As

Publication number Publication date
JP6741370B2 (ja) 2020-08-19
CN106031029B (zh) 2019-10-22
JP2017509224A (ja) 2017-03-30
US20150214907A1 (en) 2015-07-30
WO2015113069A1 (en) 2015-07-30
CN106031029A (zh) 2016-10-12

Similar Documents

Publication Publication Date Title
US10536187B2 (en) Complementary metal oxide semiconductor differential antenna transmit-receive switches with power combining circuitry for orthogonal frequency-division multiplexing systems
US10892718B2 (en) Impedance transformation circuit for amplifier
US8031003B2 (en) Solid-state RF power amplifier for radio transmitters
US8570235B2 (en) Systems and methods for complementary metal-oxide-semiconductor (CMOS) differential antenna switches using multi-section impedance transformations
US20170070199A1 (en) Radio frequency circuitr having an integrated harmonic filter and a radio frequency circuit having transistors of different threshold voltages
US9450546B2 (en) System, method and device for power amplification of a signal in an integrated circuit
US12155352B2 (en) Power amplifier arrangement
Lu et al. A self-biased adaptive reconfigurable rectenna for microwave power transmission
CN103916090A (zh) 多绕组变压器耦合的放大器
US20140306780A1 (en) Duplexers
CN111865283B (zh) 具有低泄漏电流和低插入损耗的高功率射频开关
Cho et al. A switchless CMOS bi-directional distributed gain amplifier with multi-octave bandwidth
CN110120790A (zh) 用于多频带毫米波5g通信的宽带功率放大器和匹配网络
EP2356740A1 (en) Method and system for amplifying a signal using a transformer matched transistor
US8145160B2 (en) Tx module for wireless communication
US8198968B2 (en) System and method for multiple band transmission
US8073417B2 (en) Method and system for a transformer-based high performance cross-coupled low noise amplifier
WO2014025714A1 (en) Method and apparatus for a class-e load tuned beamforming 60 ghz transmitter

Legal Events

Date Code Title Description
AS Assignment

Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SIVADAS, APU;JOSHI, ALOK;THIAGARAJAN, KRISHNASWAMY;AND OTHERS;SIGNING DATES FROM 20140120 TO 20140124;REEL/FRAME:032055/0181

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8