US9385716B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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US9385716B2
US9385716B2 US14/569,178 US201414569178A US9385716B2 US 9385716 B2 US9385716 B2 US 9385716B2 US 201414569178 A US201414569178 A US 201414569178A US 9385716 B2 US9385716 B2 US 9385716B2
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latch node
junction region
coupled
gate
drain
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US20160049938A1 (en
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Seong-jin Kim
Sung-Soo Chi
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SK Hynix Inc
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SK Hynix Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails

Definitions

  • Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device including latch circuits.
  • Soft errors occur randomly and may be corrected, unlike hard errors that result in permanent breakdown of devices.
  • Soft errors are caused by alpha particles radiating from radioactive elements such as uranium (U), thorigum (Th) and americium (Am).
  • alpha particles existing in an Epoxy Molding Compound (EMC) may generate a high-energy silicon nucleus through collisions, creating electron-hole pairs that carry charges.
  • EMC Epoxy Molding Compound
  • the electrons cause soft errors by changing or inverting the logic level of logic nodes or memory nodes through diffusion and drift.
  • Soft errors are an important issue in semiconductor memory devices. Thus, memory devices try to fix soft errors through an error detection/correction function using an Error Correction Code (ECC). However, since not all soft errors are corrected by the ECC, efforts are still being made to reduce and repair them. In this application, soft errors will be discussed in the context of logic circuits.
  • Logic circuits store information, and non-limiting examples include flip flops, latches and so on.
  • Exemplary embodiments of the present invention are directed to a semiconductor device that is resistant to soft errors occurring its logic nodes or memory nodes.
  • a semiconductor device includes a first block coupled between a first latch node and a second latch node, a second block suitable for generating common-mode noise between the first latch node and the second latch node, wherein the second block includes a first MOS transistor having a gate coupled with the first latch node, and one between a source and a drain of the first MOS transistor is coupled with the second latch node while the other between the source and the drain is floating.
  • the second block may further include a second MOS transistor having a gate coupled with the first latch node, one between a source and a drain coupled with the second latch node, and the other between the source and the drain floating.
  • the first MOS transistor may include a first PMOS transistor, and the second MOS transistor includes a first NMOS transistor.
  • the first block may include: a second PMOS transistor having a gate coupled with the first latch node, and a source and a drain coupled between a high voltage terminal and the second latch node; and a second NMOS transistor having a gate coupled with the first latch node, and a source and a drain coupled between a low voltage terminal and the second latch node.
  • a semiconductor device in accordance with another embodiment of the present invention, includes a first MOS transistor having a gate coupled with a first latch node, a first junction region coupled with a high voltage terminal and a second junction region coupled with a second latch node, a second MOS transistor having a gate coupled with the first latch node, a third junction region coupled with a low voltage terminal and a fourth junction region coupled with the second latch node, a third MOS transistor sharing the first junction region and having a gate coupled with the second latch node and a fifth junction region coupled with the first latch node, a forth MOS transistor sharing the third junction region and having a gate coupled with the second latch node and a sixth junction region coupled with the first latch node, and a fifth MOS transistor having a gate coupled with the first latch node, a floating seventh junction region, and an eighth junction region coupled with the second latch node.
  • the fifth MOS transistor may share one of the second and fourth junction regions as the eighth junction region.
  • the semiconductor device may further comprising: a first conductive line suitable for electrically connecting the second junction region and the fourth junction region to each other; and a second conductive line suitable for electrically connecting the fifth junction region and the sixth junction region to each other.
  • a semiconductor device includes a first block suitable for supplying a first voltage to a first latch node in response to a reset signal, a second block suitable for supplying a second voltage to the first latch node in response to a clock signal and an input signal, a third block coupled between the first latch node and a second latch node, and a forth block suitable for generating common-mode noise between the first latch node and the second latch node, wherein the forth block may include a first PMOS transistor having a gate coupled with the first latch node, and a source and a drain, one of which is coupled with the second latch node while the other between the source and the drain is floating, and a first NMOS transistor having a gate coupled with the first latch node, and a source and a drain, one of which is coupled with the second latch node while the other between the source and the drain is floating.
  • the first block may include: a second PMOS transistor having a gate for receiving the reset signal, and a source and a drain coupled between a first voltage terminal and the first latch node
  • the second block includes: a second NMOS transistor having a gate for receiving the clock signal, and a source and a drain coupled between a second voltage terminal and a first coupling node; and a third NMOS transistor having a gate for receiving the input signal, and a source and a drain coupled between the first coupling node and the first latch node.
  • the third block may include: a first inversion unit suitable for inverting a voltage level of the first latch node and outputting an inverted voltage level to the second latch node; and a second inversion unit suitable for inverting a voltage level of the second latch node and outputting an inverted voltage level to the first latch node.
  • the first inversion unit includes: a third PMOS transistor having a gate coupled with the first latch node, and a source and a drain coupled between the first voltage terminal and the second latch node; and a fourth NMOS transistor having a gate coupled with the first latch node, and a source and a drain coupled between the second voltage terminal and the second latch node.
  • the second inversion unit may include: a fourth PMOS transistor having a gate for receiving the clock signal, and a source and a drain coupled between the first voltage terminal and a second coupling node; a fifth PMOS transistor having a gate coupled with the second latch node, and a source and a drain coupled between the second coupling node and the first latch node; a fifth NMOS transistor having a gate for receiving a clock bar signal which is an inversion signal of the clock, and a source and a drain coupled between the second voltage terminal and a third coupling node; and a sixth NMOS transistor having a gate coupled with the second latch node, and a source and a drain coupled between the third coupling node and the first latch node.
  • the gate of the second PMOS transistor may be formed between a first junction region and a second junction region, and the gate of the fifth PMOS transistor is formed between the second junction region and a third junction region, and the gate of the fourth PMOS transistor is formed between the third junction region and a fourth junction region, and the gate of the third PMOS transistor is formed between the fourth junction region and a fifth junction region, and the gate of the first PMOS transistor is formed between the fifth junction region and a sixth junction region.
  • the sixth junction region may float.
  • the gate of the second NMOS transistor may be formed between a seventh junction region and an eighth junction region, and the gate of the third NMOS transistor is formed between the eighth junction region and a ninth junction region, and the gate of the sixth NMOS transistor is formed between the ninth junction region and a 10 th junction region, and the gate of the fifth NMOS transistor is formed between the 10 th junction region and an 11 th junction region, and the gate of the fourth NMOS transistor is formed between the 11 th junction region and a 12 th junction region, and the gate of the first NMOS transistor is formed between the 12 th junction region and a 13 th junction region.
  • the 13 th junction region may float.
  • the semiconductor device may further comprising: a first conductive line suitable for electrically connecting the second junction region and the ninth junction region to each other; and a second conductive line suitable for electrically connecting the fifth junction region and the 12 th junction region to each other.
  • a semiconductor device in accordance with another embodiment of the present invention, includes a first block coupled between a first latch node and a second latch node, and a second block suitable for generating common-mode noise between the first latch node and the second latch node, wherein the second block includes a first MOS transistor having a gate coupled with the first latch node, a first floating junction region, and a second junction region coupled with the second latch node.
  • the first block includes: a second MOS transistor having a gate coupled with the first latch node, and a source and a drain coupled between a high voltage terminal and the second latch node; and a third MOS transistor having a gate coupled with the first latch node, and a source and a drain coupled between a low voltage terminal and the second latch node, wherein the first MOS transistor shares the second junction region with one of the drains of the second and third MOS transistors.
  • FIG. 1 is a circuit diagram illustrating a semiconductor device as a comparative example.
  • FIG. 2 is a block diagram illustrating a semiconductor device in accordance with an embodiment of the present invention.
  • FIG. 3 is a circuit diagram exemplarily illustrating an initialization block, a loading block, a latch block and a common coupling block shown in FIG. 2 .
  • FIG. 4 is a layout diagram of the initialization block, the loading block, the latch block and the common coupling block shown in FIG. 3 .
  • connection/coupled refers to one component not only directly coupling another component but also indirectly coupling another component through an intermediate component.
  • a singular form may include a plural form as long as it is not specifically mentioned in a sentence.
  • FIG. 1 is a circuit diagram illustrating a semiconductor device as a comparative example.
  • the semiconductor device 100 may include a latch block 110 coupled between a first latch node LAT and a second latch node LATB and a common coupling block 120 for generating common-mode noise between the first latch node LAT and the second latch node LATB.
  • the latch block 110 may include a first inversion unit 111 coupled between the first latch node LAT and the second latch node LATB and a second inversion unit 113 coupled between the first latch node LAT and the second latch node LATB in the opposite direction to the first inversion unit 111 . That is, the input and output terminals of the first inversion unit 11 are coupled to the output and input terminals of the second inversion unit 113 , respectively. Since the latch block 110 is widely known to those skilled in the art, a detailed description thereon is omitted.
  • the common coupling block 120 protects the latch block 110 from soft error so that logic levels latched in the first latch node LAT or the second latch node LATB are not inverted.
  • the common coupling block 120 may include a capacitor.
  • the latch block 110 may continuously maintain a logic level of the first latch node LAT and a logic level of the second latch node LATB.
  • the latch block 110 may maintain the first latch node LAT in a logic low level and the second latch node LATB in a logic high level, and in contrast, it may maintain the first latch node LAT in a logic high level and the second latch node LATB in a logic low level.
  • the common coupling block 120 may generate common-mode noise between the first latch node LAT and the second latch node LATB. For example, when a voltage level of the first latch node LAT increases due to the noise, the common coupling block 120 may increase a voltage level of the second latch node LATB by the increased voltage level of the first latch node LAT. In other words, the common coupling block 120 reflects noise in the first latch node LAT and the second latch node LATB in common when the noise occurs in one among the first latch node LAT and the second latch node LATB.
  • the common coupling block 120 may maintain the logic levels of the first latch node LAT and the second latch node LATB as they are, without being inverted, although noise occurs in the first latch node LAT or the second latch node LATB.
  • FIG. 2 is a block diagram illustrating a semiconductor device in accordance with an embodiment of the present invention.
  • a latch circuit for latching a predetermined signal is described below as an example in the embodiment.
  • the following embodiment of the semiconductor device uses the same names as the example show in FIG. 1 for corresponding structures.
  • the semiconductor device 200 may include an initialization block 210 , a loading block 220 , a latch block 230 and a second latch node LATB, and a common coupling block 240 .
  • the initialization block 210 supplies a first voltage, e.g., VDD, to a first latch node LAT in response to a reset signal RSTB.
  • the loading block 220 supplies a second voltage, e.g., VSS, to the first latch node LAT in response to a clock signal CLK and an input signal DATA.
  • the latch block 230 is coupled between the first latch node LAT and a second latch node LATB.
  • the common coupling block 240 generates common-mode noise between the first latch node LAT and the second latch node LATB.
  • the latch block 230 may include a first inversion unit 231 for inverting a voltage level of the first latch node LAT and outputting the inverted voltage level to the second latch node LATB and a second inversion unit 233 for inverting a voltage level of the second latch node LATB and outputting the inverted voltage level to the first latch node LAT.
  • FIG. 3 is a circuit, diagram exemplarily illustrating the initialization block 210 , the loading block 220 , the first inversion unit 231 , the second inversion unit 233 , and the common coupling block shown in FIG. 2 .
  • the initialization block 210 may include a first PMOS transistor P 1 having a source and a drain coupled between a first voltage (VDD) terminal and the first latch node LAT and a gate for receiving the reset signal RSTB.
  • the loading block 220 may include a first NMOS transistor N 1 and a second NMOS transistor N 2 .
  • the first NMOS transistor N 1 includes a gate for receiving the input signal DATA and includes a source and a drain that are coupled between a first coupling node COND 1 and the first latch node LAT.
  • the second NMOS transistor N 2 includes a gate for receiving the clock signal CLK and includes a source and a drain that are coupled between a second voltage (VSS) terminal and the first latch node LAT.
  • the first inversion unit 231 may include a second PMOS transistor P 2 and a third NMOS transistor N 3 .
  • the second PMOS transistor P 2 has a gate coupled with the first latch node LAT, a source and a drain coupled between the first voltage (VDD) terminal and the second latch node LATB.
  • the third NMOS transistor N 3 has a gate coupled with the first latch node LAT, and a source and a drain coupled between the second voltage (VSS) terminal and the second latch node LATB.
  • the second inversion unit 233 may include third and fourth PMOS transistors P 3 and P 4 , and fourth and fifth NMOS transistors N 4 and N 5 .
  • the third PMOS transistor P 3 has a gate coupled with the second latch node LATB, and a source and a drain coupled between a second coupling node COND 2 and the first latch node LAT.
  • the fourth PMOS transistor P 4 has a gate for receiving the clock signal CLK, and a source and a drain coupled between the first voltage (VDD) terminal and the second coupling node COND 2
  • the fourth NMOS transistor N 4 has a gate coupled with the second latch node LATB, and a source and a drain coupled between a third coupling node COND 3 and the first latch node LAT.
  • the fifth NMOS transistor N 5 has a gate for receiving a clock bar signal CLKB, which is an inversion signal of the clock signal CLK, and a source and a drain coupled between the second voltage (VSS) terminal and the third coupling node COND 3 .
  • the common coupling block 240 may include a fifth PMOS transistor P 5 and a sixth NMOS transistor N 6 .
  • the fifth PMOS transistor P 5 has a gate coupled with the first latch node LAT, and a source and a drain, one of which is coupled with the second latch node LATB and the other between the source and the drain is floating.
  • the sixth NMOS transistor N 6 has a gate coupled with the first latch node LAT, and a source and a drain, one of which is coupled with the second latch node LATB and the other between the source and the drain is floating.
  • FIG. 4 is a layout diagram of the initialization block 210 , the loading block 220 , the latch block 230 and the common coupling block 240 shown in FIG. 3 .
  • the first to sixth NMOS transistors N 1 to N 6 may be disposed to share their junction regions in a first region NA, and the first to fifth PMOS transistors P 1 to P 5 may be disposed to share their junction regions in a second region PA.
  • the first region NA may include a P-type well region
  • the second region PA may include an N-type well region.
  • the gate of the second NMOS transistor N 2 may be formed between a first junction region coupled with the second voltage (VSS) terminal and a second junction region coupled with the first coupling node COND 1
  • the gate of the first NMOS transistor N 1 may be formed between the second junction region and a third junction region coupled with the first latch node LAT.
  • the gate of the fourth NMOS transistor N 4 may be formed between the third junction region and a fourth junction region coupled with the third coupling node COND 3
  • the gate of the fifth NMOS transistor N 5 may be formed between the fourth junction region and a fifth junction region coupled with the second voltage (VSS) terminal.
  • the gate of the third NMOS transistor N 3 may be formed between the fifth junction region and a sixth junction region coupled with the second latch node LATB and the gate of the sixth NMOS transistor may be formed between the sixth junction region and a floating seventh junction region.
  • the gate of the first PMOS transistor P 1 may be formed between an eighth junction region coupled with the first voltage (VDD) terminal and a ninth junction region coupled with the first latch node LAT.
  • the gate of the third PMOS transistor P 3 may be formed between the ninth junction region and a 10 th junction region coupled with the second coupling node COND 2
  • the gate of the fourth PMOS transistor P 4 may be formed between the 10 th junction region and an 11 th junction region coupled with the first voltage (VDD) terminal.
  • the gate of the second PMOS transistor P 2 may be formed between the 11 th junction region and a 12 th junction region coupled with the second latch node LATB, and the gate of the fifth PMOS transistor P 5 may be formed between the 12 th junction region and a floating 13 th junction region.
  • the third junction region and the ninth junction region may be coupled with each other through a first conductive line L 1
  • the sixth junction region and the 12 th junction region may be coupled with each other through a second conductive line L 2 .
  • the initialization block 210 may supply the first voltage VDD to the first latch node LAT during a section where the reset signal RSTB is of the logic low level.
  • the latch block 230 may latch the first latch node LAT to a logic high level corresponding to the first voltage VDD and the second latch node LATB to a logic low level corresponding to the second voltage VSS.
  • the loading bock 220 may supply the second voltage VSS to the first latch node LAT during a section where the input signal DATA and the clock signal CLK are of a logic high level.
  • the latch block 230 may latch the first latch node LAT to a logic low level corresponding to the second voltage VSS and the second latch node LATB to a logic low level corresponding to the first voltage VDD.
  • the loading block 220 may not supply the second voltage VSS to the first latch node LAT regardless of the clock signal CLK.
  • the latch block 230 may maintain the first latch node LAT in a logic high level and the second latch node LATB in a logic low level.
  • the common coupling block 240 may generate common-mode noise between the first latch node LAT and the second latch node LATB. For example, when a voltage level of the first latch node LAT increases due to the noise, the common coupling block 240 may increase a voltage level of the second latch node LATB by the increased voltage level of the first latch node LAT. Consequently, the logic levels of the first and second latch nodes LAT and LATB may be maintained as they are, without being inverted.
  • Soft errors generally occur in a junction region. However, since one junction region among the source and the drain of the fifth PMOS transistor P 5 and the sixth NMOS transistor N 6 included in the common coupling block 240 floats, the probability a soft error occurring is decreased.
  • the embodiments of the present invention in that they may prevent soft errors from occurring in latch nodes.
  • the operational reliability of a semiconductor device may be improved as tolerance to soft errors occurring in logic nodes or memory nodes is improved.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
US14/569,178 2014-08-14 2014-12-12 Semiconductor device Active 2035-01-09 US9385716B2 (en)

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KR1020140105979A KR20160020790A (ko) 2014-08-14 2014-08-14 반도체 장치
KR10-2014-0105979 2014-08-14

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11069683B2 (en) * 2018-10-05 2021-07-20 Ics Llc Self restoring logic structures

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US5905290A (en) * 1991-06-24 1999-05-18 Texas Instruments Incorporated Single event upset hardened memory cell
US20050156620A1 (en) * 2004-01-15 2005-07-21 Honeywell International Inc. Radiation hardening of logic circuitry using a cross enabled, interlocked logic system and method
US7193447B1 (en) * 2004-05-06 2007-03-20 Sun Microsystems, Inc. Differential sense amplifier latch for high common mode input
US20090134925A1 (en) * 2007-09-19 2009-05-28 International Business Machines Corporation Apparatus and method for hardening latches in soi cmos devices
US20100301914A1 (en) * 2009-06-01 2010-12-02 Sun Microsystems, Inc. Latch with clocked devices
US20110089331A1 (en) * 2009-01-30 2011-04-21 Honywell International Inc. Neutron Detector Cell Efficiency
US20110133781A1 (en) * 2009-12-08 2011-06-09 Qualcomm Incorporated Low power complementary logic latch and rf divider
US8081010B1 (en) * 2009-11-24 2011-12-20 Ics, Llc Self restoring logic
KR20120066754A (ko) 2010-12-15 2012-06-25 에스케이하이닉스 주식회사 반도체 집적 회로 장치
US20140132323A1 (en) * 2012-11-13 2014-05-15 Industrial Technology Research Institute Latch apparatus and applications thereof
US20140177697A1 (en) * 2012-12-21 2014-06-26 Nvidia Corporation Decision feedback equalizer using current mode processing with cmos compatible output level

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US5905290A (en) * 1991-06-24 1999-05-18 Texas Instruments Incorporated Single event upset hardened memory cell
US5536674A (en) * 1992-12-11 1996-07-16 Motorola, Inc. Process for forming a static-random-access memory cell
US5631863A (en) * 1995-02-14 1997-05-20 Honeywell Inc. Random access memory cell resistant to radiation induced upsets
US20050156620A1 (en) * 2004-01-15 2005-07-21 Honeywell International Inc. Radiation hardening of logic circuitry using a cross enabled, interlocked logic system and method
US7193447B1 (en) * 2004-05-06 2007-03-20 Sun Microsystems, Inc. Differential sense amplifier latch for high common mode input
US20090134925A1 (en) * 2007-09-19 2009-05-28 International Business Machines Corporation Apparatus and method for hardening latches in soi cmos devices
US20110089331A1 (en) * 2009-01-30 2011-04-21 Honywell International Inc. Neutron Detector Cell Efficiency
US20100301914A1 (en) * 2009-06-01 2010-12-02 Sun Microsystems, Inc. Latch with clocked devices
US8081010B1 (en) * 2009-11-24 2011-12-20 Ics, Llc Self restoring logic
US20110133781A1 (en) * 2009-12-08 2011-06-09 Qualcomm Incorporated Low power complementary logic latch and rf divider
KR20120066754A (ko) 2010-12-15 2012-06-25 에스케이하이닉스 주식회사 반도체 집적 회로 장치
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US20140177697A1 (en) * 2012-12-21 2014-06-26 Nvidia Corporation Decision feedback equalizer using current mode processing with cmos compatible output level

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US20160049938A1 (en) 2016-02-18

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