US9252305B2 - Photovoltaic device, manufacturing method thereof, and photovoltaic module - Google Patents

Photovoltaic device, manufacturing method thereof, and photovoltaic module Download PDF

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US9252305B2
US9252305B2 US13/979,272 US201213979272A US9252305B2 US 9252305 B2 US9252305 B2 US 9252305B2 US 201213979272 A US201213979272 A US 201213979272A US 9252305 B2 US9252305 B2 US 9252305B2
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diffusion layer
impurity diffusion
surface side
longitudinal direction
grid electrodes
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Satoshi Hamamoto
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02363—Special surface textures of the semiconductor body itself, e.g. textured active layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a photovoltaic device, a manufacturing method thereof, and a photovoltaic module.
  • a photovoltaic device such as a solar battery
  • an impurity diffusion layer (hereinafter, “diffusion layer”) is formed on the surface of a substrate by diffusing impurity opposite in conduction type to the substrate and a PN junction is formed.
  • the photovoltaic power of the photovoltaic device largely depends on the difference in level between conduction types. Accordingly, from the viewpoint of the photovoltaic power, an impurity concentration (a dopant concentration) that determines a conduction level is preferably high.
  • the diffusion layer functions as a part of electrodes for efficiently drawing a generated current to an external circuit. From this viewpoint, the dopant concentration is preferably high.
  • a resistance component gradually increases in a portion in which the electrodes are connected to the PN junction as the photovoltaic device is used for a long time. Accordingly, in the case of additionally considering the long-term reliability, the dopant concentration is preferably high with a view of suppressing the influence of such an increase in the resistance component.
  • silicon semiconductor indicates a higher crystal quality as the impurity concentration present inside the silicon semiconductor is lower.
  • the dopant concentration is too high, the crystal quality as the semiconductor greatly degrades and a recombination rate accelerates, resulting in the reduction in the photovoltaic power. Therefore, when the PN junction is a single junction structure, it is important to set the dopant concentration to an appropriate value while keeping the balance from the three viewpoints mentioned above.
  • PN junction structure is not a single junction structure.
  • a two-stage structure that is, a region near a portion just under each electrode is set as a heavily doped region where the dopant concentration is high and the other region is set as a lightly doped region where the dopant concentration is low (see, for example, Patent Literatures 1 and 2).
  • the heavily doped region near the portion just under each electrode is responsible for a function as a part of the electrode, and the other lightly doped region is responsible for a function of suppressing the degradation in the crystal quality as the semiconductor. That is, it is intended to improve the current-voltage characteristics of a solar battery cell by assigning expected roles mainly to the respective regions.
  • Patent Literature 1 Japanese Patent Application Laid-open No. 2010-186900
  • Patent Literature 2 International Publication Pamphlet No. WO 2009/157052
  • Patent Literature 3 Japanese Patent Application National Publication No. 11-508088
  • Patent Literature 4 Japanese Patent Application Laid-open No. 2005-123447
  • the heavily doped region is set slightly wider so that a positioning margin can be used at the time of forming each electrode.
  • a problem occurs that unnecessary heavily doped region remains and the characteristics do not improve as expected.
  • the problem further worsens that the characteristics do not improve as expected because it is desired to set the concentration of the heavily doped region in direct contact with each electrode to be higher.
  • the present invention has been achieved to solve the above problems, and an object of the present invention is to provide a photovoltaic device that is excellent in its photoelectric conversion efficiency and reliability and that is inexpensive.
  • the present invention is directed to a photovoltaic device that achieves the object.
  • the photovoltaic device includes a silicon substrate of a first conduction type that includes an impurity diffusion layer on one surface side, the impurity diffusion layer having an impurity element of a second conduction type diffused therein; a light-receiving-surface side electrode that includes a plurality of grid electrodes electrically connected to the impurity diffusion layer and arranged parallel at a certain interval on the one surface side of the silicon substrate; and a back-surface side electrode formed on the other surface side of the silicon substrate.
  • the impurity diffusion layer includes a first impurity diffusion layer containing the impurity element at a first concentration and a second impurity diffusion layer containing the impurity element at a second concentration lower than the first concentration.
  • the first impurity diffusion layer is formed so that a direction perpendicular to a longitudinal direction of the grid electrodes in the light-receiving-surface side electrode on the one surface side of the silicon substrate is a longitudinal direction thereof, and so that an area ratio of the first impurity diffusion layer to a band region is equal to or lower than 50%.
  • a width of the band region is uniform and identical to a maximum width of the first impurity diffusion layer in a direction parallel to the longitudinal direction of the grid electrodes.
  • a length of the band region in a longitudinal direction is identical to a length of the first impurity diffusion layer in the longitudinal direction of the first impurity diffusion layer.
  • a pattern of a first impurity diffusion layer is formed into an independent shape without any correlating to a pattern of light-receiving-surface side electrodes. Furthermore, by additionally considering a practical aspect such as a conventional alignment margin, it is possible to form the first impurity diffusion layer having a lower area ratio than a case of forming the pattern of the first impurity diffusion layer to depend on the pattern of the light-receiving-surface side electrodes.
  • the first impurity diffusion layer so that the area ratio of the first impurity diffusion layer is equal to or lower than 50% a band-shaped region having the same width as the maximum width of the pattern of the first impurity diffusion layer, a flow of a generated current from a second impurity diffusion layer to the first impurity diffusion layer and to grid electrodes can be effectively controlled with the low area ratio. Therefore, it is possible to obtain a photovoltaic device having higher photoelectric conversion efficiency.
  • FIG. 1-1 is a cross-sectional view of an example of a manufacturing method of a photovoltaic device according to an embodiment of the present invention.
  • FIG. 1-2 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 1-3 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 1-4 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 1-5 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 1-6 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 1-7 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 1-8 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 1-9 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 1-10 is a cross-sectional view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-1 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-2 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-3 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-4 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-5 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-6 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-7 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-8 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-9 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 2-10 is a perspective view of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention.
  • FIG. 3 is a characteristic diagram of fill factors (initial values) right after producing photovoltaic devices of samples 1 and those of samples 2.
  • FIG. 4 depicts a result of a reliability test conducted on photovoltaic devices of the samples 1 and the samples 2, and is a characteristic diagram of a relation between an elapsed time and a degradation rate of fill factors.
  • FIG. 5 depicts area ratios of a heavily doped n-type diffusion layer to total sheet resistance values in cases of typical combinations of sheet resistance values of the heavily doped n-type diffusion layer and sheet resistance values of a lightly doped n-type diffusion layer, respectively.
  • FIG. 6 is a characteristic diagram of sheet resistance dependencies of an open voltage and a short-circuit current of a silicon solar battery obtained by simulations.
  • FIG. 7 are plan views schematically depicting examples of a pattern of the heavily doped n-type diffusion layer according to the embodiment of the present invention.
  • FIG. 8 depicts area ratios of shapes arranged on a simple lattice depending on short-side and long-side lengths, respectively.
  • FIG. 9 are plan views schematically depicting examples of a pattern of the heavily doped n-type diffusion layer according to the embodiment of the present invention.
  • FIG. 10 depict transitions of a voltage and a current with respect to an area ratio of a heavily doped n-type diffusion layer to an entire n-type diffusion layer in a case where “the sheet resistance of the heavily doped n-type diffusion layer is 20 ⁇ / ⁇ and that of the lightly doped n-type diffusion layer is 90 ⁇ / ⁇ ” in the simulations shown in FIG. 6 .
  • FIGS. 1-1 to 1 - 10 are cross-sectional views of an example of a manufacturing method of a photovoltaic device according to the embodiment of the present invention.
  • FIGS. 2-1 to 2 - 10 are perspective views of an example of the manufacturing method of the photovoltaic device according to the embodiment of the present invention. Processes shown in FIGS. 2-1 to 2 - 10 correspond to those shown in FIGS. 1-1 to 1 - 10 , respectively.
  • p-type silicon substrate 101 a a p-type polycrystalline silicon substrate that is most commonly used for commercial solar batteries is prepared ( FIGS. 1-1 and 2 - 1 ).
  • the p-type silicon substrate 101 a is manufactured by cutting or slicing a monocrystalline silicon ingot or polycrystalline silicon ingot formed by cooling and solidifying molten silicon to wafers that are formed into silicon substrates each at a desired size and a desired thickness by a band saw or a wire saw such as a multi-wire saw. Therefore, damages generated during slicing remain on a surface of the p-type silicon substrate 101 a .
  • the p-type silicon substrate 101 a is immersed in an acid solution or a heated alkaline solution—for example, an aqueous sodium hydroxide and the surface of the p-type silicon substrate 101 a is etched, thereby removing damage regions generated at the time of obtaining silicon substrates by slicing and present near the surface of the p-type silicon substrate 101 a .
  • the p-type silicon substrate 101 a after removing the damages has a thickness of 200 micrometers, for example, and a size of 150 mm ⁇ 150 mm, for example.
  • microscopic irregularities can be formed as a texture structure on a light-receiving-surface side surface of the p-type silicon substrate 101 a .
  • a texture structure By forming such a texture structure on the light-receiving surface side of a semiconductor substrate, it is possible to cause multiple reflection of light on a surface of the photovoltaic device, to efficiently absorb the light incident on the photovoltaic device into a silicon substrate, to effectively reduce reflectivity, and to improve conversion efficiency.
  • the formation method and the shape of the texture structure are not limited to any specific one because the present invention relates to a structure of a diffusion layer of the photovoltaic device.
  • a method using an alkaline aqueous solution containing isopropyl alcohol or acid etching by a mixture solution mainly containing hydrofluoric acid and nitric acid a method of obtaining a honeycomb structure or an inverse-pyramid structure on the surface of the p-type silicon substrate 101 a by forming a mask material in which openings are partially provided on the surface of the p-type silicon substrate 101 a and etching the surface thereof via the mask material, or a method using reactive gas etching (RIE: Reactive Ion Etching) can be adopted.
  • RIE reactive gas etching
  • this p-type silicon substrate 101 a is put into a thermal diffusion furnace and heated in an atmosphere of phosphorus (P) that is an n-type impurity.
  • P phosphorus
  • high-concentration phosphorus (P) is diffused on each surface of the p-type silicon substrate 101 a , a heavily doped n-type impurity diffusion layer (hereinafter, “heavily doped n-type diffusion layer”) 102 a is formed as a first impurity diffusion layer containing the phosphorus at a first concentration, and a semiconductor pn junction is formed ( FIGS. 1-2 and 2 - 2 ).
  • the heavily doped n-type diffusion layer 102 a is formed by heating the p-type silicon substrate 101 a at a temperature of, for example, 850° C. to 900° C. in an atmosphere of phosphorus oxide chloride (POCl 3 ) gas. At this time, a heat treatment is controlled so that a surface sheet resistance of the heavily doped n-type diffusion layer 102 a is, for example, 15 ⁇ / ⁇ to 45 ⁇ / ⁇ , preferably 25 ⁇ / ⁇ to 35 ⁇ / ⁇ . Because a diffusion layer formed by thermal diffusion has a complicated concentration distribution curve, a stereotypical expression such as “concentration ⁇ depth” is virtually meaningless and a sheet resistance is often used as an expression making up for the former expression.
  • etching resistance film 111 a film having an etching resistance property (hereinafter, “etching resistance film”) 111 is formed on the heavily doped n-type diffusion layer 102 a ( FIGS. 1-3 and 2 - 3 ).
  • etching resistance film 111 a silicon nitride film (hereinafter, “SiN film”) having a thickness of 80 nanometers is formed by a plasma CVD (Chemical Vapor Deposition) method.
  • etching resistance film 111 a silicon oxide film (SiO 2 or SiO), a silicon oxynitride film (SiON), an amorphous silicon film (a-Si), a diamond-like carbon film, a resin film or the like can be used as the etching resistance film 111 . While the thickness of the etching resistance film 111 is set to 80 nanometers in the present embodiment, an appropriate thickness can be selected based on texture, etching conditions during etching, and an SiN-film removal performance in a subsequent process.
  • a laser beam is irradiated onto the etching resistance film 111 , thereby forming microscopic openings 112 ( FIGS. 1-4 and 2 - 4 ).
  • the openings 112 are formed in texture-structure forming regions 113 a .
  • the openings 112 are not formed in regions 113 b where the texture structure is not to be formed but the heavily doped n-type diffusion layer 102 a remains.
  • the openings 112 can be formed using processing means other than laser-beam irradiation. Specific examples of such processing means include a photoengraving process and blast processing used in semiconductor processing.
  • the p-type silicon substrate 101 a is wet-etched through the openings 112 ( FIGS. 1-5 and 2 - 5 ). Because the p-type silicon substrate 101 a is etched through the microscopic openings 112 , concave portions 114 are formed at concentric positions to the microscopic openings 112 on one of the surfaces of the p-type silicon substrate 101 a .
  • a mixture solution of the hydrofluoric acid and the nitric acid for example, is used as an etchant.
  • the mixture ratio of the mixture solution can be changed to an appropriate value depending on a desired etching rate and a desired etching shape.
  • the etching is performed without the influence of a crystal face orientation of the surface of the silicon substrate. Therefore, the texture of the same shape can be formed uniformly and the photovoltaic device having a smaller surface reflection loss can be formed.
  • an aqueous solution containing alkaline metal hydroxide such as sodium hydroxide or potassium hydroxide is used only when the p-type silicon substrate 101 a is made of monocrystalline silicon and a slice plane is (100) plane. It is advantageous to perform etching without the influence of the crystal face orientation as described above in a case where the p-type silicon substrate 101 a is made of monocrystalline silicon or polycrystalline silicon and the slice plane is other than the (100) plane.
  • the aqueous solution containing alkaline metal hydroxide because it is relatively easy to process the p-type silicon substrate 101 a into a shape that can further reduce the reflectivity using the etchant for anisotropy.
  • each of the concave portions 114 has an inverse-pyramid shape.
  • the etchant include an etchant obtained by heating 0.5 wt % to 4 wt % of a sodium hydroxide solution at 70° C. to 95° C. and an etchant obtained by adding a surface-active agent to such an aqueous solution.
  • the heavily doped n-type diffusion layer 102 present in the concave portions 114 is simultaneously removed. In the regions 113 b where the heavily doped n-type diffusion layer 102 a remains, the heavily doped n-type diffusion layer 102 a remains as intended. Selection of a pattern (shape and size) of each region 113 b where the heavily doped n-type diffusion layer 102 a remains includes most important elements of the present invention. This selection is described later in detail.
  • the etching resistance film 111 is removed using the hydrofluoric acid ( FIGS. 1-6 and 2 - 6 ).
  • this p-type silicon substrate 101 a is put into the thermal diffusion furnace again and heated in the atmosphere of phosphorus (P) that is the n-type impurity.
  • P phosphorus
  • low-concentration phosphorus (P) is diffused on one of the surfaces of the p-type silicon substrate 101 a , a lightly doped n-type impurity diffusion layer (hereinafter, “lightly doped n-type diffusion layer”) 102 b is formed as a second impurity diffusion layer containing the phosphorus having a second concentration, and a semiconductor pn junction is formed ( FIGS. 1-7 and 2 - 7 ).
  • the second concentration is lower than the first concentration.
  • n-type impurity diffusion layer (hereinafter, “n-type diffusion layer”) 102 constituted by the heavily doped n-type diffusion layer 102 a and the lightly doped n-type diffusion layer 102 b is thereby formed.
  • the heavily doped n-type diffusion layer 102 a is formed by heating the p-type silicon substrate 101 a at a temperature of, for example, about 840° C. in the atmosphere of the phosphorus oxide chloride (POCl 3 ) gas. At this time, a heat treatment is controlled so that a surface sheet resistance of the lightly doped n-type diffusion layer 102 b is 60 ⁇ / ⁇ to 150 ⁇ / ⁇ , for example. Because the diffusion layer formed by the thermal diffusion has a complicated concentration distribution curve, the stereotypical expression such as “concentration ⁇ depth” is virtually meaningless and the sheet resistance is often used as the expression making up for the former expression.
  • the heavily doped n-type diffusion layer 102 a is not removed but remains during the etching. Therefore, even when the low-concentration phosphorus (P) is diffused on the regions 113 b , the heavily doped n-type diffusion layer 102 a remains almost as it stands. Furthermore, in the texture-structure forming regions 113 a , the heavily doped n-type diffusion layer 102 a present in the openings 112 is removed during the etching. Therefore, the lightly doped n-type diffusion layer 102 b is formed on an inner surface of each opening 112 .
  • a method of forming a series of the heavily doped n-type diffusion layer 102 a and the lightly doped n-type impurity diffusion layer 102 b except for the selection of formation patterns (shape and size) has no direct relevance to essential characteristic parts of the present embodiment. Therefore, this method is not limited to any specific one.
  • Examples of cases other than the means described above shown in the present embodiment include a method of selectively forming the heavily doped n-type diffusion layer only in desired regions by locally irradiating a laser beam, applying heat, and further accelerating diffusion after temporarily forming the lightly doped n-type diffusion layer, a method of selectively diffusing the high-concentration phosphorus (P) via exposed portions of the openings in the etching resistance film oppositely to the case described in the present embodiment, and a method of selectively forming each region of the heavily doped n-type diffusion layer and each region of the lightly doped n-type diffusion layer by partially applying diffusion pastes on the silicon substrate.
  • a method of selectively forming the heavily doped n-type diffusion layer only in desired regions by locally irradiating a laser beam, applying heat, and further accelerating diffusion after temporarily forming the lightly doped n-type diffusion layer a method of selectively diffusing the high-concentration phosphorus (P) via exposed portions of the openings in the etching resistance film
  • a phosphorus glass layer mainly containing phosphorus oxide is formed on the surface on which the lightly doped n-type impurity diffusion layer 102 b is formed. Accordingly, the phosphorus glass is removed using a hydrofluoric acid solution or the like.
  • a silicon nitride film (SiN film) is formed as an anti-reflection film 103 on a light-receiving-surface side of the p-type silicon substrate 101 a on which the heavily doped n-type diffusion layer 102 a and the lightly doped n-type impurity diffusion layer 102 b are formed so as to improve photoelectric conversion efficiency ( FIGS. 1-8 and 2 - 8 ).
  • the plasma CVD method is used to form the anti-reflection film 103
  • the silicon nitride film is formed as the anti-reflection film 103 using mixture gas of silane and ammonium.
  • a thickness and a refraction index of the anti-reflection film 103 are set to values at which the anti-reflection film 103 can suppress light reflection most.
  • the anti-reflection film 103 a film of two or more stacked layers having different refraction indexes can be used.
  • another film formation method such as a sputtering method can be used.
  • a silicon oxide film can be formed as the anti-reflection film 103 .
  • FIGS. 1-9 and 2 - 9 the heavily doped n-type diffusion layer 102 a formed on the back surface of the p-type silicon substrate 101 a by the diffusion of phosphorus (P) is removed ( FIGS. 1-9 and 2 - 9 ).
  • a semiconductor substrate 101 in which the p-type silicon substrate 101 a serving as a first conductive layer and the n-type diffusion layer 102 formed on the light-receiving-surface side of the p-type silicon substrate 101 a and serving as a second conductive layer constitute a pn junction is obtained.
  • the heavily doped n-type diffusion layer 102 a formed on the back surface of the p-type silicon substrate 101 a is removed using a single side etching device, for example.
  • a removal method including immersing the entire p-type silicon substrate 101 a in an etchant with the anti-reflection film 103 used as a mask can be adopted.
  • the etchant an etchant obtained by heating the alkaline aqueous solution such as the sodium hydroxide solution or a potassium hydroxide solution at a room temperature to 95° C., preferably 50° C. to 70° C. is used.
  • a mixture aqueous solution of nitric acid and hydrofluoric acid can be used as the etchant.
  • light-receiving-surface side electrodes and a back-surface side electrode are formed.
  • an aluminum-mixed electrode material paste for formation of the back-surface side electrode is applied onto the entire back surface of the semiconductor substrate 101 by screen printing, and the paste is then dried.
  • a silver-mixed electrode material paste for formation of the light-receiving-surface side electrodes is applied onto the anti-reflection film 103 that is a light-receiving surface of the semiconductor substrate 101 into a comb shape by the screen printing, and the paste is then dried.
  • the electrode material paste for the light-receiving-surface side electrodes is applied onto the texture-structure forming regions 113 a.
  • the electrode material pastes on light-receiving surface side and the back surface side of the semiconductor substrate 101 are simultaneously burned in, for example, an atmospheric atmosphere at a temperature of about 760° C., thereby obtaining light-receiving-surface side electrodes 105 and a back-surface side electrode 104 ( FIGS. 1-10 and 2 - 10 ).
  • a silver material contacts silicon and is re-solidified while the anti-reflection film 103 is molten with glass contained in the paste.
  • the light-receiving-surface side electrodes 105 are formed in the texture-structure forming regions 113 a . That is, the light-receiving-surface side electrodes 105 are formed on the lightly doped n-type diffusion layer 102 b .
  • a comb-shaped configuration is constituted by a plurality of thin and long grid electrodes arranged in parallel in a predetermined direction at a certain interval and a plurality of bus electrodes.
  • the grid electrodes are locally provided on the light-receiving surface so as to collect electric power generated in the semiconductor substrate 101 .
  • the bus electrodes are provided to be nearly orthogonal to the grid electrodes so as to draw the electric power collected by the grid electrodes.
  • the grid electrodes and the bus electrodes are electrically connected to the n-type diffusion layer 102 on bottoms thereof.
  • the photovoltaic device according to the present embodiment is manufactured.
  • the heavily doped n-type diffusion layer basically remains in light-receiving-surface-side-electrode forming regions.
  • the reason is as follows.
  • the light-receiving-surface side electrodes are formed on the lightly doped n-type diffusion layer, it is conventionally considered that a component of a contact resistance between the light-receiving-surface side electrodes and the diffusion layer and that of a series resistance due to a concentrated current increase and this causes a deterioration in a fill factor and makes the fill factor unstable.
  • the present inventors actually produced, as prototypes, a plurality of photovoltaic devices as samples 1 each having a conventional configuration in which the light-receiving-surface side electrodes were formed in the regions where the heavily doped n-type diffusion layer remained (“heavily doped n-type diffusion layer regions”) and a plurality of photovoltaic devices as samples 2 each having a configuration in which the light-receiving-surface side electrodes were formed to be deviated from the heavily doped n-type diffusion layer regions.
  • the samples 1 and 2 were configured in the same conditions except for different formation positions of the light-receiving-surface side electrodes. Furthermore, an area ratio of the heavily doped n-type diffusion layer regions to the entire light-receiving surface is 20%.
  • the present inventors evaluated characteristics of the photovoltaic devices of the samples 1 and the samples 2.
  • FIG. 3 is a characteristic diagram of fill factors (initial values) right after producing photovoltaic devices of the samples 1 and those of the samples 2.
  • FIG. 4 depicts a result of a reliability test conducted on photovoltaic devices of the samples 1 and the samples 2, and is a characteristic diagram of a relation between an elapsed time and a degradation rate of fill factors (FF).
  • the degradation rate of each of the fill factors (FF) shown in FIG. 4 is obtained by dividing the photoelectric conversion efficiency of each photovoltaic device after the reliability test by the photoelectric conversion efficiency of the photovoltaic device before the reliability test.
  • a region ratio of the heavily doped n-type diffusion layer 102 a according to the present invention is set to be lower than that of the heavily doped n-type diffusion layer including the margin according to conventional techniques, it is possible to suppress the adverse effect of the heavily doped n-type diffusion layer on the current, that is, a decrease in the current to be lower than an intended current and possible to improve the characteristics.
  • a total sheet resistance value R total of the n-type diffusion layer is expressed by the following equation (1).
  • the area ratio r of the heavily doped n-type diffusion layer is expressed by the following equation (2).
  • the total sheet resistance value R total of the light-receiving surface is preferably 50 ⁇ / ⁇ to 70 ⁇ / ⁇ , more preferably 55 ⁇ / ⁇ to 65 ⁇ / ⁇ . Even in a case of a double PN junction structure as shown in the photovoltaic device according to the present embodiment, the total sheet resistance value R total is preferably in the above range.
  • the value R total is lower than 50 ⁇ / ⁇ (the dopant concentration is too high), then the crystal quality as the semiconductor degrades greatly and a recombination rate accelerates. As a result, the power is not efficiently generated in the silicon and the photovoltaic power falls.
  • the value R total is higher than 70 ⁇ / ⁇ (the dopant concentration is too low)
  • the power generated in the silicon cannot be efficiently drawn outside.
  • the photovoltaic power falls.
  • the probability of the degradation in the long-term reliability due to the increase in the resistance component of the portions in which the electrodes are connected to the PN junction rises. Therefore, by setting the total sheet resistance value R total of the light-receiving surface to fall in the range from 55 ⁇ / ⁇ to 65 ⁇ / ⁇ , it is possible to keep more satisfactory balance among the crystal quality as the semiconductor, a photovoltaic amount resulting from the level difference between the PN junctions, and the long-term reliability, and possible to obtain better characteristics.
  • FIG. 5 depicts area ratios r of a heavily doped n-type diffusion layer to the total sheet resistance values R total in cases of typical combinations of sheet resistance values R 1 of the heavily doped n-type diffusion layer and sheet resistance values R 2 of the lightly doped n-type diffusion layer, respectively.
  • FIG. 5 depicts the area ratios r of the heavily doped n-type diffusion layer to correspond to each of four types of the R total : 50 ⁇ / ⁇ , 55 ⁇ / ⁇ , 65 ⁇ / ⁇ , and 70 ⁇ / ⁇ .
  • By controlling the area ratio r of the heavily doped n-type diffusion layer to fall in such ranges it is possible to realize the photovoltaic device having a good fill factor (FF).
  • FF good fill factor
  • the area ratio r of the conventional typical heavily doped n-type diffusion layer is 20%.
  • the combination of the R 1 and the R 2 is selected so that the area ratio r of the heavily doped n-type diffusion layer 102 a falls below 20%, the adverse effect of the heavily doped n-type diffusion layer on the current, that is, the decrease in the current to be lower than the intended current can be suppressed and the characteristics can improve.
  • the area ratio r of the heavily doped n-type diffusion layer 102 a is more preferably equal to or lower than 10%.
  • a current component generated particularly in the lightly doped n-type diffusion layer flows first from a generation point to the closest heavily doped n-type diffusion layer at a shortest distance and then reaches the grid electrodes along the shape of the heavily doped n-type diffusion layer.
  • a resistance value generated up to the grid electrode at each point correlates to a numerical value represented by “(Sheet resistance of lightly doped n-type diffusion layer) ⁇ (Total path length of lightly doped n-type diffusion layer)+(Sheet resistance of heavily doped n-type diffusion layer) ⁇ (Total path length of heavily doped n-type diffusion layer)”. It is important to set the shape of the heavily doped n-type diffusion layer 102 a that can suppress the above numerical value to be small with a lower area ratio.
  • the heavily doped n-type diffusion layer does not necessarily contact the grid electrodes. Even when the heavily doped n-type diffusion layer does not contact the grid electrodes, the logic described above is applicable. In this case, the current component reaches the grid electrodes after passing through respective paths of the heavily doped n-type diffusion layer and the lightly doped n-type diffusion layer so that the sum of the formula mentioned above becomes a minimum value.
  • a shape of the pattern perpendicular to the grid electrodes in the plane of the light-receiving surface of the photovoltaic device has a directionality of allowing the generated current component to be close to the grid electrodes at the shortest distance, and is effective to more efficiently introduce the generated current to the grid electrodes.
  • a component in parallel to the grid electrodes does not allow the generated current to be close to the grid electrodes while the generated current passes through the directional component, and lacks effectiveness for more efficiently introducing the generated current to the grid electrodes even in a heavily doped n-type diffusion layer (a low sheet resistance region).
  • FIG. 6 is a characteristic diagram of sheet resistance dependencies (relative values) of an open voltage (Voc) and a short-circuit current (Isc) of a silicon solar battery obtained by simulations in the same conditions except for the total sheet resistance of the n-type diffusion layer on the light-receiving surface.
  • FIG. 6 depicts the sheet resistance dependencies based on a case where the total sheet resistance of the n-type diffusion layer is 90 ⁇ / ⁇ (with this case set to 100%).
  • the crystal quality as the semiconductor degrades and the recombination rate accelerates as the sheet resistance decreases (the impurity concentration increases).
  • the photovoltaic power falls and both the Voc and the Isc decrease.
  • the decreases are particularly noticeable in a range equal to or lower than 40 ⁇ / ⁇ which range is effective as that for the heavily doped n-type diffusion layer.
  • the heavily doped n-type diffusion layer has a simple linear or stripe shape
  • means for suppressing the area ratio is limited to narrowing the width.
  • inexpensive processing means such as a product made in bulk is supposed to be used
  • the probability increases that the heavily doped n-type diffusion layer cannot be processed as desired because it is necessary to consider the size accuracy and processing limit, and that the area ratio of the heavily doped n-type diffusion layer cannot be suppressed. Therefore, it is important to further elaborately set the shape so as to be able to effectively suppress the area ratio of the heavily doped n-type diffusion layer at a size at which it is relatively easy to process the heavily doped n-type diffusion layer.
  • Examples of a method of effectively suppressing the area ratio of the heavily doped n-type diffusion layer using almost the same size include adoption of an intermittent pattern such as a dot pattern as the shape of the heavily doped n-type diffusion layer. For example, a stripe region where stripes each having a width of 0.1 millimeter are arranged at an interval of 1 millimeter is formed so that the area ratio stripe region to a predetermined region becomes 10%.
  • a stripe region where stripes each having a width of 0.1 millimeter are arranged at an interval of 1 millimeter is formed so that the area ratio stripe region to a predetermined region becomes 10%.
  • 1-mm square dots simple lattice
  • the area ratio of the stripe region to the predetermined region is 10%
  • the area ratio of the square dot (simple lattice) region to the predetermined region is about 1% and it is possible to reduce the area ratio more conspicuously.
  • FIG. 7 are plan views schematically depicting examples of a pattern of the heavily doped n-type diffusion layer 102 a according to the present embodiment.
  • FIG. 7( a ) is an example of a rectangular pattern of the heavily doped n-type diffusion layer 102 a
  • FIG. 7( a ) is an example of a rectangular pattern of the heavily doped n-type diffusion layer 102 a
  • FIG. 7( a ) is an example of a rectangular pattern of the heavily doped n-type diffusion layer 102 a
  • FIG. 7( a ) is an example of a rectangular pattern of the heavily doped n-type diffusion layer 102 a
  • FIG. 7( b ) is an example of an elliptical pattern of the heavily doped n-type diffusion layer 102 a
  • FIG. 7( c ) is an example of a diamond pattern of the heavily doped n-type diffusion layer 102 a
  • an arrow X indicates a longitudinal direction (an extending direction) of the grid electrodes
  • an arrow Y indicates the direction perpendicular to the longitudinal direction of the grid electrodes.
  • a dashed line indicates a stripe (band) shape having the same width as a short-side maximum width of the heavily doped n-type diffusion layer 102 a as a uniform width
  • a dashed-dotted line indicates a center line of the stripe (band) shape.
  • FIG. 8 depicts area ratios of shapes arranged on a simple lattice depending on short-side and long-side lengths, respectively.
  • FIG. 8 depicts the area ratios of the shapes to the lattice region when the rectangular, elliptical, and diamond shapes each having the short-side length of 0.1 millimeter and the long-side length of 0.1 ⁇ N mm are arranged on the simple lattice, respectively.
  • the area ratios can be effectively suppressed as compared with the stripes having the same short-side size. Particularly, the effect of reducing the area ratio is considerable when N ⁇ 5.
  • any structure is appropriate for the object as long as the area ratio is lower than that of the heavily doped n-type diffusion layer 102 a of the stripe shape having the same width as the short-side length of the shape.
  • the area ratio of the heavily doped n-type diffusion layer 102 a of the shape equal to or lower than 50% of that of the heavily doped n-type diffusion layer 102 a of the stripe (band) shape having the same width as the shorter-side maximum width of each of the above shapes as the uniform width is preferable in view of a considerable effect of reducing the area ratio.
  • the current directly gains the decreasing effect and an inverse of the voltage directly gains the decreasing effect almost in proportion to the area ratio of the heavily doped n-type diffusion layer current.
  • the higher area ratio of the heavily doped n-type diffusion layer has a greater adverse effect on the current and the voltage. Therefore, it is preferable to reduce the area ratio of the heavily doped n-type diffusion layer as much as possible.
  • the length of the stripe (band) shape in the longitudinal direction is assumed to be equal to the entire length of the pattern in which the heavily doped n-type diffusion layer of each of the above shapes is arranged in the longitudinal direction. It is also preferable that a size ratio of the long side to the short side of each of the shapes falls in a range from 1 to 5. When this size ratio is lower than 1, the side is not called the long side and the component in parallel to the longitudinal direction of the grid electrodes increases. Therefore, the shape having such size ratio is not appropriate for the object of the present embodiment. When the size exceeds 5, it cannot be said that the reduction effect of the area ratio is conspicuous although it depends on the shape.
  • a lower limit value of the area ratio of the heavily doped n-type diffusion layer to the stripe (band) shape having the same width as the short-side maximum width of each of the above shapes as the uniform width can be proposed as follows as an example from the viewpoint of the processing limit although the lower limit value is not limited to any specific one from the viewpoint of functions.
  • FIG. 9 are plan views schematically depicting examples of the pattern of the heavily doped n-type diffusion layer 102 a according to the present embodiment.
  • FIG. 9( a ) is an example of the pattern of the heavily doped n-type diffusion layer 102 a in which an almost identical shape continuous in the direction perpendicular to the longitudinal direction of the grid electrodes and having changing widths is repeated almost regularly.
  • FIG. 9( a ) is an example of the pattern of the heavily doped n-type diffusion layer 102 a in which an almost identical shape continuous in the direction perpendicular to the longitudinal direction of the grid electrodes and having changing widths is repeated almost regularly.
  • FIG. 9( b ) is an example of the pattern of the heavily doped n-type diffusion layer 102 a in which irregular shapes are continuous in the direction perpendicular to the longitudinal direction of the grid electrodes and have changing widths.
  • the arrow X indicates a longitudinal direction (an extending direction) of the grid electrodes and the arrow Y indicates the direction perpendicular to the longitudinal direction (an extending direction) of the grid electrodes.
  • the dashed line indicates the stripe (band) shape having the width that is the same width as the short-side maximum width of the heavily doped n-type diffusion layer 102 a as the uniform width
  • the dashed-dotted line indicates the center line of the stripe (band) shape.
  • the area ratio of the heavily doped n-type diffusion layer 102 a of this shape is preferably equal to or lower than 50% of that of the stripe (band) shape having the uniform width in view of the considerable effect of reducing the area ratio.
  • the error angle ⁇ is expressed by ⁇
  • the error angle ⁇ according to the idea of keeping giving a higher priority to the component of the heavily doped n-type diffusion layer perpendicular to the longitudinal direction of the grid electrodes than the parallel component is appropriate for the object of the present invention similarly to the above cases. That is, when the component perpendicular to the longitudinal direction of the gird electrodes is assumed as the longitudinal component of the heavily doped n-type diffusion layer, the error angle ⁇ in the following range is appropriate for the object of the present embodiment.
  • the shape of the heavily doped n-type diffusion layer is continuous or intermittent, detailed positions are not limited to any specific one. Nevertheless, it is preferable that the detailed shapes have repeatability from the viewpoints of the manufacturing easiness and a cost reduction. Furthermore, to expect uniformity and stability of the characteristics, it is preferable that an integer multiple of the grid electrode interval matches that of the repetitive interval and that this integer multiple is equal to or greater than 1 and equal to or smaller than 20. A case where the integer multiple exceeds 20 corresponds to repetitive pitches equal to or smaller than 1 millimeter in a case of, for example, the grid electrode interval of 2 millimeters. In this case, more restrictions are given to a specific manufacturing method, so that the integer multiple exceeding 20 is unfavorable from the viewpoint of a cost reduction although not being particularly inappropriate for the original object of the present embodiment.
  • typical examples of the shape having the repeatability include a shape formed along lattice intersections particularly in the case of the intermittent shape.
  • the heavily doped n-type diffusion layer is arranged to correspond to intersections of a square lattice or a hexagonal lattice.
  • FIG. 10 depict transitions of a voltage and a current with respect to an area ratio of a heavily doped n-type diffusion layer to an entire n-type diffusion layer in a case where “the sheet resistance of the heavily doped n-type diffusion layer is 20 ⁇ / ⁇ and that of the lightly doped n-type diffusion layer is 90 ⁇ / ⁇ ” in the simulations shown in FIG. 6 .
  • FIG. 10( a ) depicts a transition of a voltage in a simulation.
  • FIG. 10( b ) depicts a transition of a current in a simulation.
  • an area ratio A indicates the area ratio of the heavily doped n-type diffusion layer to the entire n-type diffusion layer.
  • FIGS. 10( a ) and 10 ( b ) an area ratio A indicates the area ratio of the heavily doped n-type diffusion layer to the entire n-type diffusion layer.
  • an area ratio B indicates a relative area ratio of the heavily doped n-type diffusion layer of each target shape according to the present embodiment based on the case where the area ratio A to the entire cells of the “band-shaped heavily doped n-type diffusion layer” serving as the comparison target mentioned above (the entire n-type diffusion layer) is 20% (with this case set to 100%).
  • the voltage and the current are calculated while assuming that calculated values of the voltage and the current in a case where the entire n-type diffusion layer is 90 ⁇ / ⁇ are 100%.
  • the area ratio A of the heavily doped n-type diffusion layer can be suppressed to be equal to or lower than 10%, decreasing rates of the voltage and the current can be kept within 0.5%.
  • the voltage unlike the current the decreasing rate of which can be sufficiently suppressed by an electrode area or the like, it is difficult to suppress the decreasing rate of the voltage by the other elements and even a difference smaller than 1% in a relative ratio is not negligible for the improvement in efficiency.
  • the area ratio r of the conventional typical heavily doped n-type diffusion layer is 20%, and it is possible to suppress the adverse effect of the heavily doped n-type diffusion layer on the current when the area ratio r of the heavily doped n-type diffusion layer 102 a falls below 20%, that is, the decrease in the current to be lower than the intended current and possible to improve the characteristics.
  • the area ratio r of the heavily doped n-type diffusion layer is set to or lower than 10% that is a half of 20%, the effect of improving the characteristics is conspicuous.
  • the patterns (shape and size) of the heavily doped n-type diffusion layer 102 a and the lightly doped n-type diffusion layer 102 b formed on the light-receiving surface side of the semiconductor substrate 101 in the photovoltaic device are formed as independent patterns (shape and size) without depending on and correlating to the pattern (shape and size) of the light-receiving-surface side electrodes 105 that are also formed on the light-receiving surface side.
  • This can facilitate controlling the patterns of the heavily doped n-type diffusion layer 102 a and the lightly doped n-type diffusion layer 102 b and makes it possible to manufacture the photovoltaic device at a low cost and at a high yield.
  • the area ratio of the heavily doped n-type diffusion layer 102 a can be suppressed to be lower than the area ratio in the case of making the pattern (shape and size) of the heavily doped n-type diffusion layer 102 a dependent on that of the light-receiving-surface side electrodes 105 as the practical aspect.
  • the generated current can be effectively introduced to the grid electrodes with the low area ratio.
  • the generated current can be effectively introduced to the grid electrodes with the low area ratio. According to the present embodiment, these effects make it possible to achieve the photovoltaic device having the high photoelectric conversion efficiency.
  • the substrate thickness is 200 micrometers
  • a substrate made thinner down to, for example, about 50 micrometers can be similarly used as long as self-holding of the substrate can be ensured.
  • the substrate size is 150 mm ⁇ 150 mm, it is needless to mention that similar effects can be obtained whether the substrate size is larger or smaller than 150 mm ⁇ 150 mm.
  • a photovoltaic module having a high light confinement effect, excellent reliability, and excellent photoelectric conversion efficiency can be realized by arranging a plurality of photovoltaic devices configured as described in the present embodiment and electrically connecting the adjacent photovoltaic devices either in series or in parallel. In this case, it suffices to electrically connect the light-receiving-surface side electrodes of one of the adjacent photovoltaic devices to the back-surface side electrode of the other photovoltaic device. Furthermore, a laminate process for covering and laminating these photovoltaic devices with an insulating layer is performed. As a result, the photovoltaic module constituted by a plurality of photovoltaic devices is manufactured.
  • the photovoltaic device according to the present invention is useful for realizing a photovoltaic device that is excellent in its photoelectric conversion efficiency and reliability and that is inexpensive.
  • n-type impurity diffusion layer heavily doped n-type impurity diffusion layer (heavily doped n-type diffusion layer)
  • lightly doped n-type impurity diffusion layer lightly doped n-type diffusion layer

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US20230402552A1 (en) * 2022-06-10 2023-12-14 Zhejiang Jinko Solar Co., Ltd. Solar cell and production method thereof, photovoltaic module

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JP5777798B2 (ja) * 2012-03-12 2015-09-09 三菱電機株式会社 太陽電池セルの製造方法
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19522539A1 (de) 1995-06-21 1997-01-02 Fraunhofer Ges Forschung Solarzelle mit einem, eine Oberflächentextur aufweisenden Emitter sowie Verfahren zur Herstellung derselben
JP2005123447A (ja) 2003-10-17 2005-05-12 Shin Etsu Handotai Co Ltd 太陽電池及びその製造方法
US20050109388A1 (en) * 2003-11-05 2005-05-26 Canon Kabushiki Kaisha Photovoltaic device and manufacturing method thereof
DE102006057328A1 (de) 2006-12-05 2008-06-12 Q-Cells Ag Solarzelle mit Dielektrikumschichtenfolge, länglichen Kontaktregionen und quer dazu verlaufenden Metallkontakten sowie Herstellungsverfahren für diese
US20080264473A1 (en) * 2007-04-30 2008-10-30 Brian Cumpston Volume compensation within a photovoltaic device
US20080271777A1 (en) * 2005-12-30 2008-11-06 Paul Stoner Method and apparatus for eye-safe transmittal of electrical power in vehicles using white light via plastic optical fiber
WO2009157052A1 (ja) 2008-06-23 2009-12-30 三菱電機株式会社 光起電力装置の製造方法
JP2010186900A (ja) 2009-02-13 2010-08-26 Shin-Etsu Chemical Co Ltd 太陽電池及びその製造方法
US20110139236A1 (en) * 2010-04-26 2011-06-16 Kyoungsoo Lee Solar cell and method for manufacturing the same
US20110139226A1 (en) * 2010-04-02 2011-06-16 Jungmin Ha Selective emitter solar cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2732524B2 (ja) * 1987-07-08 1998-03-30 株式会社日立製作所 光電変換デバイス
JP4393938B2 (ja) * 2004-07-16 2010-01-06 信越化学工業株式会社 電極材料及び太陽電池、並びに太陽電池の製造方法
CN101101936A (zh) * 2007-07-10 2008-01-09 中电电气（南京）光伏有限公司 选择性发射结晶体硅太阳电池的制备方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19522539A1 (de) 1995-06-21 1997-01-02 Fraunhofer Ges Forschung Solarzelle mit einem, eine Oberflächentextur aufweisenden Emitter sowie Verfahren zur Herstellung derselben
JPH11508088A (ja) 1995-06-21 1999-07-13 フラウンホファー．ゲゼルシャフト．ツール．フォルデンウング．デール．アンゲヴァンドテン．フォルシュング．エー．ファウ 表面織目模様の放射層を有する太陽電池
US6147297A (en) 1995-06-21 2000-11-14 Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forschung E.V. Solar cell having an emitter provided with a surface texture and a process for the fabrication thereof
JP2005123447A (ja) 2003-10-17 2005-05-12 Shin Etsu Handotai Co Ltd 太陽電池及びその製造方法
US20050109388A1 (en) * 2003-11-05 2005-05-26 Canon Kabushiki Kaisha Photovoltaic device and manufacturing method thereof
US20080271777A1 (en) * 2005-12-30 2008-11-06 Paul Stoner Method and apparatus for eye-safe transmittal of electrical power in vehicles using white light via plastic optical fiber
DE102006057328A1 (de) 2006-12-05 2008-06-12 Q-Cells Ag Solarzelle mit Dielektrikumschichtenfolge, länglichen Kontaktregionen und quer dazu verlaufenden Metallkontakten sowie Herstellungsverfahren für diese
US20080264473A1 (en) * 2007-04-30 2008-10-30 Brian Cumpston Volume compensation within a photovoltaic device
WO2009157052A1 (ja) 2008-06-23 2009-12-30 三菱電機株式会社 光起電力装置の製造方法
JP2010186900A (ja) 2009-02-13 2010-08-26 Shin-Etsu Chemical Co Ltd 太陽電池及びその製造方法
US20110139226A1 (en) * 2010-04-02 2011-06-16 Jungmin Ha Selective emitter solar cell
US20110139236A1 (en) * 2010-04-26 2011-06-16 Kyoungsoo Lee Solar cell and method for manufacturing the same

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
International Search Report (PCT/ISA/210) issued on Mar. 27, 2012, by the Japanese Patent Office as the International Searching Authority for International Application No. PCT/JP2012/055450.
Niinobe et al., "Honeycomb-Structured Multi-Crystalline Silicon Solar Cells with 18.6% Efficiency via Industrially Applicable Laser Process", 23rd European Photovoltaic Solar Energy Conference, Sep. 2008, pp. 1824-1828.
Notification of the First Office Action issued Apr. 20, 2015 by the Chinese Patent Office in corresponding Chinese Application No. 201280007788.8, and an English translation thereof (12 pages).
Office Action (Notice of Rejection) issued on Mar. 4, 2014, by the Japanese Patent Office in corresponding Japanese Patent Application No. 2013-502429, and an English Translation of the Office Action. (4 pages).
Office Action issued May 7, 2015 by the German Office Action in corresponding German Application No. 11 2012 001 067.1, and an English translation thereof (18 pages).
Written Opinion (PCT/ISA/237) issued on Mar. 27, 2012, by the Japanese Patent Office as the International Searching Authority for International Application No. PCT/JP2012/055450.

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230402552A1 (en) * 2022-06-10 2023-12-14 Zhejiang Jinko Solar Co., Ltd. Solar cell and production method thereof, photovoltaic module
US11887844B2 (en) * 2022-06-10 2024-01-30 Zhejiang Jinko Solar Co., Ltd. Solar cell and production method thereof, photovoltaic module

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