US9230923B2 - Electronic chip with means of protecting its back face - Google Patents

Electronic chip with means of protecting its back face Download PDF

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US9230923B2
US9230923B2 US14/510,525 US201414510525A US9230923B2 US 9230923 B2 US9230923 B2 US 9230923B2 US 201414510525 A US201414510525 A US 201414510525A US 9230923 B2 US9230923 B2 US 9230923B2
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electrically conducting
substrate
electronic circuit
vias
back face
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US20150108606A1 (en
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Yann Lamy
Alain Merle
Guy-Michel Parat
Assia Tria
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/576—Protection from inspection, reverse engineering or tampering using active circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0651—Function
    • H01L2224/06515—Bonding areas having different functions
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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    • H01L2924/19042—Component type being an inductor
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
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    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
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    • H01L2924/30105—Capacitance
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    • H01L2924/30107—Inductance

Definitions

  • This application relates to the field of security and protection of electronic chips and relates to means of preventing access to data stored in the electronic circuit of an electronic chip from its back face.
  • the invention is applicable to all types of electronic chips including mobile telephony chip, bank card, health card, etc.
  • the first is to acquire or retrieve internal information manipulated by the electronic circuit in the chip (observation of electrical consumption of the circuit, electromagnetic radiation generated by the circuit, circuit probing, in other words physically accessing the circuit by setting up an electrical connection with a track internal to the circuit, contactless probing of an internal track, etc.)
  • the second consists of injecting faults (changing the state of a bit or a group of bits by injection of light, laser, electromagnetic radiation, etc.) during a calculation performed by the electronic circuit of the chip.
  • a combination of these different techniques is very frequently used.
  • the first protection level is physical hardware protection of the chips.
  • the front face of an electronic chip (the face on which the electronic chip circuit is located) may be protected by adding special protection layers on this front face.
  • These protection layers have physical and/or electrical properties that change when external attacks are made on the electronic chip, so that the chip can detect an attack and if required, can put itself in fault.
  • front face protection of an electronic chip is to implant an active metal screen on the top face of the electronic circuit of the chip and to check its integrity.
  • Such a screen was initially developed to prevent physical probing (setting up an electrical connection with one of the subjacent tracks on the front face of the chip), but it is also efficient for preventing contactless interactions with the electronic circuit of the chip (fault injections through a laser or electromagnetic radiation, contactless probing, observation of the electromagnetic radiation of the electronic circuit, etc.).
  • a mechanism for checking the integrity of the screen is necessary, in other words capable of detecting even a very minor alteration in the screen (broken track, change in track length, etc.).
  • the usefulness of a screen placed on the back face of the electronic chip is based on the capacity to check its integrity, making connections necessary between the logic implemented in the electronic circuit and this screen. It is relatively easy to use physicochemical manipulations or focussed ion beams (FIB), either to remove this protection screen for example by thinning the circuit, or to modify it (for example by forming a hole in the screen to obtain access to the back face of the chip). Therefore, it is essential to have a screen integrity check mechanism.
  • FIB focussed ion beams
  • On-off type mechanisms in other words mechanisms that verify the presence of the screen, can easily be attacked, for example by making an FIB connection, such that the screen always appears to be present to the electronic circuit.
  • Document US 2007/121575 A1 discloses an electric chip designed to contain or to process data to be protected in a secure manner.
  • the front face of the chip comprises an inductance that, by inductive coupling through the chip substrate, detects the presence of a conducting ground plane located on the back face of the chip. Alteration by attacking this conducting ground plane induces a variation in the inductive coupling between the front and back faces of the chip, which leads to a chip fault.
  • an electronic chip comprising at least:
  • a capacitive element refers to an element forming a non-zero electrical capacitance at the back face of the substrate and possibly in part of the thickness of the substrate.
  • such an electronic chip comprises an efficiently protected back face due to the capacitive element present at the back face of the substrate and the value of which can be checked to assure that the back face maintains its integrity. Therefore such a capacitive element provides efficient protection of the back face of the electronic chip, for example against thinning of the back face of the chip because such thinning would modify the value of the electrical capacitance of the capacitive element, that could be detected for example by a check on this value made by the electronic circuit on the chip.
  • the fact that the substrate of the electronic chip cannot be thinned significantly complicates procedures for recovery of data stored on the chip, including physical (for example electrical) and electromagnetic procedures.
  • the electronic circuit may be put out of service immediately when a physical attack is detected on the back face of the electronic chip (for example if the value of the capacitance of the capacitive element is changed).
  • the capacitive element present at the back face of the electronic chip also forms a good protection means against attacks involving electromagnetic radiation, since this capacitive element forms a screen against such radiation.
  • the first electrical connection between the capacitive element and the electronic circuit is formed by a physical connection made particularly by the first electrically conducting via, thus improving the security of the integrity check of the back face of the chip, because it is much more difficult to interact with such a physical electrical connection than with an inductive coupling connection.
  • the second via(s) or the trench(es) passing through the back face of the substrate and part of the thickness of the substrate facing the electronic circuit protect the back face of the electronic chip from chemical attacks because such an attack would destroy the electronic circuit of the chip due to the proximity of the bottom of the second via(s) or trench(es) to the electronic circuit.
  • this or these vias or this or these trenches form passive protection means against chemical attacks of the back face of the electronic chip.
  • these elements may in this case provide efficient protection against attacks by laser beams.
  • the second electrical connection may comprise at least one third electrically conducting via passing through the substrate or it may comprise at least part of the substrate that is electrically conducting or semiconducting.
  • the distance between the bottom wall of the second via or the trench and the electronic circuit may be less than or equal to about 20 ⁇ m, or less than or equal to 20 ⁇ m. Such proximity between the bottom wall of the second via or the trench and the electronic circuit can improve the protection of the back face of the electronic chip against chemical attacks of the back face of the substrate of the chip because in this case, the electronic circuit is quickly destroyed by the chemical agents used to attack the back face of the electronic chip.
  • the electronic chip may comprise at least:
  • the first electrically conducting layer possibly forming a first electrode of the capacitive element and being electrically connected to the electronic circuit through the first electrical connection.
  • Such a configuration can result in a capacitive element for which the value can be checked with good sensitivity. Furthermore, the presence of an electrically conducting material such as a metal in the second via(s) or trench(es) then forms a screen against electromagnetic radiation.
  • Part of the substrate placed in contact with the first dielectric layer and facing the first electrically conducting layer may form a second electrode of the capacitive element.
  • the first dielectric layer and the first electrically conducting layer may completely fill the volumes formed by the first and/or the second electrically conducting via or the trench.
  • the protection of the back face of the chip is improved in this configuration, particularly when the first dielectric layer and the first electrically conducting layer completely fill the volume formed by the second via(s) or the trench(es).
  • the electronic chip may also comprise a second structured electrically conducting layer at the front face of the substrate, forming a coil inductively coupled to at least part of the first electrically conducting layer, and the second electrically conducting layer may be electrically connected to the electronic circuit that can measure the value of an inductance of the coil.
  • said part of the first electrically conducting layer may correspond to the part located at the bottom wall of the second via or the trench.
  • the first electrically conducting layer may comprise a material which is not transparent to wavelengths between about 100 nm and 10 ⁇ m, in other words from the infrared to the ultraviolet.
  • the first electrically conducting layer can be used to reflect, diffract or diffuse light radiation such as laser beams that reach the back face of the electronic chip.
  • the capacitive element may comprise at least:
  • the electronic chip may comprise at least one third plane electrically conducting portion separated from the first plane electrically conducting portion by the second dielectric layer and electrically connected to the electronic circuit through at least the third electrically conducting via passing through the substrate, and the first plane electrically conducting portion and the third plane electrically conducting portion may form a first electrode and a second electrode respectively of a second capacitive element located at the back face of the substrate and at least partly facing the electronic circuit.
  • the capacitive element is formed by at least two plane capacitances formed at the back face of the substrate.
  • the first plane electrically conducting portion may be in contact with an electrically conducting material that fills at least the second via or the trench and may be electrically connected to the electronic circuit through at least the third electrically conducting via passing through the substrate.
  • the first plane electrically conducting portion may be electrically connected to the electronic circuit through at least a part of the substrate which is electrically conducting or semiconducting.
  • the electronic chip may comprise several second vias or trenches passing through the back face of the substrate and part of the thickness of the substrate and having different dimensions.
  • the thickness of the substrate may be between about 200 ⁇ m and 700 ⁇ m, which makes it more difficult to attack the front face of the electronic chip from its back face.
  • the electronic circuit may be made directly on the substrate or it may be transferred onto the substrate.
  • the method may include the fabrication of several second vias or trenches passing through the back face of the substrate and part of the thickness of the substrate, the dimensions of each of the second vias or trenches being chosen randomly relative to the dimensions of the other second vias or trenches. This thus makes it even more difficult to reproduce the capacitive element in comparison with a capacitive element for which the electrical capacitance has a predefined value.
  • the value of the capacitance of the capacitive element can be measured for example the first time that the electronic chip is powered up and it may be verified subsequently each time that the chip is activated.
  • the method may include the fabrication of at least one third electrically conducting via passing through the substrate and that will form at least part of the second electrical connection.
  • FIG. 1 shows an electronic chip according to a first embodiment
  • FIGS. 2A to 2C show the steps in a method of making the electronic chip according to the first embodiment
  • FIG. 3 shows an electronic chip according to a variant of the first embodiment
  • FIG. 4 shows an electronic chip according to a second embodiment
  • FIG. 5 shows an electronic chip according to a third embodiment
  • FIG. 6 shows an electronic chip according to a fourth embodiment
  • FIG. 7 shows an electronic chip according to a variant of the first embodiment.
  • FIG. 1 shows an electronic chip 100 according to a first embodiment, the back face of which comprises means of protecting from attacks against this chip.
  • the electronic chip 100 comprises a substrate 102 , for example comprising an electrically conducting or semiconducting material such as silicon, with a thickness of more than about 120 ⁇ m, and preferably between about 200 ⁇ m and 700 ⁇ m.
  • the substrate 102 comprises a first main face called the front face 104 and a second main face called the back face 106 opposite the front face 104 .
  • the front face 104 and the back face 106 of the substrate 102 are considered as being the front and back faces of the electronic chip 100 .
  • the electronic chip 100 also comprises an electronic circuit 108 , particularly including CMOS transistors made at the front face 104 of the substrate 102 and in which data to be protected are stored.
  • the electronic chip 100 also comprises means protecting the back face of the electronic chip 100 and particularly the electronic circuit 108 from the back face 106 .
  • these means comprise several non-through vias 110 made from the back face 106 of the substrate 102 through part of the thickness of the substrate 102 facing the electronic circuit 108 .
  • the vias 110 have depths (dimensions along the Z axis) and dimensions in a plane parallel to the main faces 104 and 106 of the substrate 102 ((X,Y) plane), corresponding to the diameters in the case of vias 110 with approximately circular sections, different from each other, and for example chosen at random during their fabrication.
  • the depths of the vias 100 are related to the diameters of the vias 110 and are chosen particularly as a function of the thickness of the substrate 102 and the depth reached by the electronic circuit 108 in the substrate 102 .
  • the side walls and the bottom walls of the vias 110 are covered with a dielectric layer 112 , for example comprising an oxide such as SiO 2 that also covers the back face 106 of the substrate 102 .
  • An electrically conducting layer 114 for example corresponding to a metallic layer that can be made with copper and/or tungsten, continuously covers the dielectric layer 112 at the side walls and bottom walls of the vias 110 , and at part of the back face 106 of the substrate 102 , particularly between the vias 110 .
  • the electrically conducting layer 114 , the dielectric layer 112 and part of the substrate 102 that is separated from the electrically conducting layer 114 by the dielectric layer 112 together form a capacitive element 115 , for which the value of the electrical capacitance depends particularly on the dimensions of vias 110 (depths and diameters). Since the dimensions of the vias 110 are chosen at random, the value of this electrical capacitance is also random.
  • the electrically conducting layer 114 forms the first electrode of this capacitive element 115 .
  • the part of the substrate 102 in contact with the dielectric layer 112 and located facing the electrically conducting layer 114 forms the second electrode of this capacitive element 115 .
  • a through via 116 is made through the entire thickness of the substrate 102 adjacent to the electronic circuit 108 .
  • the dielectric layer 112 and the electrically conducting layer 114 cover the side walls of the via 116 , and the electrically conducting layer 114 is prolonged at the bottom wall of the via 116 (unlike the dielectric layer 112 that only covers the side walls of the via 116 and not the bottom wall of the via 116 ), thus providing an electrical access from the front face 104 of the substrate 102 to the first electrode of the capacitive element 115 present on the back face of the electronic chip 100 .
  • a first electrically conducting element 118 a formed on the front face 104 of the substrate 102 electrically connects the conducting via 116 to the electronic circuit 108 .
  • a second electrically conducting element 118 b is also formed on the front face 104 of the substrate 102 and electrically connects the substrate 102 to the electronic circuit 108 .
  • the first electrically conducting element 118 a and the via 116 form a first electrical connection between the first electrode of the capacitive element 115 and the electronic circuit 108 .
  • the second electrically conducting element 118 b and the substrate 102 form a second electrical connection between the second electrode of the capacitive element 115 (formed by the part of the substrate 102 located in contact with the dielectric layer 112 and facing the electrically conducting layer 114 ) to the electronic circuit 108 . Therefore the value of the electrical capacitance of the capacitive element 115 can be measured by the electronic circuit 108 by means of these two electrical connections by which the electronic circuit 108 can measure the voltage or the potentials difference between the two electrodes of the capacitive element 115 .
  • the protection means disclosed above can protect the electronic chip 100 against several types of attacks.
  • thinning for example mechanical-chemical planarisation
  • Such thinning would eliminate the parts of the electrically conducting layer 114 located on the back face 106 of the substrate 102 , thus causing a break of the electrical contact between the parts of the electrically conducting layer 114 located in the vias 110 and the conducting via 116 , and therefore between the capacitive element 115 on the back face of the electronic chip 100 and the electronic circuit 108 .
  • a measurement of the value of the electrical capacitance of the capacitive element 115 by the electronic circuit 108 and a comparison between the measured value and a reference value can detect if the back face of the electronic chip has been thinned.
  • a reference value for example corresponding to a measurement of this capacitance the first time that the electronic chip 100 is used
  • the random nature of the value of this electrical capacitance formed at the back face of the electronic chip 100 when the dimensions of the vias 110 are chosen randomly also contributes to this protection because it is then impossible to simulate the presence of this capacitance if it has been destroyed, because its value is unknown.
  • the matrix of vias 110 can be used to reflect, diffract or diffuse light beams, for example laser beams or electromagnetic radiation.
  • the dimensions of the vias 110 are advantageously less than the wavelength of the laser light beams that would be blocked.
  • vias 110 at the back face of the electronic chip 100 also protects the electronic chip 100 against chemical attacks.
  • the bottom walls of the vias 110 are close to the electronic circuit 108 , for example such that the distance separating the electronic circuit 108 from the bottom wall(s) of one or several vias 110 is less than or equal to about 20 ⁇ m, or for example between about 10 and 20 ⁇ m.
  • the layers or materials deposited in the vias 110 may be thin enough such that the protection of the electronic chip 100 is not altered in view of chemical attacks.
  • the dielectric layer 112 has for example a thickness between about 200 nm and 500 nm and the electrically conductive layer 114 has for example a thickness between about 200 nm and 2000 nm.
  • the depositions carried out for making these layers which are for example PVD or PECVD, the deeper the vias are, the thinnest the deposited layers are, and thus the closest to the component the layers are.
  • the thickness of the materials arranged in the vias 110 may be unimportant compared to the aggressiveness of the chemical attacks (acid, basic, etc.).
  • the vias 110 may be partially filled by these layers or materials. During a chemical attack, the materials arranged in the vias 110 may be consumed faster than the material of the substrate 102 .
  • the electronic circuit 108 and the electrically conducting elements 118 a , 118 b are made at the front face 104 of the substrate 102 .
  • the substrate 102 may be thinned from its back face 106 if the initial thickness of the substrate 102 is greater than required.
  • the vias 110 and the via 116 are then defined by lithography and are etched, for example by the use of deep reactive ionic etching (DRIE), as shown in FIG. 2B .
  • DRIE deep reactive ionic etching
  • each via Since the etching depth of each via is dependent on the diameter of the etched via, it is possible to define a matrix of vias 110 through the back face 106 of the substrate 102 , with random dimensions and thus obtain vias 110 with different depths. However, the dimensions of the vias 110 are chosen such that these vias 110 facing the electronic circuit 108 do not reach the electronic circuit 108 through the substrate 102 . In particular, large vias 110 for which the bottom walls are very close to the electronic circuit 108 , and therefore provide very efficient protection against chemical attacks from the back face of the electronic chip 100 , can be combined with smaller vias that provide efficient protection against laser beam attacks.
  • the dielectric layer 112 is then formed on the side walls of the vias 110 and the via 116 , on the bottom walls of the vias 110 and on the non-etched parts of the back face 106 of the substrate 102 .
  • this dielectric layer 112 is obtained by the use of an oxide or silicon nitride deposit (for example of the PECVD type) on parts of the substrate 102 forming the walls of the vias 110 and 116 and the back face 106 of the substrate 102 .
  • the part of the dielectric layer 112 at the bottom of the via 116 is etched, for example with or without lithography, so that the part of the electrically conducting layer 114 that will subsequently be formed in the via 116 can be electrically in contact with the first electrically conducting element 118 a.
  • the method is completed by forming the electrically conducting layer 114 at the back face of the electronic chip 100 so as to cover the dielectric layer 112 at the walls of the vias 110 and 116 , part of the non-etched portions of the back face 106 of the substrate 102 , and also covering the bottom wall of the via 116 to be electrically in contact with the first electrically conducting element 118 a .
  • the electrically conducting layer 114 may be made by deposition and then etching. The electronic chip 100 disclosed above with reference to FIG. 1 is thus obtained.
  • one or several vias 110 may be made at the back face 106 of the substrate 102 facing the electronic circuit 108 , without needing to fill this or these vias 110 with the electrically conducting layer 114 nor to make an electrical connection with the electronic circuit 108 .
  • the protection means in this case may correspond to vias 110 made on the back face 106 of the substrate 102 facing the electronic circuit 108 , the walls of which are covered with the dielectric layer 112 and the electrically conducting layer 114 , but without the need for any electrical connection with the electronic circuit 108 because these layers form a screen against received radiation.
  • the thickness of the electrically conducting layer 114 is such that the vias 110 and 116 are not completely closed off.
  • the thickness of the electrically conducting layer 114 is such that it entirely fills the vias 110 and 116 as shown in FIG. 3 .
  • this variant can increase the strength of the electronic chip 100 while it is being manipulated.
  • FIG. 4 shows an electronic chip 200 according to a second embodiment.
  • the electronic chip 200 comprises the substrate 102 , the electronic circuit 108 , the vias 110 the walls of which are covered by the dielectric layer 112 and the electrically conducting layer 114 , the conducting via 116 and the electrically conducting elements 118 a and 118 b .
  • the electronic chip 200 also comprises another dielectric layer 202 on the front face 104 of the substrate 102 , on which another structured electrically conducting layer 204 is made, for example corresponding to a metallic layer forming a coil that can create inductive coupling with the parts of the electrically conducting layer 114 located in the deepest vias 110 .
  • another structured electrically conducting layer 204 is made, for example corresponding to a metallic layer forming a coil that can create inductive coupling with the parts of the electrically conducting layer 114 located in the deepest vias 110 .
  • this coupling is shown symbolically by inductances between the other structured electrically conducting layer 204 and the parts of the electrically conducting layer 114 located in the bottom of the vias 110 .
  • Such inductive coupling occurs particularly when the distance between the parts of the electrically conducting layer 114 located at the bottom of the vias 110 and the other structured electrically conducting layer 204 is less than or equal to about the coil diameter. Therefore, given the random nature of the depth of vias 110 made, the inductive coupling obtained is localised and random.
  • this second embodiment enables an integrity check of the back face of the electronic chip 200 not only due to the check of the electrical capacitance of the capacitive element 115 formed at the back face of the chip 200 but also by checking the value of the inductive coupling between the coil formed by the other structured electrically conducting layer 204 and the vias 110 , this measurement being made by the electronic circuit 108 (the other structured electrically conducting layer 204 is electrically connected to the electronic circuit 108 by at least one electrical connecting element 206 passing through the dielectric layer 202 ).
  • FIG. 5 shows an electronic chip 300 according to a third embodiment.
  • the electronic chip 300 comprises the substrate 102 , the electronic circuit 108 , the conducting via 116 and the electrically conducting elements 118 a and 118 b .
  • the protection means of the back face of the chip are different from the protection means of the electronic chips 100 and 200 .
  • the back face 106 of the substrate 102 facing the electronic circuit 108 is covered by a first plane electrically conducting portion 302 , in this case corresponding to a plane metallic portion.
  • the first plane electrically conducting portion 302 is electrically connected to the electronic circuit 108 through the substrate 102 (because this substrate comprises a conducting or semiconducting material that transfers an electrical potential from the back face of the substrate 102 as far as the electronic circuit 108 ).
  • the first plane electrically conducting portion 302 is covered by another dielectric layer 304 , for example comprising a material stable at high temperature such as SiO 2 .
  • this dielectric layer 304 also covers the parts of the back face 106 of the substrate 102 that are not covered by the first plane electrically conducting portion 302 .
  • a second plane electrically conducting portion 306 a and a third plane electrically conducting portion 306 b are placed in contact with the dielectric layer 304 , each at least partly facing the first plane electrically conducting portion 302 , one ( 306 a ) of which is electrically connected to the electronic circuit 108 through the electrical connection formed by the conducting via 116 and the first electrically conducting element 118 a , and the other ( 306 b ) of which is electrically connected to the electronic circuit 108 through the electrical connection formed by another conducting via 308 made through the substrate 102 and the dielectric layer 304 , and the second electrically conducting element 118 b .
  • the side walls of the vias 108 and 308 are covered by a dielectric material that avoids electrical contact between the substrate 102 and the electrically conducting materials filling the vias 108 and 308 .
  • the integrity of the back face of the electronic chip 300 is controlled by checking the value of the capacitance of a first plane capacitive element 115 a formed by the first plane electrically conducting portion 302 , corresponding to the first electrode of this first capacitive element 115 a , and the second plane electrically conducting portion 306 a corresponding to the second electrode of this first capacitive element 115 a , separated from each other by the dielectric layer 304 , and checking the value of the capacitance of a second plane capacitive element 115 b formed by the first plane electrically conducting portion 302 corresponding to the first electrode of this second capacitive element, and the third plane electrically conducting portion 306 b corresponding to the second electrode of this second capacitive element 115 b, separated from each other by the dielectric layer 304 .
  • a larger number of plane capacitive elements can be made at the back face of the electronic chip 300 .
  • Each of the capacitive elements formed at the back face of the electronic chip 300 is connected to the electronic circuit 108 through at least one conducting via that can made a fine mesh of electrical capacitances covering the entire back face of the electronic chip 300 .
  • Such protection means enable electrical detection of an attack on one or several capacitive elements on the back face of the chip (by measuring the values of capacitances of these elements as disclosed above for electronic chips 100 and 200 ) and can also form a screen against electromagnetic attacks.
  • the first portion 302 might be omitted, and the first electrode of the first capacitive element 115 a and the first electrode of the second capacitive element 115 b that are formed by the substrate 102 may be used as in the first embodiment disclosed above.
  • the plane electrically conducting portions 302 , 306 a and 306 b each have an approximately rectangular shaped section in a plane parallel to the front face 104 and the back face 106 of the substrate 102 (parallel to the (X,Y) plane), or more generally they may have solid surfaces.
  • the sections of one or several of these electrically conducting portions forming the capacitive elements at the back face of the electronic chip 300 may have different shapes, for example they may be in the form of a network of coils and thus form electrically conducting tracks, which can maximise variations in the value of the electrical capacitance if these capacitances are modified, and therefore have better sensitivity to detection of an attack on the back face of the electronic chip 300 .
  • FIG. 6 shows a fourth embodiment of an electronic chip 400 .
  • the means of protection of the back face of the electronic chip 400 are based on a measurement of the electrical capacitance of a capacitive element 115 formed at the back face 106 of the substrate 102 , between a first plane electrically conducting portion 302 and a second plane electrically conducting portion 306 separated from each other by the dielectric layer 304 .
  • the first plane electrically conducting portion 302 is connected to the vias 110 filled with an electrically conducting material, for example metallic, and the dimensions of which vary from each other and are random.
  • the conducting via 308 in this case connects the plane electrically conducting portion 302 to the second electrically conducting element 118 b itself connected to the electronic circuit 108 .
  • the presence of vias 110 makes it possible to defend against laser beam attacks made on the back face of the electronic chip 400 .
  • FIG. 7 shows a variant of the first embodiment of the electronic chip 100 .
  • the second electrical connection electrically connecting the second electrode of the capacitive element 115 (formed by the part of the substrate 102 in contact with the dielectric layer 112 and facing the electrically conducting layer 114 ) to the electronic circuit 108 that in this case is made by a second via 308 electrically connected to the second electrically conducting element 118 b and to a connection zone of the electrical contact 310 located at the back face 106 of the substrate 102 and that is in contact with the part of the substrate 102 forming the second electrode of the capacitive element 115 .
  • Such a second electrical connection improves the measurement of the value of the capacitance of the capacitive element 115 , particularly when the substrate 102 is semiconductor-based because the transfer of the electrical potential of the second electrode made by this second via 308 is better than is possible with the substrate 102 . Furthermore, such a configuration enables any type of electronic circuit 108 to make contact with the substrate, regardless of whether or not the electronic circuit has an electrical contact element on the front face. Finally, such a second electrical connection can also be used when the substrate 102 is not homogeneous, in other words when it is not formed from an electrically conducting or semiconducting material alone, for example in the case of an SOI substrate. This variant can also be applied to chips previously disclosed with reference to FIGS. 3 and 4 .
  • the cross-sections of the vias 110 in a plane parallel to the front face 104 and the back face 106 of the substrate 102 are arbitrary in shape (rectangular, triangular, etc.), or that these vias 110 are partially or totally replaced by trenches, that may or may not be straight, the side walls and bottom walls of which may or may not be covered by the dielectric layer 112 and the electrically conducting layer 114 , or completely filled with an electrically conducting material.
  • the references 110 may denote trenches that are seen in a side sectional view in these figures.
  • the protection of the back face of the electronic chips 100 - 400 disclosed above is compatible with known protections for the front face of electronic chips (for example active metal screens), and the means of protection of the back face of electronic chips 100 - 400 disclosed above may be combined with such protection on the front face of electronic chips 100 - 400 .

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FR1360292A FR3012237B1 (fr) 2013-10-22 2013-10-22 Puce electronique comprenant des moyens de protection de sa face arriere
FR1360292 2013-10-22

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FR3055471B1 (fr) * 2016-08-31 2018-09-14 Stmicroelectronics (Crolles 2) Sas Puce protegee contre les attaques face arriere
CN107818271B (zh) * 2016-09-14 2023-08-29 国民技术股份有限公司 基于芯片版图的故障注入分析方法及系统
FR3063385B1 (fr) 2017-02-28 2019-04-26 Stmicroelectronics (Rousset) Sas Circuit integre avec detection d'amincissement par la face arriere et condensateurs de decouplage
FR3069703B1 (fr) 2017-07-27 2020-01-24 Stmicroelectronics (Crolles 2) Sas Puce electronique
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FR3077158B1 (fr) * 2018-01-25 2021-02-26 Commissariat Energie Atomique Puce electronique a face arriere protegee par une structure de fragilisation amelioree
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US20150108606A1 (en) 2015-04-23
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FR3012237A1 (fr) 2015-04-24
EP2866259A1 (fr) 2015-04-29

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