TW423146B - Manufacturing method of crown-shape capacitor structure - Google Patents

Abstract

A manufacturing method of crown-shape capacitor structure is provided, which is suitable for a substrate having a switch, a plug connected to the switch, a bit-line, and a first isolation layer for isolating the substrate. The method comprises: first, defining a first isolation layer to form a first contact for communicating to the plug; then, adaptively depositing a shielding layer on a first contact, and extending the same to the surface of the first isolation layer; depositing a second isolation layer, and forming a second contact window on the plug by definition; partially removing the shielding layer to form a shielding sidewall object on the sidewall of the first isolation layer; adaptively depositing a conductive layer to fill the space enclosed by the shielding sidewall objects and extending the same to the sidewall and surface of the second isolation layer; spreading a photoresist layer to fill in the space enclosed by the conductive layer and extending the same to its surface; after a planarization process, forming a conductive sidewall and remaining the filled photoresist layer; sequentially removing the photoresist layer, the second isolation layer and the shielding layer, so as to remain the conductive sidewall layer thereby forming a bottom electrode; and completing the subsequent manufacturing of crown-type capacitor structure.

Description

Ή. 423146 V. Description of the invention (2)-come out. Mr. Lee et al. Of Hyundai Electronics Co., Ltd., in US Patent No. 5,185,282, 'expose a capacitor with a cup-shaped structure. Masao Taguchi et al. Of Fujitsu Corporation disclosed in US Patent No. 5,021,357' Fin-shaped capacitor structure; Choi et al., Samsung Electronics Co., Ltd. of Korea, discloses a & round ° cylindrical capacitor structure in U.S. Patent No. 5,104,821. These conventional technologies use increasing the surface area of the lower electrode plate to increase the capacitance of the capacitor. However, these conventional manufacturing technologies have complicated and tedious manufacturing processes, which not only increases the manufacturing cost of memory elements and lengthens the production cycle time. . In addition, since the base area of the memory cells must be continuously reduced to increase the density, when the contact nodes of the capacitor are made, the distance between the bit lines is often too close, which is damaged by wet etching during the process of conducting the plug. Otherwise, it is because the conductive plug is extremely close to the bit line and accidentally comes into contact with the bit line, which causes a short circuit, making the data inaccessible. In order to avoid this phenomenon, the process of the conventional technology is shown in Figure 丨 A. First, a thermal oxidation process is performed on the P-type silicon substrate 100, such as the area oxidation method (LOCOS) (not shown) to form a field of insulation. Layer, and the field insulation layer is used to isolate the active area. Secondly, a semiconductor process such as deposition, lithography, and ion implantation is used to form a bit line 1 41 and a semiconductor connected to other memory cells on the active area. A device such as a transistor (not shown), the transistor is composed of the gate C and a diffusion region. The main component of the bit line 141 and the gate is a polycrystalline silicon material, and the diffusion region includes a source / drain region.丨 44. Next, a first insulating layer 148 is formed to isolate the transistor, the bit line 141 and the subsequent conductive layer. Secondly, the first insulating layer 1 48 is defined by a lithography process and an etching process to form an opening such as a source / drain. Pole contacts the window and then forms a

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'23146 V. Description of the invention (3) The silicon nitride layer 149 is used as a shielding layer to cover the first insulating layer 148 and extends compliantly to the inner wall and bottom of the source / electrode contact window. As the size of the memory cell elements continues to shrink, the aspect ratio of the contact window is increased. When etching using the money engraving process, it is often the case that the etch king does not occur for narrow and deep contact windows. The conductive plugs generated in subsequent processes will not be able to contact the source / drain electrodes, which may cause open circuit problems, resulting in failure to access data normally. Please refer to FIG. 1B, and then use a dry etching process to remove the first insulating layer. The silicon nitride layer 1 49 on the surface and the bottom of the source / drain contact window is formed by a dry etching process. And 149b. Then, a polycrystalline stone layer 150 is formed as a conductive layer to cover the first insulating layer 1 48 and fill the inner space of the source / inverter contact window. 'Refer to Figure 1C' to remove the polycrystalline stone layer 1 50 on the surface of the first insulating layer 14 8 with a dry-reset process and form a conductive plug in electrical contact with the source / inverter region 14 4 Plug 147. Due to the shrinking component size of the memory cells and the increase in the aspect ratio of the conductive plugs, the uniformity of the polycrystalline sand deposits deposited in the conductive plugs is not good, and it is easy to cause the resistance of the conductive plugs to rise or even break. . Secondly, an atmospheric petrified layer 152 is formed on the surface of the first insulating layer 148 as a shielding layer. Next, a second insulating layer 155 is formed on the surface of the nitride nitride layer 152, and the second insulating layer 155 is defined by a lithography process to form a second contact exposing the surface of the silicon nitride layer 152 above the conductive plug 147. Window 156. Please refer to FIG. 1D 'removing the argon silicon layer 1 52 in the second contact window be by an etching process; a polycrystalline silicon layer 1 60 is conformably formed on the surface of the second insulating window 1 55 and extends to the second contact window 1 The side wall and bottom of 56 are conductive

Floor. Please refer to FIG. 1E #, remove the polycrystalline spar layer 1 on the surface of the second insulating layer 155; then remove the remaining second insulating layer 丨 55 'The polycrystalline silicon layer 160 and the conductive plug 14 7 are used as the lower electrode plate, and then conformably formed—a dielectric layer 170 on the polycrystalline silicon layer 160, and then an upper electrode plate 180 is formed on the dielectric layer. The manufacturing of the capacitor structure of the dynamic random access memory is completed on 170. Enclose contact-in-window-shielding layer to isolate the waterfall line. Then, another layer is formed on the insulation layer-layer j- ', which is used to remove the insulating layer around the crown capacitor. The invention is to improve the shortcomings of the conventional technology. The process ^ 'can form a drawer on the inner wall of the contact window. At the same time, a conductive M plug ^ and bit lines are formed. A shielding layer can be formed on the insulating layer. When the contact window is formed, the bit line is protected from being damaged by the etching, and it is also used as a shield when removing the insulating layer around the crown capacitor. The base of the thundercrest is protected from being damaged by the etching due to excessive etching. . The invention provides a method for manufacturing a crown capacitor, which has two main characteristics: the conventional technology is simplified. The invention only forms a shielding layer, which can avoid the short circuit between the bit line and the conductive plug due to the lithographic deviation, and can protect the crown capacitor from collapse due to over-etching of the base or even from over-etching. The bit line damaged D conventional technique must form a shielding layer in two times to achieve the aforementioned effect, so the manufacturing process is more complicated. Secondly, to ensure the conductivity of the conductive plug. Coronal capacitance

D: \ My Documents, Bureau of Successful Bids \ 87043 · ptd Page 7 V. Explanation of the Invention (5) Device and Source Contact Procedure Etching Full Situation Occurrence Method and Source Contact Information. At the same time, the resistance of the conventional plug must be increased compared to the conventional plug. The present invention includes the following steps in a switching element: The contact window formed in the first layer in the insulating layer is larger and larger as the width-to-width ratio. At the moment, 'there is often an incomplete etch for a narrow and deep contact window', so the conductive plugs generated in subsequent processes will be free of the problem of easy disconnection, resulting in failure to access normally.埴 洄 'can avoid the formation of electricity due to the uniformity of the hole filling and a second connection layer covering the side wall of a maskable layer, and contacting the third surrounding connection cover of the third surrounding cover of the window layer side wall, which communicates with the above and the bottom Contact window; above; etching to form one or three insulating parts; the disadvantage of contact window height or disconnection is a manufacturing method of a crown capacitor structure, which is suitable for manufacturing capacitors on a semiconductor substrate, and the manufacturing method includes forming a first insulating layer On the above-mentioned substrate; in the above-mentioned first contact window which can be connected to the switching element; the contact window forms a conductive plug to communicate with the switching element; The surface of the insulating layer forms a second insulating layer of a single-bit line; a second contact window of the conductive plug is formed in the second insulating layer; a surface of the second insulating layer is formed compliantly and extends to the second Contact: forming-the third insulating layer & the masking layer and filling the third insulating conductive plug defined by the lithography process and the etching step to form a third masking layer exposing the masking layer so as to The second insulating side wall of the third contact window is a second conductive layer covering the wide surface and the third contact window with compliance, and fills the side wall with the first: conductive layer surface and fills. Internal space, a flattening step is performed on the photoresist layer

D: \ My Documents' Winning Office \ 87043. ptd Page 8

4 2- 3 1 4 6

The p-layer and electric-layer finish the crown with the structure. No. 88ini4m V. Description of the invention (6) The knee to leave the third contact

If the "Euper edge layer" part; sequentially remove the above, the first, the Euper edge layer, and the shielding layer: the light forms the electrode plate under the capacitive structure; a dielectric layer J is formed under the second An electrode plate; and manufacturing of an electric layer on a read capacitor-like capacitor structure. On the electrode plate ^ dielectric layer, it can be more B months, in order to make the above and ^ H of the present invention easy to understand. The following is enumerated-the best practice and advantages are described in detail as follows: Briefly explain the main steps of Figures 1 A to 1 E. Figures 2A to 2M are the main steps of a manufacturing method. The 2N to 2P circle system shows the symbol description. The structure manufacturing method represents a crown-shaped container made of an embodiment of the present invention, and is not a cracking method of another embodiment of the present invention. 100, 2 0 0 ~ substrate; 14 4, 21 0 ~ source / drain region; 1 41, 2 4 6 ~ bit line; 147 '225 ~ conductive plug; 160, 260 ~ capacitor lower electrode plate;

V. Description of the invention (Ό 170, 2 70 ~ capacitor dielectric layer; 1 80, 2 0 0 ~ capacitor upper electrode plate; 148 '155, 220, 230, 230', 240, 250, 290 ~ insulation layer; 149 152,242 ~ shielding layer; 150,1 60,2 60 ~ conducting metal; 5 2,2 6 5 ~ photoresist; 149a, 149b, 242a, 242b ~ side wall; 245 '255' • contact window. Example Please refer to FIG. 2A, which shows the initial steps of the present invention. In this figure, the substrate 200 is a semiconductor material such as silicon and germanium, and the formation method is a worm crystal or silicon on the insulating layer. Here, a p-type Shixi substrate is taken as an example. The initial steps are shown in FIG. 2A. 'Firstly, the P-type silicon substrate 2000 is subjected to a thermal oxidation process / such as a regional oxidation method (Locos). Form a field insulation layer (not shown) 'and use the field insulation layer to isolate the active area β. Secondly, a semiconductor device such as deposition, lithography, and ion implantation is used to form a semiconductor device such as a transistor on the active area. (Not shown), the transistor is composed of a gate and a diffusion region. The main component of the gate is a polycrystalline silicon material, which diffuses. The regions include, for example, a source region and a non-electrode region. Here, the source / non-electrode region 21 0 is taken as an example. Then, the first insulating layer 2 20 ′ is formed, for example, by a chemical vapor deposition (CVD) method or a conventional method.

V. Description of the invention (8) Learn about vapor phase deposition (APCVD) or sub-normal pressure chemical vapor deposition (SAPCVD) or low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) Or high density plasma chemical vapor deposition (HDPCVD) deposition of a borophosphosilicate glass (BPSG) layer, undoped silica glass layer (NSG), high density plasma oxide layer (HDP Ox ide) or tetraethyl The purpose of the oxysilicate layer (T EOS) is to isolate the transistor from the subsequent conductive layer. Secondly, the first insulating layer 220 is defined by a lithography process and an etching process to form an opening such as a source / drain contact window, and then a first conductive layer (not shown) is formed. For example, a low-pressure chemical vapor deposition method is used to deposit a thickness of A 1000-10000 angstrom polycrystalline silicon layer is covered on the first insulating layer 220 and filled in the source / inverter contact window. The first conductive layer on the surface of the first insulating layer 220 is removed by an etching process to form a conductive plug 225 that is in electrical contact with the source / inverter region 210 so as to form an electrical connection with the aforementioned switching element. An additional insulating layer 230 is formed on the surface of the first insulating layer 220, for example, by chemical vapor deposition (CVD) or atmospheric pressure chemical vapor deposition (APCVD) or sub-normal pressure chemical vapor deposition (SAPCVD). ) Or low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD) deposition of a borophosphosilicate glass (BPSG) layer, no doping The thickness of the impurity silica glass layer (NSG), high-density plasma oxide layer (HDP Oxide), or tetraethoxysilicate layer (TE0S) can be 100,000 to 5000 angstroms. A bit line 246 connected to other memory cells is formed on the surface of the aforementioned insulating layer 230 according to semiconductor processes such as deposition, lithography, and ion implantation. The main component of the bit line 246 may be polycrystalline silicon or other Metal silicide. Another insulating layer 230 is formed on the surface of the insulating layer 230 and the surface of the bit line 246, for example,

My Documents' Winning Bureau \ 87043. ptd Page 11 V. Description of Invention (9) It is a chemical vapor deposition method (CVD) or atmospheric pressure chemical vapor deposition method (APCVD) or a sub-normal pressure chemical vapor deposition method (SAPCVD). ) Or low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) or high-density electrical chemical vapor deposition (HDPCVD) deposition of a borophosphosilicate glass (BPSG) layer, no push The thickness of the impurity silica glass layer (NSG), high-density plasma oxide layer (HDP Oxide), or tetraethoxysilicate layer (TE0s) can be 3,000 to 10,000 angstroms. In this way, the bit line 246 can be completely covered, and an insulation effect can be achieved. Since the materials are the same, for convenience of explanation, the insulating layers 230 and 230 are collectively referred to herein as the second insulating layer 240. Then, a planarization process is performed to make the surface flat for subsequent processes. Referring to FIG. 2B, a second contact window 245 is formed in the second insulating layer 240 and can be connected to the conductive plug 2 25. The lower electrode plate formed in the subsequent process will pass through the conductive plug 225 and the source / drain region. 210 contacts. Please refer to the second C 圊 'compliance to form a shielding layer 2 4 2 on the surface of the second insulating layer 24G. For example, a shielding layer 242 having a thickness of 50˜1000 angstroms is deposited by a low pressure chemical vapor deposition method (LpcvD). The shielding layer 242 extends to the sidewall and the bottom of the second contact window 245. This step is a key step. The shielding layer 242 will play its protective role in the subsequent processes and will be explained in detail in the subsequent related steps. Please refer to FIG. 2D. Next, a third insulating layer 250 is deposited on the surface of the masking layer 242, for example, by chemical vapor deposition (CVD) or atmospheric pressure chemical vapor deposition (APCVD) or sub-normal pressure chemical gas. Phase deposition (SAPaD) or low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDpcv)))

4 2 j 14 6

m) [Glass-free pottery-free impurity sand glass layer, high-density electric t-emulsion layer (OP Oxide) or tetraethoxylate layer (TE0s), preferably the thickness can be 3,000 to 20,000 angstroms, this third Insulation layer 25〇 and fill in the number ;; contact window 2 4 5 ◊ Please refer to Figure 2E, and then define the pattern of the third insulation layer 25, such as 'first coating-photoresist material' after exposure and development process ^ meaning_ The patterned photoresist layer holder 2 is exposed at a position above the second contact window 245. Referring to FIG. 2F, the patterned photoresist layer 25 2 is used as a mask, and a part of the third insulating layer 25 to the surface of the shielding layer 242 in the second contact window 2 to 45 is removed by an anisotropic etching process. A third contact window 255 is formed. Since the second insulating layer 240 is protected by the shielding layer 24 2, the bit line 2 4 6 will not be damaged due to over-etching. "* Please refer to Figure 2G, with the third insulating layer 25 as a shielding mask. Carry out an anisotropic etch process, etch the masking layer 2 4 2 to expose the surface of the conductive plug at the bottom of the third contact window 2 5 5, and etch to remove the third insulating layer 2 50 exposed under the third contact window 255 The shielding layer 242 also forms a sidewall object 242a and 242b on the side wall of the second insulating layer 240 of the third contact window 255. Since this side wall can serve as a barrier to avoid short circuit caused by the lithographic deviation, the bit line 246 is brought into contact with the conductive plug 225 which is subsequently connected to the crown capacitor and the source / drain electrode 21, and then a wet etching process is performed. The shielding layer 24 2 remaining on the bottom of the third contact window 25 5 and the original oxide layer formed on the plug surface are removed. In this process, the side walls 2 4 2 a and 2 4 2 b can also serve as a barrier to ensure the first insulation. Layer 2 40 is not engraved by the surname, protecting the bit line from damage. Referring to FIG. 2H, a second conductive layer 260 is formed to fill the second insulating layer.

My Documents, Winning Bureau \ 87043 ptd Page 13

The inner space surrounded by the side wall objects 242a and 242b of the side wall of the edge layer 24 0 is conformably formed on the surface and the side wall of the third insulating layer 250. The second conductive layer 26 0 may be formed by a low-pressure chemical vapor deposition method. A polycrystalline silicon layer having a thickness of 100 to 3000 angstroms is deposited. Referring to FIG. 21, a photoresist layer 265 is applied and fills the inner space of the third contact window 255. The thickness of the photoresist layer can be 5000-3000 Angstroms. Please refer to FIG. 2J. Next, a planarization step is performed on the photoresist layer 265 to remove the photoresist layer 265 on the surface of the second conductive layer 260 and the second conductive layer 260 on the surface of the third insulating layer 250, leaving the first Photoresist layer 2 6 5 'in the internal space of the three contact windows 255 This planarization step is performed by, for example, a chemical mechanical polishing method.

Row D Please refer to FIG. 2K, and remove the photoresist layer 265 '' in the internal space of the third contact window 255. For example, the photoresist layer 265 'is removed by dry and wet photoresist removal methods. Please refer to FIG. 2L for removing the third insulating layer 2 5 0 on the surface of the shielding layer 242, for example, the third insulating layer 2 5 is removed by a wet etching process. Please refer to FIG. 2M 'to remove the shielding layer 242 on the surface of the second insulating layer 240 to form the electrode plate 26 under the capacitor structure. For example, the shielding layer 242 is removed by a wet etching process. The shielding layer 242 can be used as a screen in this process step 'so that the second insulating layer 240 is not over-etched so as to fully support the crown capacitor structure' so as not to collapse. Then, a dielectric layer 27 is deposited on the lower electrode plate 260, and then an upper electrode plate 28 is deposited on the dielectric layer 27, and the manufacturing of the crown capacitor structure is completed. Another embodiment of the present invention follows the first embodiment to FIG. 2H, and then deposits a fourth insulating layer 2 90 instead of the photoresist layer 2 65. The process steps are as follows:

D _. \ My Documents, Bid Bureau \ 87043. ptd Page 14 V. Description of the Invention (12) Figures 2N to 2p are described as follows: Please refer to Figure 2N, first form a fourth insulating layer 290 on the second The surface of the conductive layer 260 fills the inner space surrounded by the third contact window 2 55, for example, by chemical vapor deposition (CVD) or atmospheric pressure chemical vapor deposition (APCVD) or sub-normal pressure chemical vapor deposition (SAPCVD) ) Or low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD) or high-density plasma chemical vapor deposition (HDPCVD) deposition of a borophosphosilicate glass (BPSG) layer, no doping The thickness of the impurity silica glass layer (NSG), high-density plasma oxide layer (HDP Oxide), or tetraethoxy silicate layer (TE0s) may be 5000-30,000 angstroms. Referring to FIG. 20, a planarization step is applied to the fourth insulating layer 2 90. This planarization step is performed by, for example, a chemical mechanical polishing method. Then, the fourth insulating layer 2 90 on the surface of the second conductive layer 26 and the second conductive layer 26 on the surface of the third insulating layer 240 are sequentially removed, leaving the fourth insulating layer 290 inside the third contact window 255. '. Please refer to FIG. 2P again to remove the fourth insulating layer 2 9 0 ′ inside the third contact window 2 55. For example, the fourth insulating layer 2 90 is removed by a dry etching or wet etching process. The subsequent steps are as described in Figures 2L and 2M, and will not be repeated here. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention as 'any person skilled in the art, without departing from the spirit and scope of the present invention', can make some modifications and retouching. The scope of protection of the invention shall be determined by the scope of the attached patent application.

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Claims (1)

4- 2 3 U 6 6. Scope of Patent Application 1. A manufacturing method of a crown capacitor structure 'The manufacturing method includes the following steps: forming a first insulating layer on a semiconductor substrate having a switching element; and on the first insulating layer A < first contact window is provided to the switching element; a conductive plug is formed on the first contact window to form an electrical connection with the switching element; and a bit is formed above the first insulating layer. Line and a second insulating layer that isolates the bit line; forming a second contact window in the second insulating layer that communicates with the conductive plug; compliantly forming a shielding layer on the surface of the second insulating layer, And extending to the side wall and bottom of the second contact window; forming a third insulating layer on the surface of the shielding layer and filling the second connecting window; defining the third insulating layer to make the third contact of the shielding layer A window; using the third insulating layer as a surface of the shielding plug and forming a curtain on the third contact window; removing the shielding layer to expose the shielding layer The side wall of the second insulation layer forms a surface of three insulation layers on one side and a space; the third contact window is filled with a second conductive layer to cover the second contact window and fill the side wall. A photoresist layer is formed on the surface of the second conductive layer and fills the internal space; 6. The scope of the patent application applies a flattening step to the above photoresist layer, leaving only the portion of the photoresist layer in the third contact window; sequentially removing the photoresist layer, the third insulation layer, and the shielding Layer to leave the above-mentioned second conductive layer to form an electrode plate below the capacitor structure; forming a dielectric layer on the electrode plate below the capacitor structure; and forming an upper electrode plate on the dielectric layer to complete the crown capacitor Manufacturing of structures. 2. The method according to item 1 of the scope of patent application, wherein the semiconductor substrate formed is a crushed substrate. 3. The method according to item 1 of the scope of patent application, wherein the first conductive layer and the second conductive layer formed are composed of polycrystalline silicon, tungsten silicide, metal tungsten, or metal petroxide. 4. The method according to item 1 of the scope of patent application, wherein the shielding layer formed is composed of 1 liter of fossil. 5. The method according to item 1 of the scope of patent application, wherein the thickness of the shielding layer is 50 to 100 angstroms. 6. The method as described in item 1 of the scope of the patent application, wherein the thickness of the third insulating layer formed is 300-3000 Angstroms. 7. The method according to item 1 of the scope of patent application, wherein the thickness of the second conductive layer formed is 100 to 3000 angstroms. 8. The method according to item 1 of the scope of patent application, wherein the thickness of the formed photoresist layer can be 500 0 to 3 00 00 angstroms. 9. A manufacturing method of a crown capacitor structure, the manufacturing method includes the following steps: D: \ My Documents \ Winning Bureau \ 87043 · ptd Page 17 423146 β 6. The scope of the patent application is on a semiconductor substrate with a switching element; the first insulating layer is formed in the first insulating layer-which can be connected to the above switching element-ϊίΐ : Flail touch window to form a conductive plug, # to form a bit line with the above switching element-insulation layer and an insulation layer to isolate the brother; ΐίί formed in the second insulation layer-can be connected to the above conductive plug The second compliance forms a shielding layer on the surface of the upper second insulating layer and extends to the sidewall and bottom of the second contact window; forming a third insulating layer on the surface of the shielding layer and filling the second contact definition The third insulating layer is formed above the conductive plug to form a third contact window exposing the shielding layer; and the third insulating layer is used as a shielding mask to remove the shielding layer to expose the surface of the conductive plug and the conductive plug. The side wall of the second contact layer of the third contact window forms a side Pft. IlJL. · The object is formed to form a conductive layer for covering the surface of the third insulating layer and the third contact window in compliance. And fill the space surrounded by the side wall; form a fourth insulating layer to conformably cover the surface of the second conductive layer and fill the inner space of the third contact window; apply the fourth insulating layer A planarization step, leaving only the fourth insulating layer portion in the third contact window; D: \ My Documents' Winning Bureau \ 87043. ptd Page 18: 2 3 1 4 6 6. Scope of Patent Application The above layers are removed in order to leave a dielectric layer and an upper electrode. ! 〇 If applying for a special conductor substrate is Shi Xi 11. If applying for a dedicated conductive layer and the silicide or metal silicide 12. If applying for a masking layer is made of halogenated 13. If applying for a masking layer thickness of 50 14. If applying for a special third layer The thickness of the insulating layer 15. If the thickness of the second conductive layer is applied 16. If the thickness of the fourth insulation layer is applied U · —a dynamic method, the manufacturer shall form a first insulation formed in the first insulation and the cover formed therein. Covering the fourth insulating layer formed therein, the third insulating layer formed above, the third insulating layer above, and the above-mentioned shielding the second conductive layer to form an electrode plate under the capacitor structure; an electrode under the capacitor structure; Board; and the method described in item 9 of the manufacturing scope of the crown capacitor structure on the dielectric layer, wherein the semi-substrate is formed. The method ′ described in item 9 of the invention, wherein the second conductive layer is formed of a polycrystalline silicon, tungsten silicide, or metal tungsten material. The method described in item 9 of the scope of interest is silicon composition. The method described in item 9 of the scope of interest ~ 1 0 0 0 Angstroms. The method described in item 9 of the profit range is 3000 ~ 30,000 Angstroms. The method described in item 9 of the profit range is 100 ~ 300 0 Angstroms. The method described in item 9 of the profit range may be 5000 to 300,000 Angstroms. The manufacturing method of the crown capacitor structure of the random access memory includes the following steps: The edge layer is formed on a semiconductor substrate with a switching element; the edge layer is formed by a lithography process and an etching process to form a communication layer. D: \ My Documents' Winning Bureau \ 87043 · ptd Page 19 423146 6. Apply for a patent to the above-mentioned switch to deposit the process. The switching element passes through the lithography process to the above-mentioned conductive deposit at a first distance from the bit line. Extend to the first deposition-third window; use the lithography process to electrically plug the third contact above the third plug surface and wall; deposit a second and third contact to coat a photoresist internal space The photoresist layer of the above photoresist sequentially removes the upper element from the second and etched electrical plug layer forming the electrically insulating layer in accordance with the two contact insulating layer first contact window; the first contact connection; the upper half Insulating layer; the second connection on the program covers the side wall of the window to form a conductive plug on the above-mentioned window, and the lithography process and window are defined by the above and the etching procedure; the insulating layer is a shielding cover on the third The contact window is conductive and conforms to the window, and fills the above layer to form a single-digit second insulation layer in the second conductive conductor process to form a contact window; on the surface and bottom of the second insulation layer ; The surface of the shielding layer is filled with the first third insulating layer, and an etching process is performed to form an exposure curtain to etch the shielding layer to expose the side wall of the second insulating layer to cover the surface of the space electrical layer surrounded by the third insulating side wall And fill the first layer with a flattening step, leaving only the third part; the photoresist layer, the third insulating layer, and the above-mentioned shielding line and one separated into a connectable surface, and extended to contact the above two Guide the shielding layer to the surface of one side of the conductive layer and the three-contact window to contact the inner shielding layer of the window to D: \ My Documents, Bid Bureau \ 87043.ptd Page 20 423146 6. The scope of the patent application leaves the above-mentioned second conductive layer to form the electrode plate under the capacitor structure; forming a dielectric layer under the capacitor structure and the electrode A plate; and forming an upper electrode plate on the dielectric layer to complete the manufacture of the crown-shaped capacitor structure. 18. The method according to item 17 of the scope of patent application, wherein the semiconductor substrate formed is a silicon substrate. 19. The method according to item 17 of the scope of the patent application, wherein the first conductive layer and the second conductive layer are formed, #compound crystal or tungsten silicide or metal crane or metal silicide material. 20. The method according to item 17 of the scope of patent application, wherein the shielding layer formed is composed of nitride nitride. 21. The method according to item 17 of the scope of patent application, wherein the thickness of the shielding layer is 50 to 1,000 angstroms. 22. The method according to item 17 in the scope of patent application, wherein the thickness of the third insulating layer formed is 30 00 ~ 30 000 Angstroms. 23. The method according to item 17 in the scope of patent application, 'formed therein The thickness of the second conductive layer is 100 to 300 0 angstroms. 24. According to the method described in item 17 of the scope of patent application, the thickness of the photoresist layer that is applied may be 5,000 to 30,000 angstroms. 25. A method for manufacturing a crown capacitor structure of a dynamic random access memory, the manufacturing method includes the following steps: depositing a first insulating layer on a semiconductor substrate having a switching element; Forming a first contact window which can be connected to the switching element by a lithography process and a money engraving process; D: \ My Documents' Winning Bureau \ 87043.ptd Page 21 ^ 23146 VI. Apply for a patent to deposit an electrical connection on the above-mentioned switching element with a deposition process, and half off the bit line above the above-mentioned insulating layer A second insulation layer is deposited on the second conformance of the second conductive window to the conductive plug by a lithography process and an etching process. A shielding layer is deposited on the side wall and the bottom of the second contact window. The third contact window above the electrical plug is defined by the lithography process and the last name engraving process. The third contact window with the lithography process and the «the third insulating layer is used as a shield plug surface and a second is deposited on the third contact window wall. The conductive layer conforms to the first contact window and fills the side. A fourth insulating layer is deposited to conform and fill the third contact window to apply contact to the fourth insulating layer. The fourth insulating layer portion of the window sequentially removes the photoresist layer, and leaves the second conductive layer to form a window to form a conductive plug, thereby forming a bit line and an isolation section with the upper conductor process. Two insulating layers are formed to form a contactable window; the surface of the first insulating layer extends to the surface of the upper shielding layer and fills the second contacting the third insulating layer, and forms an exposed shielding layer in the above guide procedure. Engraving the shielding layer to expose the conductive side wall of the second insulating layer to form a side covering the space surrounded by the surface of the third insulating layer and the wall; covering the space of the surface portion of the second conductive layer; a planarization step, Leaving only the third and first insulation layers and the above-mentioned shielding potential, with the electrode plate under the capacitor structure; 423146 —— 6. Scope of patent application Form a dielectric layer on the electrode plate below the capacitor structure: and, form an upper electrode plate on the dielectric layer to complete the manufacture of the crown capacitor structure. 26. The method according to item 25 of the scope of patent application, wherein the semiconductor substrate formed by the card is a silicon substrate. 27. The method according to item 25 of the scope of the patent application, wherein the first conductive layer and the second conductive layer formed are composed of polycrystalline spar or broken tungsten or metal tungsten or metal silicide. 28. The method according to item 25 of the scope of the patent application, wherein the shielding layer is formed of silicon nitride. 29. The method according to item 25 of the scope of application for a patent, wherein the thickness of the shielding layer is 50˜1000 Angstroms. 30. The method described in item 25 of the scope of patent application 'wherein the third insulating layer is formed to a thickness of 30 00 ~ 300 00 Angstroms 31. The method described in item 25 of the scope of patent application' where formed The thickness of the second conductive layer is 100-300 Angstroms. 32. The method as described in item 9 of the scope of the patent application, wherein the thickness of the fourth insulating layer formed may be 5,000 to 300,000 angstroms.