US9129562B2 - Emission control line driver and organic light emitting display using the same - Google Patents

Emission control line driver and organic light emitting display using the same Download PDF

Info

Publication number
US9129562B2
US9129562B2 US13/247,945 US201113247945A US9129562B2 US 9129562 B2 US9129562 B2 US 9129562B2 US 201113247945 A US201113247945 A US 201113247945A US 9129562 B2 US9129562 B2 US 9129562B2
Authority
US
United States
Prior art keywords
node
transistor
coupled
input terminal
clock signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US13/247,945
Other versions
US20120176417A1 (en
Inventor
Hwan-Soo Jang
Chang-Soo Pyon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Assigned to SAMSUNG MOBILE DISPLAY CO., LTD. reassignment SAMSUNG MOBILE DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: JANG, HWAN-SOO, PYON, CHANG-SOO
Publication of US20120176417A1 publication Critical patent/US20120176417A1/en
Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. MERGER (SEE DOCUMENT FOR DETAILS). Assignors: SAMSUNG MOBILE DISPLAY CO., LTD.
Application granted granted Critical
Publication of US9129562B2 publication Critical patent/US9129562B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/025—Reduction of instantaneous peaks of current
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • aspects of embodiments according to the present invention relate to an emission control line driver and an organic light emitting display using the same.
  • the FPDs include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display.
  • LCD liquid crystal display
  • FED field emission display
  • PDP plasma display panel
  • organic light emitting display an organic light emitting display
  • the organic light emitting display displays an image using organic light emitting diodes (OLEDs) that generate light by re-combination of electrons and holes.
  • OLEDs organic light emitting diodes
  • the organic light emitting display has a fast response speed and is driven with low power consumption.
  • a typical organic light emitting display supplies current corresponding to data signals to the OLEDs by using transistors formed in pixels so that light is emitted by the OLEDs.
  • the typical organic light emitting display includes a data driver for supplying the data signals to data lines, a scan driver for sequentially supplying scan signals to scan lines, an emission control line driver for supplying emission control signals to emission control lines, and a display unit including a plurality of pixels coupled to the data lines, the scan lines, and the emission control lines.
  • the pixels included in the display unit are selected, when the scan signals are supplied to the scan lines, to receive the data signals from the data lines.
  • the pixels that receive the data signals generate light with brightness (e.g., predetermined brightness) corresponding to the data signals and display a predetermined image.
  • the emission times of the pixels are controlled by the emission control signals that are supplied from the emission control lines.
  • the emission control signals are supplied to overlap the scan signals that are supplied to one scan line or two scan lines to set the pixels, to which the data signals are supplied, in a non-emission state.
  • the emission control line driver includes stages coupled to the emission control lines.
  • the stages receive at least four clock signals and output high or low voltages to output lines.
  • the stages included in the typical emission control line driver are driven by at least four clock signals, a large number of transistors are included. Therefore, manufacturing cost increases and it is difficult to secure the reliability of driving.
  • the emission control line driver is formed of a PMOS transistor, a low level output is unstable.
  • the gate electrode of the transistor that outputs the low signal is maintained at a lower voltage than the low signal.
  • the voltage of the gate electrode of the transistor increases due to leakage current and the output of the low signal is unstable.
  • embodiments of the present invention are directed toward an emission control line driver capable of securing the stability of an output and of freely controlling the width of emission control signals, and an organic light emitting display using the same.
  • an emission control line driver including a plurality of stages. Each of the stages includes a first transistor coupled between a first output terminal and a first power source, the first transistor being configured to be turned on or off to correspond to a voltage applied to a first node that is coupled to a gate electrode of the first transistor, a second transistor coupled between the first output terminal and a second power source that outputs a voltage that is lower than the first power source, the second transistor being configured to be turned on or off to correspond to a voltage applied to a second node that is coupled to a gate electrode of the second transistor, a third transistor coupled between a fourth input terminal and the first node, and having a gate electrode coupled to a first input terminal, a fourth transistor coupled between the first power source and the second node, and having a gate electrode coupled to the first node, a first controller coupled to the first input terminal and a second input terminal to supply a sampling signal to a second output terminal, a second controller coupled to the first input terminal and a
  • the emission control line driver may further include a second capacitor coupled between the first node and the first power source.
  • the first input terminal may be configured to receive a first clock signal.
  • the second input terminal may be configured to receive a second clock signal.
  • the third input terminal may be configured to receive a third clock signal.
  • the fourth input terminal may be configured to receive a start signal or a sampling signal of a previous stage.
  • the first clock signal, the second clock signal, and the third clock signal may not overlap each other.
  • Each of the first clock signal and the second clock signal may be set in a period of i (i is a natural number) horizontal periods.
  • the third clock signal may be set in a period of i/2 horizontal periods.
  • the third clock signal may be supplied in a horizontal period after the first clock signal or the second clock signal is supplied in the horizontal period.
  • the first controller may include a fifth transistor coupled between the fourth input terminal and a third node, and having a gate electrode coupled to the first input terminal, a sixth transistor coupled between a sixth node and the second input terminal, and having a gate electrode coupled to the third node, a seventh transistor coupled between the sixth node and the first power source, and having a gate electrode coupled to the first output terminal, a third capacitor coupled between the third node and the sixth node, and a fourth capacitor coupled between the first output terminal and the first power source.
  • the second output terminal may be electrically coupled to the sixth node.
  • the second controller may include an eighth transistor coupled between the first input terminal and a fourth node, and having a gate electrode coupled to the first node, a ninth transistor coupled between the fourth node and the second power source, and having a gate electrode coupled to the first input terminal, a tenth transistor coupled between the second node and a fifth node, and having a gate electrode coupled to the third input terminal, an eleventh transistor coupled between the fifth node and the third input terminal, and having a gate electrode coupled to the fourth node, and a fifth capacitor coupled between the fourth node and the fifth node.
  • the emission control line driver may further include a twelfth transistor coupled between the fourth input terminal and the third transistor, the twelfth transistor being configured to be turned on when a first control signal is supplied to a gate electrode of the twelfth transistor, and a thirteenth transistor coupled between a fifth input terminal and the first controller, the thirteenth transistor being configured to be turned on when a second control signal is supplied to a gate electrode of the thirteenth transistor.
  • the first control signal and the second control signal may not overlap each other.
  • the emission control line driver may further include a fourteenth transistor coupled between the first node and the second power source, the fourteenth transistor being configured to be turned on when a reset signal is supplied to a gate electrode of the fourteenth transistor.
  • the reset signal may be commonly supplied to all of the stages.
  • an organic light emitting display includes a scan driver for sequentially supplying scan signals to scan lines, a data driver for supplying data signals to data lines, an emission control line driver for supplying emission control signals to emission control lines, and pixels positioned at crossing regions of the scan lines, the data lines, and the emission control lines.
  • the emission control line driver includes stages respectively coupled to the emission control lines.
  • Each of the stages includes a first transistor coupled between a first output terminal and a first power source, the first transistor being configured to be turned on or off to correspond to a voltage applied to a first node that is coupled to a gate electrode of the first transistor, a second transistor coupled between the first output terminal and a second power source that outputs a voltage that is lower than the first power source, the second transistor being configured to be turned on or off to correspond to a voltage applied to a second node that is coupled to a gate electrode of the second transistor, a third transistor coupled between a fourth input terminal and the first node, and having a gate electrode coupled to a first input terminal, a fourth transistor coupled between the first power source and the second node, and having a gate electrode coupled to the first node, a first controller coupled to the first input terminal and a second input terminal to supply a sampling signal to a second output terminal, a second controller coupled to the first input terminal and a third input terminal to control the voltage of the second node, and a first capacitor coupled between the second input terminal
  • the voltage of the gate electrode of the transistor that outputs the low signal is periodically reduced using the clock signal so that the stability of an output may be secured.
  • the width of the emission control signal may be controlled to correspond to the width of the start signal.
  • FIG. 1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention
  • FIG. 2 is a block diagram schematically illustrating stages of an emission control line driver of FIG. 1 ;
  • FIG. 3 is a circuit diagram illustrating a first embodiment of one of the stages of FIG. 2 ;
  • FIG. 4 is a waveform chart illustrating the operation processes of one of the stages of FIG. 3 ;
  • FIG. 5 is a circuit diagram illustrating a second embodiment of one of the stages of FIG. 2 ;
  • FIG. 6 is a circuit diagram illustrating a third embodiment of one of the stages of FIG. 2 .
  • first element when a first element is described as being coupled to a second element, the first element may be directly coupled to the second element or may be indirectly coupled to the second element via one or more third elements. Further, some of the elements that are not essential to the complete understanding of the invention are omitted for clarity. Also, like reference numerals refer to like elements throughout.
  • FIGS. 1 to 6 exemplary embodiments of the present invention, by which those skilled in the art may perform the present invention, will be described in detail with reference to FIGS. 1 to 6 .
  • FIG. 1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention.
  • the organic light emitting display includes a display unit 40 that includes pixels 50 positioned at the crossing regions of scan lines S 1 to Sn, data lines D 1 to Dm, and emission control lines E 1 to En, a scan driver 10 for driving the scan lines S 1 to Sn, a data driver 20 for driving the data lines D 1 to Dm, an emission control line driver 30 for driving the emission control lines E 1 to En, and a timing controller 60 for controlling the drivers 10 , 20 , and 30 .
  • the scan driver 10 sequentially supplies scan signals to the scan lines S 1 to Sn.
  • the pixels 50 are selected in units of horizontal lines (e.g., line-by-line).
  • the data driver 20 supplies data signals to the data lines D 1 to Dm in synchronization with the scan signals.
  • the data signals supplied to the data lines D 1 to Dm are supplied to the pixels 50 that are selected by the scan signals.
  • the emission control line driver 30 sequentially supplies emission control signals to the emission control lines E 1 to En.
  • the emission control line driver 30 supplies the emission control signals so that the pixels 50 are set in a non-emission state during a period when the voltages corresponding to the data signals are charged. Therefore, the emission control signal supplied to the i th (i is a natural number) emission control line E i overlaps the scan signal supplied to the i th scan line S i .
  • the width of the emission control signal may be suitably set to correspond to the structure of the pixel 50 and the brightness to be realized.
  • FIG. 2 is a block diagram schematically illustrating stages of the emission control line driver of FIG. 1 .
  • the emission control line driver 30 includes n stages 321 to 32 n in order to supply emission control signals to the n emission control lines E 1 to En.
  • the stages 321 to 32 n are coupled to the emission control lines E 1 to En, respectively, and are driven by three clock signals CLK 1 , CLK 2 , and CLK 3 .
  • Each of the stages 321 to 32 n includes a first input terminal 33 , a second input terminal 34 , a third input terminal 35 , and a fourth input terminal 36 .
  • the first input terminal 33 of a k th (k is an odd or even number) stage 32 k receives the first clock signal CLK 1 and the second input terminal 34 receives the second clock signal CLK 2 .
  • the first input terminal 33 of a (k+1) th stage 32 k +1 receives the second clock signal CLK 2
  • the second input terminal 34 receives the first clock signal CLK 1 .
  • the third clock signal CLK 3 is supplied to the third input terminal 35 of each of the stages 321 to 32 n , and a start signal FLM or a sampling signal of a previous stage is supplied to the fourth input terminal 36 .
  • the stages 321 to 32 n may be formed of the same circuit and generate the emission control signals having width that is changed to correspond to the start signal FLM.
  • FIG. 3 is a circuit diagram illustrating a first embodiment of one of the stages of FIG. 2 .
  • the first stage 321 will be illustrated.
  • the stage 321 includes a first transistor M 1 , a second transistor M 2 , a third transistor M 3 , a fourth transistor M 4 , a first capacitor C 1 , a second capacitor C 2 , a first controller 100 , and a second controller 102 .
  • the first transistor M 1 is coupled between a first output terminal 37 and a first power source VDD.
  • the gate electrode of the first transistor M 1 is coupled to a first node N 1 .
  • the first transistor M 1 controls the voltage of the first output terminal 37 to correspond to the voltage applied to the first node N 1 .
  • the first power source VDD e.g., a high voltage
  • the high voltage supplied to the first output terminal 37 is used as an emission control signal.
  • the second transistor M 2 is coupled between the first output terminal 37 and a second power source VSS.
  • the gate electrode of the second transistor M 2 is coupled to a second node N 2 .
  • the second transistor M 2 controls the voltage of the first output terminal 37 to correspond to the voltage applied to the second node N 2 .
  • the second power source VSS e.g., a low voltage
  • the third transistor M 3 is coupled between the fourth input terminal 36 and the first node N 1 .
  • the gate electrode of the third transistor M 3 is coupled to the first input terminal 33 .
  • the third transistor M 3 is turned on or off to correspond to the first clock signal CLK 1 supplied to the first input terminal 33 .
  • the third transistor M 3 is turned on, the fourth input terminal 36 and the first node N 1 are electrically coupled to each other.
  • the start signal FLM (or a previous stage sampling signal) is supplied to the fourth input terminal 36 , the first transistor M 1 is turned on.
  • the fourth transistor M 4 is coupled between the first power source VDD and the second node N 2 .
  • the gate electrode of the fourth transistor M 4 is coupled to the first node N 1 .
  • the fourth transistor M 4 is turned on or off to correspond to the voltage that is applied to the first node N 1 in order to control the voltage of the second node N 2 . That is, the fourth transistor M 4 is turned on when a low voltage is applied to the first node N 1 in order to supply the voltage of the first power source VDD to the second node N 2 .
  • the low voltage is supplied to the first node N 1
  • the high voltage of the first power source VDD is supplied to the second node N 2 so that the first transistor M 1 and the second transistor M 2 are turned on or off at different times.
  • the first capacitor C 1 is coupled between the second input terminal 34 and the second node N 2 .
  • the first capacitor C 1 controls the voltage of the second node N 2 to correspond to the second clock signal CLK 2 supplied to the second input terminal 34 .
  • the operation processes of the first capacitor C 1 will be described later in more detail.
  • the second capacitor C 2 is coupled between the first node N 1 and the first power source VDD.
  • the second capacitor C 2 is charged with the voltage corresponding to the turning on or off of the first transistor M 1 .
  • a first controller 100 supplies a sampling signal to a second output terminal 38 to correspond to the first clock signal CLK 1 and the second clock signal CLK 2 . Therefore, the first controller 100 includes a fifth transistor M 5 , a sixth transistor M 6 , a seventh transistor M 7 , a third capacitor C 3 , and a fourth capacitor C 4 .
  • the fifth transistor M 5 is coupled between the fourth input terminal 36 and a third node N 3 .
  • the gate electrode of the fifth transistor M 5 is coupled to the first input terminal 33 .
  • the fifth transistor M 5 is turned on or off to correspond to the first clock signal CLK 1 supplied to the first input terminal 33 in order to control the voltage of the third node N 3 .
  • the sixth transistor M 6 is coupled between a sixth node N 6 and the second input terminal 34 .
  • the gate electrode of the sixth transistor M 6 is coupled to the third node N 3 .
  • the sixth transistor M 6 controls the voltage of the sixth node N 6 to correspond to the voltage applied to the third node N 3 .
  • the seventh transistor M 7 is coupled between the first power source VDD and the sixth node N 6 .
  • the gate electrode of the seventh transistor M 7 is coupled to the first output terminal 37 .
  • the seventh transistor M 7 is turned on or off to correspond to the voltage applied to the first output terminal 37 in order to control the voltage of the sixth node N 6 .
  • the third capacitor C 3 is coupled between the third node N 3 and the sixth node N 6 .
  • the third capacitor C 3 is charged with the voltage corresponding to the turning on or turning off of the sixth transistor M 6 .
  • the fourth capacitor C 4 is coupled between the first power source VDD and the first output terminal 37 .
  • the fourth capacitor C 4 is charged with the voltage corresponding to the turning on or off of the seventh transistor M 7 .
  • the second output terminal 38 is coupled to the sixth node N 6 .
  • the second output terminal 38 supplies the voltage applied to the sixth node N 6 as a sampling signal to a next stage 322 .
  • the second controller 102 controls the voltage of the second node N 2 to correspond to the first clock signal CLK 1 and the third clock signal CLK 3 .
  • the second controller 102 maintains the voltage of the second node N 2 as a low voltage.
  • the second controller 102 includes an eighth transistor M 8 , a ninth transistor M 9 , a tenth transistor M 10 , an eleventh transistor M 11 , and a fifth capacitor C 5 .
  • the eighth transistor M 8 is coupled between the first input terminal 33 and a fourth node N 4 .
  • the gate electrode of the eighth transistor M 8 is coupled to the first node N 1 .
  • the eighth transistor M 8 is turned on or off to correspond to the voltage applied to the first node N 1 in order to control the voltage of the fourth node N 4 .
  • the ninth transistor M 9 is coupled between the fourth node N 4 and the second power source VSS.
  • the gate electrode of the ninth transistor M 9 is coupled to the first input terminal 33 .
  • the ninth transistor M 9 is turned on or off to correspond to the first clock signal CLK 1 supplied to the first input terminal 33 in order to control the voltage of the fourth node N 4 .
  • the tenth transistor M 10 is coupled between the second node N 2 and a fifth node N 5 .
  • the gate electrode of the tenth transistor M 10 is coupled to a third input terminal 35 .
  • the tenth transistor M 10 is turned on or off to correspond to the third clock signal CLK 3 supplied to the third input terminal 35 in order to control the voltage of the second node N 2 .
  • the eleventh transistor M 11 is coupled between the fifth node N 5 and the third input terminal 35 .
  • the gate electrode of the eleventh transistor M 11 is coupled to the fourth node N 4 .
  • the eleventh transistor M 11 is turned on or off to correspond to the voltage applied to the fourth node N 4 in order to control the voltage of the fifth node N 5 .
  • the fifth capacitor C 5 is coupled between the fourth node N 4 and the fifth node N 5 .
  • the fifth capacitor C 5 is charged with the voltage corresponding to the turning on or off of the eleventh transistor M 11 .
  • FIG. 4 is a waveform chart illustrating the operation processes of the stage of FIG. 3 .
  • the first clock signal CLK 1 and the second clock signal CLK 2 are supplied in the period of iH (i is a natural number, e.g., a horizontal period), and the third clock signal CLK 3 is supplied in the period of i/2H.
  • i is a natural number, e.g., a horizontal period
  • CLK 3 is supplied in the period of i/2H.
  • the first clock signal CLK 1 and the second clock signal CLK 2 are set in the period of 2H and the third clock signal CLK 3 is set in the period of 1H.
  • the first clock signal CLK 1 and the second clock signal CLK 2 are supplied in different horizontal periods H, and the third clock signal CLK 3 is supplied every horizontal period H so that the first clock signal CLK 1 does not overlap the third clock signal CLK 3 . Then, in the horizontal period H, after the first clock signal CLK 1 or the second clock signal CLK 2 is supplied, the third clock signal CLK 3 is supplied. That is, in an exemplary horizontal period, the third clock signal CLK 3 is supplied after the first clock signal CLK 1 is supplied. In the next horizontal period, the third clock signal CLK 3 is supplied after the second clock signal CLK 2 is supplied.
  • the start signal FLM (e.g., the low signal) is supplied to the fourth input terminal 36 .
  • the first clock signal CLK 1 is supplied to the first input terminal 33 .
  • the third transistor M 3 , the fifth transistor M 5 , and the ninth transistor M 9 are turned on.
  • the start signal FLM is supplied to the first node N 1 .
  • the start signal FLM is supplied to the first node N 1 , the first transistor M 1 , the fourth transistor M 4 , and the eighth transistor M 8 are turned on.
  • the first transistor M 1 When the first transistor M 1 is turned on, the voltage corresponding to the turning on of the first transistor M 1 is charged at the second capacitor C 2 .
  • the first transistor M 1 When the first transistor M 1 is turned on, the voltage of the first power source VDD is supplied to the first output terminal 37 . In this case, the emission control signal is supplied to the emission control line E 1 .
  • the fourth transistor M 4 When the fourth transistor M 4 is turned on, the first power source VDD is supplied to the second node N 2 .
  • the second transistor M 2 When the first power source VDD is supplied to the second node N 2 , the second transistor M 2 is turned off.
  • the first power source VDD may be stably supplied to the first output terminal 37 .
  • the eighth transistor M 8 When the eighth transistor M 8 is turned on, the fourth node N 4 and the first input terminal 33 are electrically coupled to each other.
  • the fourth node N 4 since the first clock signal CLK 1 is supplied to the first input terminal 33 , the fourth node N 4 receives a low voltage.
  • the start signal is supplied to the third node N 3 .
  • the sixth transistor M 6 is turned on.
  • the sixth node N 6 and the second input terminal 34 are electrically coupled to each other.
  • the second clock signal CLK 2 is not supplied to the second input terminal 34 , the sixth node N 6 maintains a high voltage so that a sampling signal is not supplied to the second output terminal 38 .
  • the sixth transistor M 6 is turned on, the voltage corresponding to the turning on of the sixth transistor M 6 is charged at the third capacitor C 3 .
  • the ninth transistor M 9 When the ninth transistor M 9 is turned on, the voltage of the second power source VSS is supplied to the fourth node N 4 .
  • the eleventh transistor M 11 When the second power source VSS is supplied to the fourth node N 4 , the eleventh transistor M 11 is turned on.
  • the eleventh transistor M 11 When the eleventh transistor M 11 is turned on, the fifth node N 5 and the third input terminal 35 are electrically coupled to each other.
  • the fifth node N 5 maintains a high voltage.
  • the eleventh transistor M 11 since the eleventh transistor M 11 is turned on, the voltage corresponding to the turning on of the eleventh transistor is charged at the fifth capacitor C 5 .
  • the supply of the first clock signal CLK 1 to the first input terminal 33 is stopped.
  • the third transistor M 3 , the fifth transistor M 5 , and the ninth transistor M 9 are turned off.
  • the fourth input terminal 36 and the first node N 1 are electrically isolated from each other.
  • the first node N 1 maintains a low voltage by the second capacitor C 2 . Therefore, the first transistor M 1 maintains a turn on state so that the voltage of the first power source VDD is output to the first output terminal 37 . Since the fourth transistor M 4 maintains a turn on state by the voltage of the second capacitor C 2 , the second transistor M 2 stably maintains a turn off state.
  • the sixth transistor M 6 maintains a turn on state to correspond to the voltage charged at the third capacitor C 3 so that the second output terminal 38 maintains a previous voltage.
  • the ninth transistor M 9 When the ninth transistor M 9 is turned off, the fourth node N 4 and the second power source VSS are electrically isolated from each other.
  • the eighth transistor M 8 since the eighth transistor M 8 maintains a turned on state to correspond to the voltage applied to the first node N 1 , the fourth node N 4 and the first input terminal 33 are electrically coupled to each other. Therefore, the voltage of the fourth node N 4 increases to the voltage supplied to the first input terminal 33 (e.g., the voltage of a high signal).
  • the eleventh transistor M 11 When the fourth node N 4 receives the voltage of the high signal, the eleventh transistor M 11 is turned off.
  • the fifth capacitor C 5 is charged with the voltage corresponding to the turning off of the eleventh transistor M 11 .
  • the third clock signal CLK 3 is supplied to the third input terminal 35 .
  • the tenth transistor M 10 is turned on.
  • the second node N 2 and the fifth node N 5 are electrically coupled to each other.
  • the fourth transistor M 4 maintains a turned on state and the eleventh transistor M 11 maintains a turned off state, the second node N 2 maintains the voltage of the first power source VDD.
  • the second clock signal CLK 2 is supplied to the second input terminal 34 in the next horizontal period.
  • the sixth transistor M 6 since the sixth transistor M 6 is set in a turn on state, the second clock signal CLK 2 is supplied to the sixth node N 6 .
  • the second clock signal CLK 2 supplied to the sixth node N 6 as a sampling signal is supplied to the next stage via the second output terminal 38 .
  • the voltage of the third node N 3 is reduced by the coupling of the third capacitor C 3 . Therefore, the sixth transistor M 6 stably maintains a turned on state.
  • the second clock signal CLK 2 supplied to the second input terminal 34 is transmitted to the second node N 2 by the coupling of the first capacitor C 1 .
  • the second node N 2 since the second node N 2 receives the first power source VDD, the voltage of the first power source VDD is maintained without a change in a voltage.
  • the third clock signal CLK 3 is supplied to the third input terminal 35 .
  • the tenth transistor M 10 is turned on.
  • the second node N 2 and the fifth node N 5 are electrically coupled to each other.
  • the fourth transistor M 4 maintains a turned on state and the eleventh transistor M 11 maintains a turned off state, the second node N 2 maintains the voltage of the first power source VDD.
  • the supply of the start signal FLM is stopped (e.g., a high voltage) in the next horizontal period, and the first clock signal CLK 1 is supplied to the first input terminal 33 .
  • the third transistor M 3 When the first clock signal CLK 1 is supplied, the third transistor M 3 , the fifth transistor M 5 , and the ninth transistor M 9 are turned on.
  • the third transistor M 3 When the third transistor M 3 is turned on, the first node N 1 and the fourth input terminal 36 are electrically coupled to each other.
  • the first transistor M 1 , the fourth transistor M 4 , and the eighth transistor M 8 are turned off.
  • the first output terminal 37 When the first transistor M 1 is turned off, the first output terminal 37 is set in a floating state. In this case, the first output terminal 37 maintains the high voltage that is an output signal of a previous period.
  • the emission control signal supplied to the emission control line E 1 is supplied to the pixels 50 , charging is performed by the capacitors of the pixels. Therefore, although the first output terminal 37 is set in a floating state, the output voltage of a previous period is maintained by the parasitic capacitors of the pixels 50 and the emission control line.
  • the fifth transistor M 5 When the fifth transistor M 5 is turned on, a high voltage is supplied to the third node N 3 so that the sixth transistor M 6 is turned off.
  • the sixth transistor M 6 When the sixth transistor M 6 is turned off, the sixth node N 6 and the second input terminal 34 are electrically isolated from each other.
  • the third capacitor C 3 is charged with the voltage corresponding to the turning off of the sixth transistor M 6 .
  • the fourth node N 4 and the second power source VSS are electrically coupled to each other.
  • the fourth node N 4 receives the voltage of the second power source VSS so that the eleventh transistor M 11 is turned on.
  • the eleventh transistor M 1 is turned on, the fifth node N 5 and the third input terminal 35 are electrically coupled to each other.
  • the voltage corresponding to the turning on of the eleventh transistor M 11 is stored at the fifth capacitor C 5 .
  • the third clock signal CLK 3 is supplied to the third input terminal 35 .
  • the tenth transistor M 10 is turned on.
  • the second node N 2 and the third input terminal 35 are electrically coupled to each other via the fifth node N 5 .
  • the third clock signal CLK 3 (e.g., a low voltage) is supplied to the second node N 2 .
  • the second transistor M 2 is turned on so that the voltage of the second power source VSS is output to the first output terminal 37 . In this case, the supply of the emission control signal to the emission control line E 1 is stopped.
  • the seventh transistor M 7 is turned on.
  • the voltage of the first power source VDD is supplied to the sixth node N 6 .
  • the third clock signal CLK 3 may be set as a voltage lower than the second power source VSS so that the second transistor M 2 may be stably turned on. Then, the stage 321 outputs the voltage of the first power source VDD to the first output terminal 37 until the next start signal FLM is supplied.
  • the voltage of the second node N 2 is reduced by the coupling of the first capacitor C 1 . Therefore, the voltage of the second node N 2 stably maintains a low voltage so that the voltage of the second power source VSS may be stably output to the first output terminal 37 .
  • a sampling signal is supplied to the next stage in synchronization with the second clock signal CLK 2 (In the next stage, the second clock signal CLK 2 is supplied to the first input terminal). In this case, the next stage stably outputs the emission control signal using the sampling signal.
  • FIG. 4 it is illustrated that one sampling signal is generated to correspond to the start signal FLM.
  • the present invention is not limited to the above.
  • the width of the start signal FLM is controlled so that the width of the emission control signal may be freely controlled.
  • FIG. 5 is a circuit diagram illustrating a second embodiment of the stage of FIG. 2 .
  • the same elements as those of FIG. 3 are denoted by the same reference numerals and detailed description thereof will be omitted.
  • the stage 321 further includes a twelfth transistor M 12 and a thirteenth transistor M 13 for bidirectional driving.
  • the twelfth transistor M 12 is coupled between the fourth input terminal 36 and the third transistor M 3 .
  • the gate electrode of the twelfth transistor M 12 receives a first control signal CS 1 .
  • the twelfth transistor M 12 is turned on when the first control signal CS 1 is supplied.
  • the thirteenth transistor M 13 is coupled between a fifth input terminal 39 and the fifth transistor M 5 (or a first controller 100 ). Then, the gate electrode of the thirteenth transistor M 13 receives a second control signal CS 2 . The thirteenth transistor M 13 is turned on when the second control signal CS 2 is supplied.
  • the fifth input terminal 39 receives the start signal or the sampling signal of the next stage.
  • the first control signal CS 1 and the second control signal CS 2 are supplied at different times (e.g., not overlapped with each other). For example, when the emission control signals are supplied in a first direction (from top to bottom of a panel), the first control signal CS 1 is supplied so that the twelfth transistor M 12 is turned on and so that the thirteenth transistor M 13 maintains a turned off state. When the emission control signals are supplied in a second direction (from bottom to top of the panel), the second control signal CS 2 is supplied so that the thirteenth transistor M 13 is turned on and so that the twelfth transistor M 12 maintains a turned off state.
  • the stage 321 further includes the twelfth transistor M 12 and the thirteenth transistor M 13 for bidirectional driving, and the operation processes are substantially the same as the first embodiment illustrated in FIG. 3 .
  • FIG. 6 is a circuit diagram illustrating a third embodiment of the stage of FIG. 2 .
  • the same elements as those of FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.
  • the stage 321 further includes a fourteenth transistor M 14 coupled between the first node N 1 and the second power source VSS.
  • the fourteenth transistor M 14 is turned on to supply the voltage of the second power source VSS to the first node N 1 when a reset signal (Reset) is supplied to the gate of the fourteenth transistor M 14 .
  • the first transistor M 1 is turned on so that the voltage of the first power source VDD is supplied to the first output terminal 37 .
  • the reset signal (Reset) is commonly supplied to all of the stages 321 to 32 n when a power source is turned on and/or off.
  • the emission control signals are supplied to the emission control lines E 1 to En so that the pixels 50 are set in a non-emission state. That is, according to the third embodiment of the present invention, it is possible to prevent over-current from flowing or unnecessary light from being generated when the power source is turned on and/or off using the reset signal.
  • the third clock signal CLK 3 is supplied to all of the stages 321 to 32 n .
  • the present invention is not limited to the above.
  • the third clock signal CLK 3 may be supplied to even and odd stages via different lines. Then, the load of the third clock signal CLK 3 is minimized or reduced so that the stability of driving the stages may be improved.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

An emission control line driver is capable of securing the stability of an output and of freely controlling the width of emission control signals. The emission control line driver includes a plurality of stages respectively coupled to emission control lines. Each of the stages includes a plurality of transistors that are configured to output the emission control signal. The width of the emission control signal may be controlled to correspond to the width of a start signal. Furthermore, a circuit structure of the stages is simplified.

Description

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority to and the benefit of Korean Patent Application No. 10-2011-0001419, filed on Jan. 6, 2011, in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.
BACKGROUND
1. Field
Aspects of embodiments according to the present invention relate to an emission control line driver and an organic light emitting display using the same.
2. Description of the Related Art
Recently, various flat panel displays (FPDs) with reduced weight and volume as compared to cathode ray tube (CRT) displays have been developed. The FPDs include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic light emitting display.
Among the FPDs, the organic light emitting display displays an image using organic light emitting diodes (OLEDs) that generate light by re-combination of electrons and holes. The organic light emitting display has a fast response speed and is driven with low power consumption. A typical organic light emitting display supplies current corresponding to data signals to the OLEDs by using transistors formed in pixels so that light is emitted by the OLEDs.
The typical organic light emitting display includes a data driver for supplying the data signals to data lines, a scan driver for sequentially supplying scan signals to scan lines, an emission control line driver for supplying emission control signals to emission control lines, and a display unit including a plurality of pixels coupled to the data lines, the scan lines, and the emission control lines.
The pixels included in the display unit are selected, when the scan signals are supplied to the scan lines, to receive the data signals from the data lines. The pixels that receive the data signals generate light with brightness (e.g., predetermined brightness) corresponding to the data signals and display a predetermined image. Here, the emission times of the pixels are controlled by the emission control signals that are supplied from the emission control lines. In general, the emission control signals are supplied to overlap the scan signals that are supplied to one scan line or two scan lines to set the pixels, to which the data signals are supplied, in a non-emission state.
Therefore, the emission control line driver includes stages coupled to the emission control lines. The stages receive at least four clock signals and output high or low voltages to output lines.
However, since the stages included in the typical emission control line driver are driven by at least four clock signals, a large number of transistors are included. Therefore, manufacturing cost increases and it is difficult to secure the reliability of driving. In addition, when the emission control line driver is formed of a PMOS transistor, a low level output is unstable.
To be specific, when a low signal is supplied to an emission control line, the gate electrode of the transistor that outputs the low signal is maintained at a lower voltage than the low signal. However, the voltage of the gate electrode of the transistor increases due to leakage current and the output of the low signal is unstable.
SUMMARY
Accordingly, embodiments of the present invention are directed toward an emission control line driver capable of securing the stability of an output and of freely controlling the width of emission control signals, and an organic light emitting display using the same.
According to an embodiment of the present invention, there is provided an emission control line driver including a plurality of stages. Each of the stages includes a first transistor coupled between a first output terminal and a first power source, the first transistor being configured to be turned on or off to correspond to a voltage applied to a first node that is coupled to a gate electrode of the first transistor, a second transistor coupled between the first output terminal and a second power source that outputs a voltage that is lower than the first power source, the second transistor being configured to be turned on or off to correspond to a voltage applied to a second node that is coupled to a gate electrode of the second transistor, a third transistor coupled between a fourth input terminal and the first node, and having a gate electrode coupled to a first input terminal, a fourth transistor coupled between the first power source and the second node, and having a gate electrode coupled to the first node, a first controller coupled to the first input terminal and a second input terminal to supply a sampling signal to a second output terminal, a second controller coupled to the first input terminal and a third input terminal to control the voltage of the second node, and a first capacitor coupled between the second input terminal and the second node.
The emission control line driver may further include a second capacitor coupled between the first node and the first power source. The first input terminal may be configured to receive a first clock signal. The second input terminal may be configured to receive a second clock signal. The third input terminal may be configured to receive a third clock signal. The fourth input terminal may be configured to receive a start signal or a sampling signal of a previous stage. The first clock signal, the second clock signal, and the third clock signal may not overlap each other. Each of the first clock signal and the second clock signal may be set in a period of i (i is a natural number) horizontal periods. The third clock signal may be set in a period of i/2 horizontal periods. The third clock signal may be supplied in a horizontal period after the first clock signal or the second clock signal is supplied in the horizontal period.
The first controller may include a fifth transistor coupled between the fourth input terminal and a third node, and having a gate electrode coupled to the first input terminal, a sixth transistor coupled between a sixth node and the second input terminal, and having a gate electrode coupled to the third node, a seventh transistor coupled between the sixth node and the first power source, and having a gate electrode coupled to the first output terminal, a third capacitor coupled between the third node and the sixth node, and a fourth capacitor coupled between the first output terminal and the first power source. The second output terminal may be electrically coupled to the sixth node.
The second controller may include an eighth transistor coupled between the first input terminal and a fourth node, and having a gate electrode coupled to the first node, a ninth transistor coupled between the fourth node and the second power source, and having a gate electrode coupled to the first input terminal, a tenth transistor coupled between the second node and a fifth node, and having a gate electrode coupled to the third input terminal, an eleventh transistor coupled between the fifth node and the third input terminal, and having a gate electrode coupled to the fourth node, and a fifth capacitor coupled between the fourth node and the fifth node.
The emission control line driver may further include a twelfth transistor coupled between the fourth input terminal and the third transistor, the twelfth transistor being configured to be turned on when a first control signal is supplied to a gate electrode of the twelfth transistor, and a thirteenth transistor coupled between a fifth input terminal and the first controller, the thirteenth transistor being configured to be turned on when a second control signal is supplied to a gate electrode of the thirteenth transistor. The first control signal and the second control signal may not overlap each other. The emission control line driver may further include a fourteenth transistor coupled between the first node and the second power source, the fourteenth transistor being configured to be turned on when a reset signal is supplied to a gate electrode of the fourteenth transistor. The reset signal may be commonly supplied to all of the stages.
According to an embodiment, an organic light emitting display includes a scan driver for sequentially supplying scan signals to scan lines, a data driver for supplying data signals to data lines, an emission control line driver for supplying emission control signals to emission control lines, and pixels positioned at crossing regions of the scan lines, the data lines, and the emission control lines. The emission control line driver includes stages respectively coupled to the emission control lines. Each of the stages includes a first transistor coupled between a first output terminal and a first power source, the first transistor being configured to be turned on or off to correspond to a voltage applied to a first node that is coupled to a gate electrode of the first transistor, a second transistor coupled between the first output terminal and a second power source that outputs a voltage that is lower than the first power source, the second transistor being configured to be turned on or off to correspond to a voltage applied to a second node that is coupled to a gate electrode of the second transistor, a third transistor coupled between a fourth input terminal and the first node, and having a gate electrode coupled to a first input terminal, a fourth transistor coupled between the first power source and the second node, and having a gate electrode coupled to the first node, a first controller coupled to the first input terminal and a second input terminal to supply a sampling signal to a second output terminal, a second controller coupled to the first input terminal and a third input terminal to control the voltage of the second node, and a first capacitor coupled between the second input terminal and the second node.
According to the emission control line driver illustrated in the embodiments of the present invention and the organic light emitting display using the same, the voltage of the gate electrode of the transistor that outputs the low signal is periodically reduced using the clock signal so that the stability of an output may be secured. In addition, according to the embodiments of the present invention, the width of the emission control signal may be controlled to correspond to the width of the start signal. Furthermore, according to the embodiments of the present invention, since the stages receive three clock signals, a circuit structure may be simplified.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, together with the specification, illustrate exemplary embodiments of the present invention, and, together with the description, serve to explain the principles of the present invention.
FIG. 1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention;
FIG. 2 is a block diagram schematically illustrating stages of an emission control line driver of FIG. 1;
FIG. 3 is a circuit diagram illustrating a first embodiment of one of the stages of FIG. 2;
FIG. 4 is a waveform chart illustrating the operation processes of one of the stages of FIG. 3;
FIG. 5 is a circuit diagram illustrating a second embodiment of one of the stages of FIG. 2; and
FIG. 6 is a circuit diagram illustrating a third embodiment of one of the stages of FIG. 2.
 DETAILED DESCRIPTION
Hereinafter, certain exemplary embodiments according to the present invention will be described with reference to the accompanying drawings. Here, when a first element is described as being coupled to a second element, the first element may be directly coupled to the second element or may be indirectly coupled to the second element via one or more third elements. Further, some of the elements that are not essential to the complete understanding of the invention are omitted for clarity. Also, like reference numerals refer to like elements throughout.
Hereinafter, exemplary embodiments of the present invention, by which those skilled in the art may perform the present invention, will be described in detail with reference to FIGS. 1 to 6.
FIG. 1 is a block diagram illustrating an organic light emitting display according to an embodiment of the present invention.
Referring to FIG. 1, the organic light emitting display according to an embodiment of the present invention includes a display unit 40 that includes pixels 50 positioned at the crossing regions of scan lines S1 to Sn, data lines D1 to Dm, and emission control lines E1 to En, a scan driver 10 for driving the scan lines S1 to Sn, a data driver 20 for driving the data lines D1 to Dm, an emission control line driver 30 for driving the emission control lines E1 to En, and a timing controller 60 for controlling the drivers 10, 20, and 30.
The scan driver 10 sequentially supplies scan signals to the scan lines S1 to Sn. When the scan signals are supplied to the scan lines S1 to Sn, the pixels 50 are selected in units of horizontal lines (e.g., line-by-line).
The data driver 20 supplies data signals to the data lines D1 to Dm in synchronization with the scan signals. The data signals supplied to the data lines D1 to Dm are supplied to the pixels 50 that are selected by the scan signals.
The emission control line driver 30 sequentially supplies emission control signals to the emission control lines E1 to En. Here, the emission control line driver 30 supplies the emission control signals so that the pixels 50 are set in a non-emission state during a period when the voltages corresponding to the data signals are charged. Therefore, the emission control signal supplied to the ith (i is a natural number) emission control line Ei overlaps the scan signal supplied to the ith scan line Si. On the other hand, the width of the emission control signal may be suitably set to correspond to the structure of the pixel 50 and the brightness to be realized.
FIG. 2 is a block diagram schematically illustrating stages of the emission control line driver of FIG. 1.
Referring to FIG. 2, the emission control line driver 30 according to an embodiment of the present invention includes n stages 321 to 32 n in order to supply emission control signals to the n emission control lines E1 to En. The stages 321 to 32 n are coupled to the emission control lines E1 to En, respectively, and are driven by three clock signals CLK1, CLK2, and CLK3.
Each of the stages 321 to 32 n includes a first input terminal 33, a second input terminal 34, a third input terminal 35, and a fourth input terminal 36.
The first input terminal 33 of a kth (k is an odd or even number) stage 32 k receives the first clock signal CLK1 and the second input terminal 34 receives the second clock signal CLK2. The first input terminal 33 of a (k+1)th stage 32 k+1 receives the second clock signal CLK2, and the second input terminal 34 receives the first clock signal CLK1. The third clock signal CLK3 is supplied to the third input terminal 35 of each of the stages 321 to 32 n, and a start signal FLM or a sampling signal of a previous stage is supplied to the fourth input terminal 36.
The stages 321 to 32 n may be formed of the same circuit and generate the emission control signals having width that is changed to correspond to the start signal FLM.
FIG. 3 is a circuit diagram illustrating a first embodiment of one of the stages of FIG. 2. In FIG. 3, for convenience sake, the first stage 321 will be illustrated.
Referring to FIG. 3, the stage 321, according to the first embodiment of the present invention, includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first capacitor C1, a second capacitor C2, a first controller 100, and a second controller 102.
The first transistor M1 is coupled between a first output terminal 37 and a first power source VDD. The gate electrode of the first transistor M1 is coupled to a first node N1. The first transistor M1 controls the voltage of the first output terminal 37 to correspond to the voltage applied to the first node N1. Here, when the first transistor M1 is turned on, the first power source VDD (e.g., a high voltage) is supplied to the first output terminal 37. Since the first output terminal 37 is coupled to the emission control line E1, the high voltage supplied to the first output terminal 37 is used as an emission control signal.
The second transistor M2 is coupled between the first output terminal 37 and a second power source VSS. The gate electrode of the second transistor M2 is coupled to a second node N2. The second transistor M2 controls the voltage of the first output terminal 37 to correspond to the voltage applied to the second node N2. Here, when the second transistor M2 is turned on, the second power source VSS (e.g., a low voltage) is supplied to the first output terminal 37.
The third transistor M3 is coupled between the fourth input terminal 36 and the first node N1. The gate electrode of the third transistor M3 is coupled to the first input terminal 33. The third transistor M3 is turned on or off to correspond to the first clock signal CLK1 supplied to the first input terminal 33. When the third transistor M3 is turned on, the fourth input terminal 36 and the first node N1 are electrically coupled to each other. When the start signal FLM (or a previous stage sampling signal) is supplied to the fourth input terminal 36, the first transistor M1 is turned on.
The fourth transistor M4 is coupled between the first power source VDD and the second node N2. The gate electrode of the fourth transistor M4 is coupled to the first node N1. The fourth transistor M4 is turned on or off to correspond to the voltage that is applied to the first node N1 in order to control the voltage of the second node N2. That is, the fourth transistor M4 is turned on when a low voltage is applied to the first node N1 in order to supply the voltage of the first power source VDD to the second node N2. When the low voltage is supplied to the first node N1, the high voltage of the first power source VDD is supplied to the second node N2 so that the first transistor M1 and the second transistor M2 are turned on or off at different times.
The first capacitor C1 is coupled between the second input terminal 34 and the second node N2. The first capacitor C1 controls the voltage of the second node N2 to correspond to the second clock signal CLK2 supplied to the second input terminal 34. The operation processes of the first capacitor C1 will be described later in more detail.
The second capacitor C2 is coupled between the first node N1 and the first power source VDD. The second capacitor C2 is charged with the voltage corresponding to the turning on or off of the first transistor M1.
A first controller 100 supplies a sampling signal to a second output terminal 38 to correspond to the first clock signal CLK1 and the second clock signal CLK2. Therefore, the first controller 100 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, a third capacitor C3, and a fourth capacitor C4.
The fifth transistor M5 is coupled between the fourth input terminal 36 and a third node N3. The gate electrode of the fifth transistor M5 is coupled to the first input terminal 33. The fifth transistor M5 is turned on or off to correspond to the first clock signal CLK1 supplied to the first input terminal 33 in order to control the voltage of the third node N3.
The sixth transistor M6 is coupled between a sixth node N6 and the second input terminal 34. The gate electrode of the sixth transistor M6 is coupled to the third node N3. The sixth transistor M6 controls the voltage of the sixth node N6 to correspond to the voltage applied to the third node N3.
The seventh transistor M7 is coupled between the first power source VDD and the sixth node N6. The gate electrode of the seventh transistor M7 is coupled to the first output terminal 37. The seventh transistor M7 is turned on or off to correspond to the voltage applied to the first output terminal 37 in order to control the voltage of the sixth node N6.
The third capacitor C3 is coupled between the third node N3 and the sixth node N6. The third capacitor C3 is charged with the voltage corresponding to the turning on or turning off of the sixth transistor M6.
The fourth capacitor C4 is coupled between the first power source VDD and the first output terminal 37. The fourth capacitor C4 is charged with the voltage corresponding to the turning on or off of the seventh transistor M7.
In FIG. 3, the second output terminal 38 is coupled to the sixth node N6. The second output terminal 38 supplies the voltage applied to the sixth node N6 as a sampling signal to a next stage 322.
The second controller 102 controls the voltage of the second node N2 to correspond to the first clock signal CLK1 and the third clock signal CLK3. Here, in a period when the emission control signal is not supplied to the first output terminal 37, the second controller 102 maintains the voltage of the second node N2 as a low voltage. In FIG. 3, the second controller 102 includes an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a fifth capacitor C5.
The eighth transistor M8 is coupled between the first input terminal 33 and a fourth node N4. The gate electrode of the eighth transistor M8 is coupled to the first node N1. The eighth transistor M8 is turned on or off to correspond to the voltage applied to the first node N1 in order to control the voltage of the fourth node N4.
The ninth transistor M9 is coupled between the fourth node N4 and the second power source VSS. The gate electrode of the ninth transistor M9 is coupled to the first input terminal 33. The ninth transistor M9 is turned on or off to correspond to the first clock signal CLK1 supplied to the first input terminal 33 in order to control the voltage of the fourth node N4.
The tenth transistor M10 is coupled between the second node N2 and a fifth node N5. The gate electrode of the tenth transistor M10 is coupled to a third input terminal 35. The tenth transistor M10 is turned on or off to correspond to the third clock signal CLK3 supplied to the third input terminal 35 in order to control the voltage of the second node N2.
The eleventh transistor M11 is coupled between the fifth node N5 and the third input terminal 35. The gate electrode of the eleventh transistor M11 is coupled to the fourth node N4. The eleventh transistor M11 is turned on or off to correspond to the voltage applied to the fourth node N4 in order to control the voltage of the fifth node N5.
The fifth capacitor C5 is coupled between the fourth node N4 and the fifth node N5. The fifth capacitor C5 is charged with the voltage corresponding to the turning on or off of the eleventh transistor M11.
FIG. 4 is a waveform chart illustrating the operation processes of the stage of FIG. 3.
Referring to FIG. 4, the first clock signal CLK1 and the second clock signal CLK2 are supplied in the period of iH (i is a natural number, e.g., a horizontal period), and the third clock signal CLK3 is supplied in the period of i/2H. In FIG. 4, for convenience sake, the first clock signal CLK1 and the second clock signal CLK2 are set in the period of 2H and the third clock signal CLK3 is set in the period of 1H.
In FIG. 4, the first clock signal CLK1 and the second clock signal CLK2 are supplied in different horizontal periods H, and the third clock signal CLK3 is supplied every horizontal period H so that the first clock signal CLK1 does not overlap the third clock signal CLK3. Then, in the horizontal period H, after the first clock signal CLK1 or the second clock signal CLK2 is supplied, the third clock signal CLK3 is supplied. That is, in an exemplary horizontal period, the third clock signal CLK3 is supplied after the first clock signal CLK1 is supplied. In the next horizontal period, the third clock signal CLK3 is supplied after the second clock signal CLK2 is supplied.
Operation processes will be described in more detail as follows. First, the start signal FLM (e.g., the low signal) is supplied to the fourth input terminal 36. After the start signal FLM is supplied to the fourth input terminal 36, the first clock signal CLK1 is supplied to the first input terminal 33. When the first clock signal CLK1 is supplied, the third transistor M3, the fifth transistor M5, and the ninth transistor M9 are turned on.
When the third transistor M3 is turned on, the start signal FLM is supplied to the first node N1. When the start signal FLM is supplied to the first node N1, the first transistor M1, the fourth transistor M4, and the eighth transistor M8 are turned on.
When the first transistor M1 is turned on, the voltage corresponding to the turning on of the first transistor M1 is charged at the second capacitor C2. When the first transistor M1 is turned on, the voltage of the first power source VDD is supplied to the first output terminal 37. In this case, the emission control signal is supplied to the emission control line E1.
When the fourth transistor M4 is turned on, the first power source VDD is supplied to the second node N2. When the first power source VDD is supplied to the second node N2, the second transistor M2 is turned off. When the second transistor M2 is turned off, the first power source VDD may be stably supplied to the first output terminal 37.
When the eighth transistor M8 is turned on, the fourth node N4 and the first input terminal 33 are electrically coupled to each other. Here, since the first clock signal CLK1 is supplied to the first input terminal 33, the fourth node N4 receives a low voltage.
When the fifth transistor M5 is turned on, the start signal is supplied to the third node N3. When the start signal is supplied to the third node N3, the sixth transistor M6 is turned on. When the sixth transistor M6 is turned on, the sixth node N6 and the second input terminal 34 are electrically coupled to each other. Here, since the second clock signal CLK2 is not supplied to the second input terminal 34, the sixth node N6 maintains a high voltage so that a sampling signal is not supplied to the second output terminal 38. On the other hand, since the sixth transistor M6 is turned on, the voltage corresponding to the turning on of the sixth transistor M6 is charged at the third capacitor C3.
When the ninth transistor M9 is turned on, the voltage of the second power source VSS is supplied to the fourth node N4. When the second power source VSS is supplied to the fourth node N4, the eleventh transistor M11 is turned on. When the eleventh transistor M11 is turned on, the fifth node N5 and the third input terminal 35 are electrically coupled to each other. Here, since the third clock signal CLK3 is not supplied to the third input terminal 35, the fifth node N5 maintains a high voltage. On the other hand, since the eleventh transistor M11 is turned on, the voltage corresponding to the turning on of the eleventh transistor is charged at the fifth capacitor C5.
Then, the supply of the first clock signal CLK1 to the first input terminal 33 is stopped. When the supply of the first clock signal CLK1 is stopped, the third transistor M3, the fifth transistor M5, and the ninth transistor M9 are turned off.
When the third transistor M3 is turned off, the fourth input terminal 36 and the first node N1 are electrically isolated from each other. Here, the first node N1 maintains a low voltage by the second capacitor C2. Therefore, the first transistor M1 maintains a turn on state so that the voltage of the first power source VDD is output to the first output terminal 37. Since the fourth transistor M4 maintains a turn on state by the voltage of the second capacitor C2, the second transistor M2 stably maintains a turn off state.
When the fifth transistor M5 is turned off, the fourth input terminal 36 and the third node N3 are electrically isolated from each other. Here, the sixth transistor M6 maintains a turn on state to correspond to the voltage charged at the third capacitor C3 so that the second output terminal 38 maintains a previous voltage.
When the ninth transistor M9 is turned off, the fourth node N4 and the second power source VSS are electrically isolated from each other. Here, since the eighth transistor M8 maintains a turned on state to correspond to the voltage applied to the first node N1, the fourth node N4 and the first input terminal 33 are electrically coupled to each other. Therefore, the voltage of the fourth node N4 increases to the voltage supplied to the first input terminal 33 (e.g., the voltage of a high signal). When the fourth node N4 receives the voltage of the high signal, the eleventh transistor M11 is turned off. Here, the fifth capacitor C5 is charged with the voltage corresponding to the turning off of the eleventh transistor M11.
Then, the third clock signal CLK3 is supplied to the third input terminal 35. When the third clock signal CLK3 is supplied, the tenth transistor M10 is turned on. When the tenth transistor M10 is turned on, the second node N2 and the fifth node N5 are electrically coupled to each other. At this time, since the fourth transistor M4 maintains a turned on state and the eleventh transistor M11 maintains a turned off state, the second node N2 maintains the voltage of the first power source VDD.
After the third clock signal CLK3 is supplied, the second clock signal CLK2 is supplied to the second input terminal 34 in the next horizontal period. Here, since the sixth transistor M6 is set in a turn on state, the second clock signal CLK2 is supplied to the sixth node N6. The second clock signal CLK2 supplied to the sixth node N6 as a sampling signal is supplied to the next stage via the second output terminal 38. On the other hand, when the second clock signal CLK2 is supplied to the sixth node N6, the voltage of the third node N3 is reduced by the coupling of the third capacitor C3. Therefore, the sixth transistor M6 stably maintains a turned on state.
Additionally, the second clock signal CLK2 supplied to the second input terminal 34 is transmitted to the second node N2 by the coupling of the first capacitor C1. Here, since the second node N2 receives the first power source VDD, the voltage of the first power source VDD is maintained without a change in a voltage.
Then, the third clock signal CLK3 is supplied to the third input terminal 35. When the third clock signal CLK3 is supplied, the tenth transistor M10 is turned on. When the tenth transistor M10 is turned on, the second node N2 and the fifth node N5 are electrically coupled to each other. Here, since the fourth transistor M4 maintains a turned on state and the eleventh transistor M11 maintains a turned off state, the second node N2 maintains the voltage of the first power source VDD.
After the third clock signal CLK3 is supplied, the supply of the start signal FLM is stopped (e.g., a high voltage) in the next horizontal period, and the first clock signal CLK1 is supplied to the first input terminal 33.
When the first clock signal CLK1 is supplied, the third transistor M3, the fifth transistor M5, and the ninth transistor M9 are turned on.
When the third transistor M3 is turned on, the first node N1 and the fourth input terminal 36 are electrically coupled to each other. Here, since a high voltage is supplied to the first node N1, the first transistor M1, the fourth transistor M4, and the eighth transistor M8 are turned off. When the first transistor M1 is turned off, the first output terminal 37 is set in a floating state. In this case, the first output terminal 37 maintains the high voltage that is an output signal of a previous period.
Since the emission control signal supplied to the emission control line E1 is supplied to the pixels 50, charging is performed by the capacitors of the pixels. Therefore, although the first output terminal 37 is set in a floating state, the output voltage of a previous period is maintained by the parasitic capacitors of the pixels 50 and the emission control line.
When the fifth transistor M5 is turned on, a high voltage is supplied to the third node N3 so that the sixth transistor M6 is turned off. When the sixth transistor M6 is turned off, the sixth node N6 and the second input terminal 34 are electrically isolated from each other. Here, the third capacitor C3 is charged with the voltage corresponding to the turning off of the sixth transistor M6.
When the ninth transistor M9 is turned on, the fourth node N4 and the second power source VSS are electrically coupled to each other. Here, the fourth node N4 receives the voltage of the second power source VSS so that the eleventh transistor M11 is turned on. When the eleventh transistor M1 is turned on, the fifth node N5 and the third input terminal 35 are electrically coupled to each other. On the other hand, the voltage corresponding to the turning on of the eleventh transistor M11 is stored at the fifth capacitor C5.
Then, the third clock signal CLK3 is supplied to the third input terminal 35. When the third clock signal CLK3 is supplied, the tenth transistor M10 is turned on. When the tenth transistor M10 is turned on, the second node N2 and the third input terminal 35 are electrically coupled to each other via the fifth node N5. Here, the third clock signal CLK3 (e.g., a low voltage) is supplied to the second node N2. When the low voltage is supplied to the second node N2, the second transistor M2 is turned on so that the voltage of the second power source VSS is output to the first output terminal 37. In this case, the supply of the emission control signal to the emission control line E1 is stopped. When the second power source VSS is supplied to the first output terminal 37, the seventh transistor M7 is turned on. When the seventh transistor M7 is turned on, the voltage of the first power source VDD is supplied to the sixth node N6.
According to an embodiment of the present invention, the third clock signal CLK3 may be set as a voltage lower than the second power source VSS so that the second transistor M2 may be stably turned on. Then, the stage 321 outputs the voltage of the first power source VDD to the first output terminal 37 until the next start signal FLM is supplied.
Additionally, according to embodiments of the present invention, whenever the second clock signal CLK2 is supplied, the voltage of the second node N2 is reduced by the coupling of the first capacitor C1. Therefore, the voltage of the second node N2 stably maintains a low voltage so that the voltage of the second power source VSS may be stably output to the first output terminal 37.
On the other hand, a sampling signal is supplied to the next stage in synchronization with the second clock signal CLK2 (In the next stage, the second clock signal CLK2 is supplied to the first input terminal). In this case, the next stage stably outputs the emission control signal using the sampling signal.
Additionally, in FIG. 4, it is illustrated that one sampling signal is generated to correspond to the start signal FLM. However, the present invention is not limited to the above. For example, when the start signal FLM overlaps two first clock signals CLK1, two sampling signals are supplied to the next stage. Therefore, according to embodiments of the present invention, the width of the start signal FLM is controlled so that the width of the emission control signal may be freely controlled.
FIG. 5 is a circuit diagram illustrating a second embodiment of the stage of FIG. 2. In FIG. 5, the same elements as those of FIG. 3 are denoted by the same reference numerals and detailed description thereof will be omitted.
Referring to FIG. 5, the stage 321, according to the second embodiment of the present invention, further includes a twelfth transistor M12 and a thirteenth transistor M13 for bidirectional driving.
The twelfth transistor M12 is coupled between the fourth input terminal 36 and the third transistor M3. The gate electrode of the twelfth transistor M12 receives a first control signal CS1. The twelfth transistor M12 is turned on when the first control signal CS1 is supplied.
The thirteenth transistor M13 is coupled between a fifth input terminal 39 and the fifth transistor M5 (or a first controller 100). Then, the gate electrode of the thirteenth transistor M13 receives a second control signal CS2. The thirteenth transistor M13 is turned on when the second control signal CS2 is supplied. The fifth input terminal 39 receives the start signal or the sampling signal of the next stage.
Here, the first control signal CS1 and the second control signal CS2 are supplied at different times (e.g., not overlapped with each other). For example, when the emission control signals are supplied in a first direction (from top to bottom of a panel), the first control signal CS1 is supplied so that the twelfth transistor M12 is turned on and so that the thirteenth transistor M13 maintains a turned off state. When the emission control signals are supplied in a second direction (from bottom to top of the panel), the second control signal CS2 is supplied so that the thirteenth transistor M13 is turned on and so that the twelfth transistor M12 maintains a turned off state.
The stage 321, according to the second embodiment of the present invention, further includes the twelfth transistor M12 and the thirteenth transistor M13 for bidirectional driving, and the operation processes are substantially the same as the first embodiment illustrated in FIG. 3.
FIG. 6 is a circuit diagram illustrating a third embodiment of the stage of FIG. 2. In FIG. 6, the same elements as those of FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.
Referring to FIG. 6, the stage 321, according to the third embodiment of the present invention, further includes a fourteenth transistor M14 coupled between the first node N1 and the second power source VSS. The fourteenth transistor M14 is turned on to supply the voltage of the second power source VSS to the first node N1 when a reset signal (Reset) is supplied to the gate of the fourteenth transistor M14. When the second power source VSS is supplied to the first node N1, the first transistor M1 is turned on so that the voltage of the first power source VDD is supplied to the first output terminal 37.
Here, the reset signal (Reset) is commonly supplied to all of the stages 321 to 32 n when a power source is turned on and/or off. As described above, when the reset signal (Reset) is supplied and the power source is turned on and/or off, the emission control signals are supplied to the emission control lines E1 to En so that the pixels 50 are set in a non-emission state. That is, according to the third embodiment of the present invention, it is possible to prevent over-current from flowing or unnecessary light from being generated when the power source is turned on and/or off using the reset signal.
Additionally, in FIG. 2, the third clock signal CLK3 is supplied to all of the stages 321 to 32 n. However, the present invention is not limited to the above. For example, the third clock signal CLK3 may be supplied to even and odd stages via different lines. Then, the load of the third clock signal CLK3 is minimized or reduced so that the stability of driving the stages may be improved.
The present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims, and equivalents thereof.

Claims (26)

What is claimed is:
1. An emission control line driver comprising a plurality of stages, wherein each of the stages comprises:
a first transistor electrically coupled between a first output terminal and a first power source, the first transistor being configured to be turned on or off to correspond to a voltage applied to a first node that is directly coupled to a gate electrode of the first transistor;
a second transistor electrically coupled between the first output terminal and a second power source that outputs a voltage that is lower than the first power source, the second transistor being configured to be turned on or off to correspond to a voltage applied to a second node that is directly coupled to a gate electrode of the second transistor;
a third transistor coupled between a fourth input terminal and the first node, and having a gate electrode directly coupled to a first input terminal, the third transistor being configured to electrically couple the first node to the fourth input terminal in response to a signal received from the first input terminal;
a fourth transistor coupled between the first power source and the second node, and having a gate electrode directly coupled to the first node;
a first controller coupled to the first input terminal and a second input terminal and configured to supply a sampling signal to a second output terminal;
a second controller electrically coupled to the first input terminal and a third input terminal and configured to control the voltage of the second node; and
a first capacitor electrically coupled between the second input terminal and the second node.
2. The emission control line driver as claimed in claim 1, further comprising a second capacitor coupled between the first node and the first power source.
3. The emission control line driver as claimed in claim 1,
wherein the first input terminal is configured to receive a first clock signal,
wherein the second input terminal is configured to receive a second clock signal,
wherein the third input terminal is configured to receive a third clock signal, and
wherein the fourth input terminal is configured to receive a start signal or a sampling signal of a previous stage.
4. The emission control line driver as claimed in claim 3, wherein the first clock signal, the second clock signal, and the third clock signal do not overlap each other.
5. The emission control line driver as claimed in claim 3,
wherein each of the first clock signal and the second clock signal are set in a period of i horizontal periods, and
wherein the third clock signal is set in a period of i/2 horizontal periods.
6. The emission control line driver as claimed in claim 5, wherein the third clock signal is supplied in a horizontal period after the first clock signal or the second clock signal is supplied in the horizontal period.
7. The emission control line driver as claimed in claim 1, wherein the first controller comprises:
a fifth transistor coupled between the fourth input terminal and a third node, and having a gate electrode coupled to the first input terminal;
a sixth transistor coupled between a sixth node and the second input terminal, and having a gate electrode coupled to the third node;
a seventh transistor coupled between the sixth node and the first power source, and having a gate electrode coupled to the first output terminal;
a third capacitor coupled between the third node and the sixth node; and
a fourth capacitor coupled between the first output terminal and the first power source.
8. The emission control line driver as claimed in claim 7, wherein the second output terminal is electrically coupled to the sixth node.
9. The emission control line driver as claimed in claim 1, wherein the second controller comprises:
an eighth transistor coupled between the first input terminal and a fourth node, and having a gate electrode coupled to the first node;
a ninth transistor coupled between the fourth node and the second power source, and having a gate electrode coupled to the first input terminal;
a tenth transistor coupled between the second node and a fifth node, and having a gate electrode coupled to the third input terminal;
an eleventh transistor coupled between the fifth node and the third input terminal, and having a gate electrode coupled to the fourth node; and
a fifth capacitor coupled between the fourth node and the fifth node.
10. The emission control line driver as claimed in claim 1, further comprising:
a twelfth transistor coupled between the fourth input terminal and the third transistor, the twelfth transistor being configured to be turned on when a first control signal is supplied to a gate electrode of the twelfth transistor; and
a thirteenth transistor coupled between a fifth input terminal and the first controller, the thirteenth transistor being configured to be turned on when a second control signal is supplied to a gate electrode of the thirteenth transistor.
11. The emission control line driver as claimed in claim 10, wherein the first control signal and the second control signal do not overlap each other.
12. The emission control line driver as claimed in claim 10, wherein the fifth input terminal is configured to receive a start signal or a sampling signal of a next stage.
13. The emission control line driver as claimed in claim 1, further comprising a fourteenth transistor coupled between the first node and the second power source, the fourteenth transistor being configured to be turned on when a reset signal is supplied to a gate electrode of the fourteenth transistor.
14. The emission control line driver as claimed in claim 13, wherein the reset signal is commonly supplied to all of the stages.
15. An organic light emitting display comprising:
a scan driver for sequentially supplying scan signals to scan lines;
a data driver for supplying data signals to data lines;
an emission control line driver for supplying emission control signals to emission control lines; and
pixels positioned at crossing regions of the scan lines, the data lines, and the emission control lines,
wherein the emission control line driver comprises stages respectively coupled to the emission control lines, and
wherein each of the stages comprises:
a first transistor electrically coupled between a first output terminal and a first power source, the first transistor being configured to be turned on or off to correspond to a voltage applied to a first node that is directly coupled to a gate electrode of the first transistor;
a second transistor electrically coupled between the first output terminal and a second power source that outputs a voltage that is lower than the first power source, the second transistor being configured to be turned on or off to correspond to a voltage applied to a second node that is directly coupled to a gate electrode of the second transistor;
a third transistor coupled between a fourth input terminal and the first node, and having a gate electrode directly coupled to a first input terminal, the third transistor being configured to electrically couple the first node to the fourth input terminal in response to a signal received from the first input terminal;
a fourth transistor coupled between the first power source and the second node, and having a gate electrode directly coupled to the first node;
a first controller coupled to the first input terminal and a second input terminal and configured to supply a sampling signal to a second output terminal;
a second controller electrically coupled to the first input terminal and a third input terminal and configured to control the voltage of the second node; and
a first capacitor electrically coupled between the second input terminal and the second node.
16. The organic light emitting display as claimed in claim 15, further comprising a second capacitor coupled between the first node and the first power source.
17. The organic light emitting display as claimed in claim 15,
wherein the first input terminal of an ith stage of the stages is configured to receive a first clock signal,
wherein the second input terminal of the ith stage is configured to receive a second clock signal,
wherein the third input terminal of the ith stage is configured to receive a third clock signal, and
wherein the fourth input terminal of the ith stage is configured to receive a start signal or a sampling signal of a previous stage.
18. The organic light emitting display as claimed in claim 17,
wherein the first input terminal of an (i+1)th stage of the stages is configured to receive the second clock signal,
wherein the second input terminal of the (i+1)th stage is configured to receive the first clock signal,
wherein the third input terminal of the (i+1)th stage is configured to receive the third clock signal, and
wherein the fourth input terminal of the (i+1)th stage is configured to receive the start signal or the sampling signal of a previous stage.
19. The organic light emitting display as claimed in claim 18,
wherein each of the first clock signal and the second clock signal are set in a period of i horizontal periods, and
wherein the third clock signal is set in a period of i/2 horizontal periods.
20. The organic light emitting display as claimed in claim 18, wherein the third clock signal is supplied in a horizontal period after the first clock signal or the second clock signal is supplied in the horizontal period.
21. The organic light emitting display as claimed in claim 18, wherein the third clock signal supplied to the ith stage and the (i+1)th stage is supplied via different transmission lines.
22. The organic light emitting display as claimed in claim 15, wherein the first controller comprises:
a fifth transistor coupled between the fourth input terminal and a third node, and having a gate electrode coupled to the first input terminal;
a sixth transistor coupled between a sixth node and the second input terminal, and having a gate electrode coupled to the third node;
a seventh transistor coupled between the sixth node and the first power source, and having a gate electrode coupled to the first output terminal;
a third capacitor coupled between the third node and the sixth node; and
a fourth capacitor coupled between the first output terminal and the first power source.
23. The organic light emitting display as claimed in claim 22, wherein the second output terminal is electrically coupled to the sixth node.
24. The organic light emitting display as claimed in claim 15, wherein the second controller comprises:
an eighth transistor coupled between the first input terminal and a fourth node, and having a gate electrode coupled to the first node;
a ninth transistor coupled between the fourth node and the second power source, and having a gate electrode coupled to the first input terminal;
a tenth transistor coupled between the second node and a fifth node, and having a gate electrode coupled to the third input terminal;
an eleventh transistor coupled between the fifth node and the third input terminal, and having a gate electrode coupled to the fourth node; and
a fifth capacitor coupled between the fourth node and the fifth node.
25. The organic light emitting display as claimed in claim 15, further comprising:
a twelfth transistor coupled between the fourth input terminal and the third transistor, the twelfth transistor being configured to be turned on when a first control signal is supplied to a gate electrode of the twelfth transistor; and
a thirteenth transistor coupled between a fifth input terminal and the first controller, the thirteenth transistor being configured to be turned on when a second control signal is supplied to a gate electrode of the thirteenth transistor,
wherein the twelfth transistor and the thirteenth transistor are configured to be turned on at different times.
26. The organic light emitting display as claimed in claim 15, further comprising a fourteenth transistor coupled between the first node and the second power source, the fourteenth transistor being configured to be turned on when a reset signal is supplied.
US13/247,945 2011-01-06 2011-09-28 Emission control line driver and organic light emitting display using the same Active 2032-06-05 US9129562B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020110001419A KR101944465B1 (en) 2011-01-06 2011-01-06 Emission Driver and Organic Light Emitting Display Device Using the same
KR10-2011-0001419 2011-01-06

Publications (2)

Publication Number Publication Date
US20120176417A1 US20120176417A1 (en) 2012-07-12
US9129562B2 true US9129562B2 (en) 2015-09-08

Family

ID=45463251

Family Applications (1)

Application Number Title Priority Date Filing Date
US13/247,945 Active 2032-06-05 US9129562B2 (en) 2011-01-06 2011-09-28 Emission control line driver and organic light emitting display using the same

Country Status (6)

Country Link
US (1) US9129562B2 (en)
EP (1) EP2474969B1 (en)
JP (1) JP5940769B2 (en)
KR (1) KR101944465B1 (en)
CN (1) CN102592539B (en)
TW (1) TWI451388B (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150035733A1 (en) * 2013-08-05 2015-02-05 Samsung Display Co., Ltd. Stage circuit and organic light emitting display device using the same
US20150061982A1 (en) * 2013-08-29 2015-03-05 Samsung Display Co., Ltd. Stage circuit and organic light emitting display device using the same
US20160321999A1 (en) * 2013-12-30 2016-11-03 Kunshan New Flat Panel Display Techn. Center Co. Scanning Drive Circuit and Organic Light-Emitting Display
US10614732B2 (en) * 2017-02-20 2020-04-07 Samsung Display Co., Ltd. Stage circuit and scan driver using the same
US10777290B2 (en) 2012-02-29 2020-09-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
USRE48358E1 (en) 2012-08-21 2020-12-15 Samsung Display Co., Ltd. Emission control driver and organic light emitting display device having the same
US11043281B2 (en) * 2017-08-31 2021-06-22 Boe Technology Group Co., Ltd. Shift register unit and driving method thereof, circuit, array substrate and display device
US11074854B1 (en) * 2020-03-09 2021-07-27 Novatek Microelectronics Corp. Driving device and operation method thereof
US11100856B2 (en) 2016-06-17 2021-08-24 Samsung Display Co., Ltd. Stage and organic light emitting display device using the same
US11727885B2 (en) 2021-12-09 2023-08-15 Samsung Display Co., Ltd. Scan driver and display device including the same
US11830419B1 (en) * 2022-11-10 2023-11-28 AUO Corporation Display panel and light emitting signal generator thereof

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101881853B1 (en) * 2012-02-29 2018-07-26 삼성디스플레이 주식회사 Emission driving unit, emission driver and organic light emitting display device having the same
CN102760406B (en) * 2012-07-13 2015-01-28 京东方科技集团股份有限公司 Light-emitting control circuit, light-emitting control method and shift register
CN102760407B (en) * 2012-07-13 2015-11-25 京东方科技集团股份有限公司 Emission control circuit, light-emitting control method and shift register
KR101988590B1 (en) 2012-10-24 2019-06-13 삼성디스플레이 주식회사 Emission Driver
EP3564742B1 (en) * 2012-10-30 2022-02-23 Sharp Kabushiki Kaisha Active-matrix substrate and display panel including the same
CN103065584B (en) * 2012-12-18 2015-06-03 华南理工大学 Power source organic electroluminescence scanning drive device and drive method thereof
KR102081910B1 (en) * 2013-06-12 2020-02-27 삼성디스플레이 주식회사 Capacitor, driving circuit comprising the capacitor, and display device comprising the driving circuit
CN104751770B (en) * 2013-12-25 2018-01-16 昆山国显光电有限公司 Emission control drive circuit and the OLED using the circuit
KR102120070B1 (en) * 2013-12-31 2020-06-08 엘지디스플레이 주식회사 Display device and method of driving the same
CN105096791B (en) * 2014-05-08 2017-10-31 上海和辉光电有限公司 Multiplex driver and display device
KR102262174B1 (en) * 2014-08-04 2021-06-09 삼성디스플레이 주식회사 Light emission control driver and display device having the same
CN104167175B (en) * 2014-08-06 2016-08-31 上海和辉光电有限公司 Oled
CN104809978B (en) * 2015-05-21 2017-05-17 京东方科技集团股份有限公司 Shifting register unit, driving method of shifting register unit, grid driving circuit and display device
CN105139795B (en) * 2015-09-22 2018-07-17 上海天马有机发光显示技术有限公司 A kind of gate scanning circuit and its driving method, gated sweep cascade circuit
KR102532899B1 (en) 2015-11-04 2023-05-17 삼성디스플레이 주식회사 Organic light emitting display panel
CN106920498B (en) 2015-12-25 2019-10-25 昆山工研院新型平板显示技术中心有限公司 GIP circuit and its driving method and panel display apparatus
KR102613407B1 (en) 2015-12-31 2023-12-13 엘지디스플레이 주식회사 display apparatus, gate driving circuit and driving method thereof
CN105575329B (en) * 2016-03-16 2017-12-01 京东方科技集团股份有限公司 Shift register and driving method, drive circuit, array base palte and display device
KR102512721B1 (en) * 2016-04-05 2023-03-23 삼성디스플레이 주식회사 Display apparatus
KR102477486B1 (en) * 2016-04-19 2022-12-14 삼성디스플레이 주식회사 Emission control driver and display device having the same
TWI625718B (en) * 2016-10-04 2018-06-01 創王光電股份有限公司 High stability shift register with adjustable pulse width
CN106486065B (en) * 2016-12-29 2019-03-12 上海天马有机发光显示技术有限公司 Shifting deposit unit, register, organic light emitting display panel and driving method
CN108806588B (en) * 2017-04-28 2020-06-12 昆山国显光电有限公司 Light-emitting control circuit, light-emitting control method and shift register
CN108806590B (en) * 2017-04-28 2023-11-24 昆山国显光电有限公司 Emission control driver and display device thereof
CN107978277B (en) 2018-01-19 2019-03-26 昆山国显光电有限公司 Scanner driver and its driving method, organic light emitting display
TWI639149B (en) 2018-03-09 2018-10-21 友達光電股份有限公司 Pixel circuit
CN108389544B (en) 2018-03-23 2021-05-04 上海天马有机发光显示技术有限公司 Emission controller, control method thereof and display device
CN108389546B (en) * 2018-03-26 2021-11-30 武汉天马微电子有限公司 Emission control circuit, driving method thereof, emission controller and display device
KR102415379B1 (en) * 2018-03-29 2022-07-01 삼성디스플레이 주식회사 Emission driver and organic light emitting display device having the same
KR102098331B1 (en) * 2019-04-29 2020-04-08 삼성디스플레이 주식회사 Emission driver and organic light emitting display deivce including the same
CN110364121A (en) * 2019-06-27 2019-10-22 昆山国显光电有限公司 Scanning circuit, display panel and display device
KR102206090B1 (en) * 2020-02-20 2021-01-21 삼성디스플레이 주식회사 Capacitor, driving circuit comprising the capacitor, and display device comprising the driving circuit
KR102186759B1 (en) * 2020-04-01 2020-12-07 삼성디스플레이 주식회사 Emission driver and organic light emitting display deivce including the same
KR20210145048A (en) 2020-05-22 2021-12-01 삼성디스플레이 주식회사 Emission driver, display apparatus including the same, method of driving display apparatus
CN111768733B (en) * 2020-06-10 2022-08-30 京东方科技集团股份有限公司 Light emission control signal generation circuit, method and display device
KR20220034470A (en) * 2020-09-11 2022-03-18 엘지디스플레이 주식회사 Scan driver and organic light emitting display device including the same
CN116994516B (en) * 2023-07-28 2024-01-30 上海和辉光电股份有限公司 Gate driving circuit and display panel

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070063933A1 (en) * 2005-09-13 2007-03-22 Chung Bo Y Emission control line driver and organic light emitting display using the emission control line driver
US20070240024A1 (en) 2006-04-06 2007-10-11 Dong Yong Shin Scan driving circuit and organic light emitting display using the same
US20070262935A1 (en) 2006-05-09 2007-11-15 Dong Yong Shin Data driver and organic light emitting diode (OLED) display using the same
US20080079685A1 (en) 2006-09-29 2008-04-03 Semiconductor Energy Laboratory Co., Ltd. Display device
US20080150844A1 (en) * 2006-12-20 2008-06-26 Sangmoo Choi Organic light emitting diode display
CN101527110A (en) 2008-03-04 2009-09-09 三星移动显示器株式会社 Emission driver and organic light emitting display using the same
US20090303169A1 (en) 2008-06-06 2009-12-10 Sony Corporation Scanning drive circuit and display device including the same
US20100188316A1 (en) * 2009-01-29 2010-07-29 Hwan-Soo Jang Emission control driver and organic light emitting display device using the same
KR20100087870A (en) 2009-01-29 2010-08-06 삼성모바일디스플레이주식회사 Emission driver and organic light emitting display using the same
US20100207968A1 (en) 2009-02-17 2010-08-19 Mi-Hae Kim Emission driver and organic light emitting display device including the same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4168836B2 (en) 2003-06-03 2008-10-22 ソニー株式会社 Display device
KR100776511B1 (en) * 2006-04-18 2007-11-16 삼성에스디아이 주식회사 Scan driving circuit and organic light emitting display using the same

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070063933A1 (en) * 2005-09-13 2007-03-22 Chung Bo Y Emission control line driver and organic light emitting display using the emission control line driver
US20070240024A1 (en) 2006-04-06 2007-10-11 Dong Yong Shin Scan driving circuit and organic light emitting display using the same
TW200739499A (en) 2006-04-06 2007-10-16 Samsung Sdi Co Ltd Scan driving circuit and organic light emitting display using the same
JP2007279667A (en) 2006-04-06 2007-10-25 Samsung Sdi Co Ltd Scan driving circuit and organic light emitting display using same
US20070262935A1 (en) 2006-05-09 2007-11-15 Dong Yong Shin Data driver and organic light emitting diode (OLED) display using the same
US20080079685A1 (en) 2006-09-29 2008-04-03 Semiconductor Energy Laboratory Co., Ltd. Display device
JP2008089915A (en) 2006-09-29 2008-04-17 Semiconductor Energy Lab Co Ltd Liquid crystal display device
US20080150844A1 (en) * 2006-12-20 2008-06-26 Sangmoo Choi Organic light emitting diode display
CN101527110A (en) 2008-03-04 2009-09-09 三星移动显示器株式会社 Emission driver and organic light emitting display using the same
US20090225068A1 (en) 2008-03-04 2009-09-10 Seon-I Jeong Emission driver and organic light emitting display using the same
US20090303169A1 (en) 2008-06-06 2009-12-10 Sony Corporation Scanning drive circuit and display device including the same
TW201003605A (en) 2008-06-06 2010-01-16 Sony Corp Scanning drive circuit and display device including the same
US20100188316A1 (en) * 2009-01-29 2010-07-29 Hwan-Soo Jang Emission control driver and organic light emitting display device using the same
KR20100087871A (en) 2009-01-29 2010-08-06 삼성모바일디스플레이주식회사 Emission driver and organic light emitting display using the same
KR20100087870A (en) 2009-01-29 2010-08-06 삼성모바일디스플레이주식회사 Emission driver and organic light emitting display using the same
US20100207968A1 (en) 2009-02-17 2010-08-19 Mi-Hae Kim Emission driver and organic light emitting display device including the same
KR20100093738A (en) 2009-02-17 2010-08-26 삼성모바일디스플레이주식회사 Emission driver and organic light emitting display using the same

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Extended European Search Report dated Apr. 5, 2012 for corresponding European Patent Application No. 11193980.7, 8pp.
Japanese Office action mailed on Apr. 14, 2015, for corresponding Japanese Application No. 2011-124258; 4 pages.
SIPO Office action dated Feb. 2, 2015, for corresponding Chinese Patent application 201110344357.8, (6 pages).
Taiwan Office Action dated Dec. 16, 2013 of the Taiwanese Patent Application 100149401 claiming priority of the corresponding Korean Patent Application No. 10-2011-0001419, (4 pages).

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11017871B2 (en) 2012-02-29 2021-05-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11600348B2 (en) 2012-02-29 2023-03-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11538542B2 (en) 2012-02-29 2022-12-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10777290B2 (en) 2012-02-29 2020-09-15 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
USRE48358E1 (en) 2012-08-21 2020-12-15 Samsung Display Co., Ltd. Emission control driver and organic light emitting display device having the same
US9368069B2 (en) * 2013-08-05 2016-06-14 Samsung Display Co., Ltd. Stage circuit and organic light emitting display device using the same
US20150035733A1 (en) * 2013-08-05 2015-02-05 Samsung Display Co., Ltd. Stage circuit and organic light emitting display device using the same
US20150061982A1 (en) * 2013-08-29 2015-03-05 Samsung Display Co., Ltd. Stage circuit and organic light emitting display device using the same
US9454934B2 (en) * 2013-08-29 2016-09-27 Samsung Display Co., Ltd. Stage circuit and organic light emitting display device using the same
US20160321999A1 (en) * 2013-12-30 2016-11-03 Kunshan New Flat Panel Display Techn. Center Co. Scanning Drive Circuit and Organic Light-Emitting Display
US10013919B2 (en) * 2013-12-30 2018-07-03 Kunshan New Flat Panel Display Technology Center Co. Ltd. Scanning drive circuit and organic light-emitting display
US11100856B2 (en) 2016-06-17 2021-08-24 Samsung Display Co., Ltd. Stage and organic light emitting display device using the same
US11640788B2 (en) 2016-06-17 2023-05-02 Samsung Display Co., Ltd. Stage and organic light emitting display device using the same
US10614732B2 (en) * 2017-02-20 2020-04-07 Samsung Display Co., Ltd. Stage circuit and scan driver using the same
US11043281B2 (en) * 2017-08-31 2021-06-22 Boe Technology Group Co., Ltd. Shift register unit and driving method thereof, circuit, array substrate and display device
US11074854B1 (en) * 2020-03-09 2021-07-27 Novatek Microelectronics Corp. Driving device and operation method thereof
US11727885B2 (en) 2021-12-09 2023-08-15 Samsung Display Co., Ltd. Scan driver and display device including the same
US11830419B1 (en) * 2022-11-10 2023-11-28 AUO Corporation Display panel and light emitting signal generator thereof
US20240161686A1 (en) * 2022-11-10 2024-05-16 AUO Corporation Display panel and light emitting signal generator thereof

Also Published As

Publication number Publication date
JP2012145906A (en) 2012-08-02
US20120176417A1 (en) 2012-07-12
TW201232518A (en) 2012-08-01
EP2474969A1 (en) 2012-07-11
KR101944465B1 (en) 2019-02-07
KR20120080008A (en) 2012-07-16
EP2474969B1 (en) 2017-08-02
CN102592539B (en) 2016-01-20
CN102592539A (en) 2012-07-18
TWI451388B (en) 2014-09-01
JP5940769B2 (en) 2016-06-29

Similar Documents

Publication Publication Date Title
US9129562B2 (en) Emission control line driver and organic light emitting display using the same
US9330593B2 (en) Stage circuit and organic light emitting display using the same
US9443464B2 (en) Stage circuit and organic light emitting display device using the same
US8582715B2 (en) Stage circuit and scan driver using the same
US9183781B2 (en) Stage circuit and bidirectional emission control driver using the same
US9277622B2 (en) Emission control line driver
US8665182B2 (en) Emission control driver and organic light emitting display device using the same
KR101987933B1 (en) Pixel and Organic Light Emitting Display Device Using the same
US8717257B2 (en) Scan driver and organic light emitting display using the same
US8803562B2 (en) Stage circuit and scan driver using the same
US8451259B2 (en) Emission driver and organic light emitting display device including the same
US9262962B2 (en) Pixel and organic light emitting display device using the same
US8290115B2 (en) Driver and organic light emitting diode display using the same
US20110050741A1 (en) Organic light emitting display device and driving method thereof
US20110157125A1 (en) Pixel and organic light emitting display device
US20100188316A1 (en) Emission control driver and organic light emitting display device using the same
US8674906B2 (en) Organic light emitting display device
US9153167B2 (en) Organic light emitting display capable of displaying an image with desired brightness
US9384692B2 (en) Organic light emitting display having a reduced number of signal lines
US8743024B2 (en) Emission control driver and organic light emitting display using the same
US8723765B2 (en) Stage circuit and scan driver using the same
US8314788B2 (en) Organic light emitting display device
US8957576B2 (en) Pixel and organic light emitting display using the same
US20120206432A1 (en) Inverter and organic light emitting display using the same
US9324273B2 (en) Organic light emitting display and method of driving the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG MOBILE DISPLAY CO., LTD., KOREA, REPUBLIC

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JANG, HWAN-SOO;PYON, CHANG-SOO;REEL/FRAME:027007/0762

Effective date: 20110926

AS Assignment

Owner name: SAMSUNG DISPLAY CO., LTD., KOREA, REPUBLIC OF

Free format text: MERGER;ASSIGNOR:SAMSUNG MOBILE DISPLAY CO., LTD.;REEL/FRAME:028884/0128

Effective date: 20120702

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8