KR102186759B1 - Emission driver and organic light emitting display deivce including the same - Google Patents

Abstract

Each stage of the light emission control driver includes a first signal processing unit generating a first signal and a second signal in response to a first voltage, a first sub-control signal, and a second sub-control signal, and a level higher than the first voltage. A second signal processor configured to generate a third signal and a fourth signal in response to a second voltage, a third sub-control signal, the first signal, and the second signal, and the first voltage, the second voltage And a third signal processing unit configured to generate the emission control signal in response to the third signal and the fourth signal, and the first signal processing unit receives the emission control signal output from a previous stage to the first sub A light emission control driver that is provided as a control signal, and the first signal processing unit of a first stage receives a start signal as the first sub-control signal.

Description

Light emission control driving unit and organic light emitting display device including the same TECHNICAL FIELD [EMISSION DRIVER AND ORGANIC LIGHT EMITTING DISPLAY DEIVCE INCLUDING THE SAME}

The present invention relates to an emission control driver and an organic light emitting display device including the same, and more particularly, to a light emission control driver with a simplified configuration, and an organic light emitting display device including the same.

Recently, Liquid Crystal Display, Organic Light Emitting Display, Electro Wetting Display Device, Plasma Display Panel (PDP), and Electrophoretic Display Device) and other various display devices are being developed.

Among the display devices, an organic light emitting display device displays an image by using an organic light emitting diode that generates light by recombination of electrons and holes. Such an organic light emitting display device has an advantage of having a fast response speed and low power consumption.

A typical organic light emitting display device includes a plurality of pixels that display an image, a scan driver that sequentially supplies scan signals to the pixels, a data driver that supplies data voltages to the pixels, and emission control that supplies emission control signals to the pixels. It includes a driving part.

The pixels receive data voltages in response to the scan signals. The pixels display a predetermined image by generating light with a predetermined luminance corresponding to the data voltages. The emission time of the pixels is controlled by emission control signals. The light emission control driver is initialized in response to the initialization control signals and generates light emission control signals. Recently, there is a demand for a technology capable of simplifying the configuration of the light emission control driver.

An object of the present invention is to provide a light emission control driver with a simplified configuration and an organic light emitting display device including the same.

The emission control driver according to an embodiment of the present invention includes a plurality of stages sequentially outputting emission control signals through emission control lines, and each of the stages is provided with a first voltage and a first sub control signal , And a first signal processor for generating a first signal and a second signal in response to a second sub-control signal, receiving a second voltage having a level higher than the first voltage, and receiving a third sub-control signal, the first A second signal processor configured to generate a third signal and a fourth signal in response to a signal and the second signal, and receive the first voltage and the second voltage, and respond to the third signal and the fourth signal And a third signal processing unit configured to generate the emission control signal, wherein the first signal processing unit of each stage receives the emission control signal output from a previous stage as the first sub-control signal, and The first signal processor of the stage receives a start signal as the first sub control signal.

The first signal processing unit of each of the odd-numbered stages receives a first clock signal as the second sub-control signal, the second signal processing unit receives a second clock signal as the third sub-control signal, and The first signal processing unit of each of the stages receives the second clock signal as the second sub control signal, and the second signal processing unit receives the first clock signal as the third sub control signal.

The first and second clock signals have the same frequency, and the second clock signal is a signal in which the first clock signal is shifted by a first period defined as a half-cycle period of the period of the first clock signal.

The activation level section of the start signal is set as a second section defined as a section having a time 4 times that of the first section, and the start signal is a level in which the first clock signal is less than the first level at the first level. It is activated at the point of transition to the second level with.

Each of the emission control signals has the second voltage level during a third period defined as three times the time of the first period, and the emission control signals are sequentially shifted by the first period and output.

The first signal processor includes first to third transistors, a gate terminal of the first transistor receiving the second sub-control signal, a source terminal receiving the first sub-control signal, and the second The gate terminal of the transistor is connected to the drain terminal of the first transistor, the drain terminal is provided with the second sub-control signal, the gate terminal of the third transistor is provided with the second sub-control signal, and the source terminal is A source terminal of the second transistor, a drain terminal receiving the first voltage, the first signal being output through the source terminals of the second and third transistors connected to each other, and the second signal Is output through the drain terminal of the first transistor.

The second signal processing unit includes fourth to seventh transistors and first and second capacitors, a gate terminal of the fourth transistor receiving the third sub-control signal, and a drain terminal of the first node and the second capacitor. Connected to the drain terminal of the first transistor, the first electrode of the first capacitor is provided with the third sub control signal, the second electrode is connected to the drain terminal of the fourth transistor, and the fifth transistor The gate terminal of is connected to the source terminal and the second node of the third transistor, the source terminal is provided with the second voltage, the drain terminal is connected to the source terminal of the fourth transistor, and A gate terminal is connected to the second node, a drain terminal is provided with the third sub-control signal, a first electrode of the second capacitor is connected to the gate terminal of the sixth transistor, and a second electrode is the A source terminal of a sixth transistor is connected, a gate terminal of the seventh transistor is provided with the third sub control signal, a source terminal is connected to a third node, and a drain terminal is connected to the source terminal of the sixth transistor. And the third signal is provided to the third node, and the fourth signal is provided to the first node.

The third signal processing unit includes eighth to tenth transistors and a third capacitor, a gate terminal of the eighth transistor is connected to the first node, a source terminal is provided with the second voltage, and a drain terminal Is connected to the third node, a first electrode of the third capacitor is provided with the second voltage, a second electrode is connected to the third node, and a gate terminal of the ninth transistor is the third node Is connected to, a source terminal is provided with the second voltage, a drain terminal is connected to a corresponding emission control line, a gate terminal of the tenth transistor is connected to the first node, and the source terminal is connected to the corresponding It is connected to a light emission control line, a drain terminal receiving the first voltage, and the drain terminal of the ninth transistor and the source terminal of the tenth transistor are a source terminal of a first transistor of a first signal processing unit of a next stage Is connected to

An organic light emitting display device according to an embodiment of the present invention includes a display panel including a plurality of pixels connected to corresponding scan lines, corresponding data lines, and corresponding emission control lines, and a scan signal through the scan lines. A scan driver sequentially providing data to the pixels, data driving providing data voltages to the pixels through the data lines, and a plurality of light emission control signals sequentially providing emission control signals to the pixels through the light emission control lines And a light emission control driver including stages, wherein each of the stages is provided with a first voltage and generates a first signal and a second signal in response to a first sub-control signal and a second sub-control signal. A first signal processing unit receives a second voltage having a level higher than the first voltage, and generates a third signal and a fourth signal in response to a third sub-control signal, the first signal, and the second signal. 2 a signal processing unit, and a third signal processing unit receiving the first voltage and the second voltage and generating the emission control signal in response to the third signal and the fourth signal, and The first signal processor receives the emission control signal output from the previous stage as the first sub-control signal, and the first signal processor in the first stage receives the start signal as the first sub-control signal.

The light emission control driver according to an embodiment of the present invention includes a plurality of stages sequentially outputting light emission control signals through light emission control lines, and each of the stages includes a first direction control signal and a second direction control signal. In response, a bidirectional driver that outputs any one of a first input signal and a second input signal as a first sub control signal, receives a first voltage, and receives the first sub control signal and a second sub control signal. A first signal processing unit that generates a first signal and a second signal, receives a second voltage having a level higher than the first voltage, and receives a third sub-control signal, the first signal, and a second signal in response to the second signal. A second signal processing unit generating a third signal and a fourth signal, and a third signal receiving the first voltage and the second voltage, and generating the emission control signal in response to the third signal and the fourth signal A processing unit, wherein each of the bidirectional driving units receives the light emission control signal output from the previous stage as the first input signal and the emission control signal output from the next stage as the second input signal, The bidirectional driver of the first stage receives a start signal as the first input signal, and the bidirectional driver of the last stage receives the start signal as the second input signal.

The light emission control driver according to an embodiment of the present invention includes a plurality of stages sequentially outputting light emission control signals through light emission control lines, and each of the stages includes a first direction control signal and a second direction control signal. In response, a bidirectional driver that outputs any one of a first input signal and a second input signal as a first sub control signal, receives a first voltage, and receives the first sub control signal and a second sub control signal. A first signal processing unit that generates a first signal and a second signal, receives a second voltage having a level higher than the first voltage, and receives a third sub-control signal, the first signal, and a second signal in response to the second signal. A second signal processor that generates a third signal, a fourth signal, and a carry signal, and receives the first voltage and the second voltage, and generates the light emission control signal in response to the third signal and the fourth signal. A third signal processing unit, wherein each of the bidirectional driving units receives the carry signal output from the previous stage as the first input signal and provides the carry signal output from the next stage as the second input signal In response, the bidirectional driver of the first stage receives a start signal as the first input signal, and the bidirectional driver of the last stage receives the start signal as the second input signal.

The light emission control driver of the organic light emitting display device of the present invention has a simplified configuration.

1 is a block diagram of an organic light emitting display device according to a first exemplary embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of an arbitrary pixel shown in FIG. 1.
3 is a block diagram showing the configuration of a light emission control driver shown in FIG. 1.
4 is a detailed circuit diagram of the stage shown in FIG. 3.
5 is a timing diagram for explaining the operation of the first stage shown in FIG. 4.
6 and 7 are detailed circuit diagrams of a stage of an emission control driver of an organic light emitting diode display according to a second exemplary embodiment of the present invention.
8 is a detailed circuit diagram of a stage of a light emission control driver of an organic light emitting diode display according to a third exemplary embodiment of the present invention.
9 is a timing diagram for explaining the operation of the first stage shown in FIG. 8.
10 is a timing diagram for explaining the operation of the second stage shown in FIG. 8.

Advantages and features of the present invention will become apparent with reference to embodiments described below in detail together with the accompanying drawings. The present invention is not limited to the embodiments described in detail below, but may be implemented in various different forms.

In the following description, when a part is connected to another part, this includes not only the case of being directly connected but also the case of being electrically connected with another element interposed therebetween. In addition, parts not related to the present invention in the drawings are omitted to clarify the description of the present invention, and similar parts are shown with the same reference numerals throughout the specification.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram of an organic light emitting display device according to a first exemplary embodiment of the present invention.

Referring to FIG. 1, the organic light emitting display device 100 according to the first embodiment of the present invention includes a display panel 110, a timing controller 120, a scan driver 130, a data driver 140, and emission control. It includes a driving unit 150.

The display panel 110 includes a plurality of pixels PX11 to PXnm arranged in a matrix form. The pixels PX11 to PXnm are connected to a plurality of scan lines S1 to Sn extending in a row direction and a plurality of data lines D1 to Dm intersecting the scan lines S1 to Sn. Further, the pixels PX11 to PXnm are connected to a plurality of emission control lines E1 to En extending parallel to the scan lines S1 to Sn.

The scan lines S1 to Sn are connected to the scan driver 130 to receive scan signals. The data lines D1 to Dm are connected to the data driver 140 to receive data voltages. The emission control lines E1 to En are connected to the emission control driver 150 to receive emission control signals. n and m are integers greater than zero.

The timing controller 120 receives image signals R, G, and B and control signals from an external device (eg, a system board). The control signals may include a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and a main clock signal MCLK.

The timing controller 120 converts the data format of the image signals R, G, and B to meet the specifications of the interface with the data driver 140. The timing controller 120 provides the image signals R', G', and B'converted from the data format to the data driver 140.

The timing controller 120 generates a first control signal CONT1, a second control signal CONT2, and a third control signal CONT3 in response to control signals provided from the outside. The first control signal CONT1 is a control signal for controlling an operation timing of the scan driver 130. The second control signal CONT2 is a control signal for controlling an operation timing of the data driver 140. The third control signal CONT3 is a control signal for controlling an operation timing of the light emission control driver 150. The timing controller 120 provides a first control signal CONT1 to the scan driver 130, a second control signal CONT2 to the data driver 140, and controls the third control signal CONT3 to emit light. It is provided to the driving unit 150.

The scan driver 130 generates a plurality of scan signals in response to the first control signal CONT1. The scan signals are applied in row units and sequentially to the pixels PX11 to PXnm through the scan lines S1 to Sn. As a result, the pixels PX11 to PXnm can be selected in row units and sequentially.

The data driver 140 generates data voltages corresponding to the image signals R', G', and B'in response to the second control signal CONT2. Data voltages are provided to the pixels PX11 to PXnm through corresponding data lines D1 to Dm.

The third control signal CONT3 for controlling the light emission control driver 150 includes a plurality of sub control signals. The sub control signals may include a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2.

The light emission control driver 150 is provided with a first voltage VGL and a second voltage VGH having a level higher than the first voltage VGL. The light emission control driver 150 generates light emission control signals in response to the third control signal CONT3. Specifically, the light emission control driver 150 emits light using a start signal FLM, a first clock signal CLK1, a second clock signal CLK2, a first voltage VGL, and a second voltage VGH. Generate control signals. This operation will be described in detail below. The emission control signals are provided to the pixels PX11 to PXnm through the emission control lines E1 to En.

The pixels PX11 to PXnm receive the first emission voltage ELVDD and the second emission voltage ELVSS. Each of the pixels PX11 to PXnm receives data voltages through the corresponding data lines D1 to Dm in response to scan signals provided through the corresponding scan lines S1 to Sn. Each of the pixels PX11 to PXnm receives emission control signals through corresponding emission control lines E1 to En. Each of the pixels PX11 to PXnm emit light with a luminance corresponding to the data voltage provided using the first emission voltage ELVDD and the second emission voltage ELVSS. This operation will be described in detail below. The emission time of each of the pixels PX11 to PXnm may be controlled by emission control signals.

The emission control driver 150 of the present invention emits light using only the start signal FLM, the first clock signal CLK1, the second clock signal CLK2, the first voltage VGL, and the second voltage VGH. Can generate control signals. That is, separate control signals for initialization are not required in the light emission control driver 150. Accordingly, the configuration of the light emission control driver 150 can be simplified.

FIG. 2 is an equivalent circuit diagram of an arbitrary pixel shown in FIG. 1.

Since the pixels PX11 to PXnm shown in FIG. 1 have the same configuration and operate in the same manner, only an equivalent circuit diagram of one pixel is shown in FIG. 2. Therefore, the operation of one pixel will be described below.

Referring to FIG. 2, a pixel Pij includes an organic light emitting diode (OLED), a driving transistor T1, a capacitor Cst, a switching transistor T2, and a light emission control transistor T3. . The source terminal of the driving transistor T1 receives the first emission voltage ELVDD, and the drain terminal is connected to the source terminal of the emission control transistor T3. The gate terminal of the driving transistor T1 is connected to the drain terminal of the switching transistor T2. The gate terminal of the switching transistor T2 is connected to the corresponding scan line Si, and the source terminal is connected to the corresponding data line Dj.

The switching transistor T2 is turned on in response to a scan signal provided through the scan line Si. The turned-on switching transistor T2 provides the data voltage received through the data line Dj to the gate terminal of the driving transistor T1.

The first electrode of the capacitor Cst is connected to the source terminal of the driving transistor T1, and the second electrode is connected to the gate terminal of the driving transistor T1. The capacitor Cst charges the data voltage applied to the gate terminal of the driving transistor T1 and maintains it even after the switching transistor T2 is turned off.

The gate terminal of the emission control transistor T3 is connected to the corresponding emission control line Ei, and the drain terminal is connected to the anode electrode of the organic light emitting diode OLED. The light emission control transistor T3 is turned on in response to the light emission control signal provided through the light emission control line Ei. The turned-on emission control transistor T3 serves to provide the current I _OLED flowing through the driving transistor T1 to the organic light emitting diode OLED.

The organic light emitting diode OLED receives the second light emission voltage ELVSS through the cathode electrode. The organic light emitting diode OLED emits light by varying the intensity according to the amount of current I _OLED supplied from the driving transistor T1 through the emission control transistor T3.

3 is a block diagram showing the configuration of a light emission control driver shown in FIG. 1.

Referring to FIG. 3, the light emission control driver 150 includes a plurality of stages STAGE1 to STAGEn that are dependently connected to each other to sequentially output light emission control signals. The stages STAGE1 to STAGEn are connected to corresponding emission control lines E1 to En, respectively, and sequentially output emission control signals. The emission control signals are output by overlapping each other for a predetermined period.

The stages STAGE1 to STAGEn each receive a first voltage VGL and a second voltage VGH having a level higher than the first voltage VGL. Also, the stages STAGE1 to STAGEn receive a first clock signal CLK1 and a second clock signal CLK2, respectively.

Hereinafter, the emission control signals output through the emission control lines E1 to En are defined as first to nth emission control signals.

Among the stages STAGE1 to STAGEn, the first stage STAGE1 is driven by receiving the start signal FLM. Specifically, the first stage STAGE1 receives the first voltage VGL and the second voltage VGH, and responds to the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2. Thus, a first light emission control signal is generated. The first emission control signal is provided to the pixels arranged in corresponding row units through the first emission control line E1.

The stages STAGE2 to STAGEn excluding the first stage STAGE1 are connected to each other and are sequentially driven. Specifically, the stage of the current cutting is connected to the output terminal of the previous stage, and receives a light emission control signal output from the previous stage. The current stage is driven in response to a light emission control signal provided from the previous stage.

For example, the second stage STAGE2 receives a first emission control signal output from the first stage STAGE1, which is a previous stage. The second stage STAGE2 is driven in response to the first emission control signal. Specifically, the second stage STAGE2 is provided with a first voltage VGL and a second voltage VGH, and is applied to the first emission control signal, the first clock signal CLK1, and the second clock signal CLK2. In response, a second light emission control signal is generated. The second emission control signal is provided to the pixels arranged in corresponding row units through the second emission control line E2. Since the other stages STAGE3 to STAGEn also operate in the same manner, a description of the operations of the other stages STAGE3 to STAGEn will be omitted below.

4 is a detailed circuit diagram of the stage shown in FIG. 3.

Although a circuit diagram of the first stage STAGE1 and the second stage STAGE2 is shown in FIG. 4, the stages STAGE3 to STAGEn have the same configuration and operate in the same manner. Accordingly, the configuration and operation of the first stage STAGE1 will be described in detail below, and the configuration and operation of the second stage STAGE2 and other stages STAGE3 to STAGEn will be briefly described.

Referring to FIG. 4, stages STAGE1 to STAGEn each include a first signal processing unit 151, a second signal processing unit 152, and a third signal processing unit 153.

A control signal provided to the first signal processing unit 151 of each of the stages STAGE1 to STAGEn may be defined as a first sub control signal and a second sub control signal.

Specifically, the first signal processing unit 151 of each stage STAGE1 to STAGEn may receive a light emission control signal output from a previous stage as a first sub control signal. The first signal processing unit 151 of the first stage STAGE1 may receive the start signal FLM as a first sub control signal.

In addition, the first signal processing unit 151 of each of the odd-numbered stages STAGE1, STAGE3,..., STAGEn-1 may receive a first clock signal CLK1 as a second sub-control signal. The first signal processing unit 151 of each of the even-numbered stages STAGE2, STAGE4,..., STAGEn may receive a second clock signal CLK2 as a second sub-control signal.

Therefore, the first signal processing unit 151 receives the first voltage VGL and generates the first signal CS1 and the second signal CS2 in response to the first sub control signal and the second sub control signal. I can. The first signal CS1 and the second signal CS2 are provided to the second signal processing unit 152.

Taking the first stage STAGE1 as an example, the first signal processing unit 151 of the first stage STAGE1 receives the first voltage VGL, the start signal FLM and the first clock signal CLK1 In response to, a first signal CS1 and a second signal CS2 are generated. The first signal processing unit 151 provides the first signal CS1 and the second signal CS2 to the second signal processing unit 152.

The first signal processing unit 151 includes first to third transistors M1 to M3. The first to third transistors M1 to M3 may be formed of PMOS transistors.

The source terminal of the first transistor M1 receives the start signal FLM, the gate terminal receives the first clock signal CLK1, and the drain terminal is connected to the gate terminal of the second transistor M2.

The gate terminal of the second transistor M2 is connected to the drain terminal of the first transistor M1, the source terminal is connected to the source terminal of the third transistor M3, and the drain terminal receives the first clock signal CLK1. It is provided.

* The gate terminal of the third transistor M3 receives the first clock signal CLK1 and is connected to the drain terminal of the second transistor M2. The source terminal of the third transistor M3 is connected to the source terminal of the second transistor M2, and the drain terminal receives the first voltage VGL.

The first signal CS1 is output through source terminals of the second and third transistors M2 and M3 connected to each other. The second signal CS2 is output through the drain terminal of the first transistor M1.

A control signal provided to the second signal processing unit 152 of each of the stages STAGE1 to STAGEn may be defined as a third sub-control signal.

Specifically, the second signal processing unit 152 of each of the odd-numbered stages STAGE1, STAGE3,..., STAGEn-1 may receive the second clock signal CLK2 as a third sub-control signal. The second signal processing unit 152 of each of the even-numbered stages STAGE2, STAGE4,..., STAGEn may receive a first clock signal CLK1 as a third sub-control signal.

The second signal processing unit 152 receives the second voltage VGH, and in response to the third sub-control signal, the first signal CS1, and the second signal CS3, the third signal CS3 and the fourth signal Signal CS4 can be generated. The third signal CS3 and the fourth signal CS4 are provided to the second signal processing unit 152.

Taking the first stage STAGE1 as an example, the second signal processing unit 152 of the first stage STAGE1 receives the second voltage VGH, and the second clock signal CLK2 and the first signal processing unit ( A third signal CS3 and a fourth signal CS3 are generated in response to the first signal CS1 and the second signal CS2 provided from the 151. The second signal processing unit 152 provides the third signal CS3 and the fourth signal CS4 to the third signal processing unit 153.

The second signal processing unit 152 includes fourth to seventh transistors M4 to M7 and first and second capacitors C1 and C2. The fourth to seventh transistors M4 to M7 may be formed of PMOS transistors.

The gate terminal of the fourth transistor M4 receives the second clock signal CLK2, the drain terminal is connected to the gate terminal of the first node N1 and the second transistor M2, and the source terminal is a fifth transistor. It is connected to the drain terminal of (M5).

The first electrode of the first capacitor C1 receives the second clock signal CLK2, and the second electrode is connected to the drain terminal of the fourth transistor M4 and the first node N1.

The gate terminal of the fifth transistor M5 is connected to the source terminal and the second node N2 of the third transistor M3, the source terminal is supplied with the second voltage VGH, and the drain terminal is the fourth transistor ( It is connected to the source terminal of M4).

The gate terminal of the sixth transistor M6 is connected to the second node N2, the source terminal is connected to the drain terminal of the seventh transistor M7, and the drain terminal receives the second clock signal CLK2.

The first electrode of the second capacitor C2 is connected to the gate terminal of the sixth transistor M6, and the second electrode is connected to the source terminal of the sixth transistor M6.

The gate terminal of the seventh transistor M7 receives the second clock signal CLK2, the source terminal is connected to the third node N3, and the drain terminal is connected to the source terminal of the sixth transistor M6.

The third signal CS3 is provided to the third node N3. The fourth signal CS4 is provided to the first node N1.

The third signal processing unit 153 of the first stage STAGE1 is provided with a first voltage VGL and a second voltage VGH, and a third signal CS3 and a third signal received from the second signal processing unit 152. In response to the 4 signal CS4, a first emission control signal is generated. The first emission control signal is provided to the pixels through the first emission control line E1. The first emission control signal is provided to the first signal processing unit 151 of the second stage STAGE2.

The third signal processing unit 153 includes eighth to tenth transistors M8 to M10 and a third capacitor C3. The eighth to tenth transistors M8 to M10 may be formed of PMOS transistors.

The gate terminal of the eighth transistor M8 is connected to the first node N1, the source terminal is supplied with the second voltage VGH, and the drain terminal is connected to the third node N3.

The first electrode of the third capacitor C3 receives the second voltage VGH, and the second electrode is connected to the third node N3.

The gate terminal of the ninth transistor M9 is connected to the third node N3, the source terminal is supplied with the second voltage VGH, and the drain terminal is connected to the first emission control line E1.

The gate terminal of the tenth transistor M10 is connected to the first node N1, the source terminal is connected to the first emission control line E1, and the drain terminal receives the first voltage VGL.

The drain terminal of the ninth transistor M9 and the source terminal of the tenth transistor M10 are connected to the source terminal of the first transistor M1 of the first signal processing unit 151 of the second stage STAGE2.

Specific operations of the transistors M1 to M10 by the start signal FLM, the first clock signal CLK1, and the second clock signal CLK2 will be described in detail below with reference to FIG. 5.

5 is a timing diagram for explaining the operation of the first stage shown in FIG. 4.

Referring to FIG. 5, the first clock signal CLK1 and the second clock signal CLK2 have the same frequency. That is, the first clock signal CLK1 and the second clock signal CLK2 have the same first period T1. The second clock signal CLK2 is a signal in which the first clock signal CLK1 is shifted by a half cycle of the first period T1 of the first clock signal CLK1. The period in which the second clock signal CLK2 is shifted from the first clock signal CLK1 may be defined as a first period 1H.

The start signal FLM is provided only to the first stage STAGE1, and the high level period of the start signal FLM may be defined as the second period 4H. The second period 4H may be set as a period twice the period of the first clock signal CLK1 and the second clock signal CLK2. That is, the second section 4H may be set as a section having a time 4 times that of the first section 1H.

The start signal FLM may transition from a low level to a high level when the first clock signal CLK1 transitions from a high level to a low level. As described above, after transitioning from the low level to the high level, the start signal FLM maintains the high level during the second period 4H. That is, the start signal FLM is activated when the first clock signal CLK1 transitions from the high level to the low level, and the activated period is maintained during the second period 4H.

Hereinafter, a high level of each signal is defined as a first level, and a low level lower than the high level is defined as a second level. Further, the first voltage VGL may have a second level, and the second voltage VGH may have a first level.

At a first time t1, the start signal FLM and the first clock signal CLK1 have a second level, and the second clock signal CLK2 has a first level.

The first clock signal CLK1 having the second level is provided to the gate of the first transistor M1 and the gate of the third transistor M3. Accordingly, the first transistor M1 and the third transistor M3 are turned on.

The start signal FLM having the second level through the turned-on first transistor M1 is provided to the gate of the second transistor M2 and the first node N1. Accordingly, the second transistor M2 is turned on, and the voltage of the first node N1 has a second level.

A first clock signal CLK1 having a second level through the turned-on second transistor M2 and a first voltage VGL through the turned-on third transistor M3 are provided to the second node N2. Accordingly, the voltage of the second node N2 has a second level.

The second clock signal CLK2 having the first level is provided to the fourth transistor M4 and the seventh transistor M7. Accordingly, the fourth and seventh transistors M4 and M7 are turned off.

Since the voltage of the first node N1 has the second level, the eighth transistor M8 is turned on. The second voltage VGH is provided to the third node N3 through the turned-on eighth transistor M8. Accordingly, the voltage of the third node N3 has a first level. The third capacitor C3 is charged with the second voltage VGH. That is, the voltage having the first level is charged in the third capacitor C3. Since the voltage of the third node N3 has a first level, the ninth transistor M9 is turned off.

Since the voltage of the first node N1 has a second level, the tenth transistor M10 is turned on. The first voltage VGL is provided to the first emission control line E1 by the turned-on tenth transistor M10. Therefore, the first light emission control signal has a second level.

At a second time t2, the start signal FLM has a second level, and the first clock signal CLK1 and the second clock signal CLK2 have a first level. The first transistor M1 and the third transistor M3 are turned off by the first clock signal CLK1 having the first level.

Since the voltage of the first node N1 is maintained at the second level, the second transistor M2 is turned on. A first clock signal CLK1 having a first level is provided to the second node N2 through the turned-on second transistor M2. Accordingly, the voltage of the second node N2 has a first level.

Since the voltage of the first node N1 has a second level, the eighth transistor M8 and the tenth transistor M10 are turned on. Since the second voltage VGH is provided to the third node N3 through the turned-on eighth transistor M8, the voltage of the third node N3 is maintained at the first level.

Since the voltage of the third node N3 has a first level and the voltage of the first node N1 has a second level, the ninth transistor M9 is turned off, and the tenth transistor M10 is turned off. Is on. Accordingly, the first light emission control signal maintains the second level.

At a third time t3, the second clock signal CLK2 transitions from the first level to the second level and then transitions from the second level to the first level again. Accordingly, the potential of the first node N1 is bootstrapped by the amount of change in the potential of the second clock signal CLK2 due to coupling of the first capacitor C1. That is, the first node N1 having the voltage of the second level at the second time t2 is in the second level section of the second clock signal CLK2 due to the coupling of the first capacitor C1. It has a voltage of a third level having a voltage level lower than that of the second level. General PMOS transistors have better driving characteristics when a lower voltage level is applied. In the second level period of the second clock signal CLK2, since the voltage of the first node N1 has a third level lower than the second level, the driving characteristics of the eighth and tenth transistors M8 and M10 are improved. Can be. The first emission control signal maintains the second level.

At a fourth time t4, the start signal FLM and the second clock signal CLK2 have a first level, and the first clock signal CLK1 has a second level.

The first transistor M1 is turned on by the first clock signal CLK1 having the second level, and the start signal FLM having the first level is provided to the first node N1. The voltage of the first node N1 has a first level. Since the voltage of the first node N1 has a first level, the second transistor M2 and the tenth transistor M10 are turned off.

The third transistor M3 is turned on by the first clock signal CLK1 having the second level, and the first voltage VGL is provided to the second node N2. Accordingly, the voltage of the second node N2 has a second level.

The seventh transistor M7 is turned off by the second clock signal CLK2 having the first level. Since the voltage of the first node N1 has a first level, the eighth transistor M8 is turned off. The voltage of the third node N3 is maintained at the first level by the third capacitor C3. Since the voltage of the third node N3 maintains the first level, the ninth transistor M9 is turned off. Accordingly, the first light emission control signal maintains the second level.

At a fifth time t5, the start signal FLM and the first clock signal CLK1 have a first level, and the second clock signal CLK2 has a second level.

The first transistor M1 and the third transistor M3 are turned off by the first clock signal CLK1 having the first level. Since the voltage of the first node N1 maintains the first level, the second transistor M2, the eighth transistor M8, and the tenth transistor M10 are turned off.

The fourth transistor M4 and the seventh transistor M7 are turned on by the second clock signal CLK2 having the second level. Also, since the voltage of the second node M2 has a second level, the fifth and sixth transistors M5 and M6 are turned on.

Like the bootstrap described above, the potential of the second node N2 is bootstrapped by the amount of change in the potential of the second clock signal CLK2 by coupling of the second capacitor C2. That is, in the second level period of the second clock signal CLK2, the voltage of the second node N2 has a third level lower than the second level.

A second clock signal CLK2 having a second level is provided to the third node N3 through the turned-on sixth and seventh transistors M6 and M7. Accordingly, the voltage of the third node N3 has the second level at the fifth time t5. Since the voltage of the third node N3 has the second level, the ninth transistor M9 is turned on.

* Since the ninth transistor M9 is turned on and the tenth transistor M10 is turned off, the first emission control signal has a first level.

At a sixth time t6, the start signal FLM and the first clock signal CLK1 have a second level, and the second clock signal CLK2 has a first level. Referring to the operation of the first time t6 described above, the first emission control signal has a second level at the sixth time t6.

A section in which the first emission control signal has a first level may be defined as a third section 3H. The third section 3H may be set as a section having a time three times that of the first section 1H.

The first emission control signal is provided to the pixels through the second stage STGAE2 and the first emission control line E1. The second stage STGAE2 generates a second emission control signal in response to the first emission control signal, the first clock signal CLK1, and the second clock signal CLK2.

The second emission control signal is output by being shifted by a first period 1H from the first emission control signal. That is, the light emission control signals output from the stages STAGE1 to STAGEn are sequentially shifted by the first period 1H and then output. Specifically, the emission control signal output from the current stage is a signal obtained by shifting the emission control signal output from the previous stage by a first period (1H).

As a result, the emission control driver 150 of the organic light emitting display device according to the first embodiment of the present invention receives the first voltage VGL and the second voltage VGH, and receives the start signal FLM and the first clock. Light emission control signals may be generated in response to the signal CLK1 and the second clock signal CLK2. Accordingly, the configuration of the light emission control driver 150 can be simplified.

6 and 7 are detailed circuit diagrams of a stage of an emission control driver of an organic light emitting diode display according to a second exemplary embodiment of the present invention.

6 illustrates a circuit diagram of a first stage STAGE1 and a second stage STAGE2, and FIG. 7 illustrates an n-1th stage STAGEn-1 and an nth stage STAGEn. However, substantially the plurality of stages STAGE1 to STAGEn have the same configuration and operate in the same manner. The stages shown in FIGS. 6 and 7 operate in the same manner as the stages shown in FIG. 4 except for including a bidirectional driving unit. Therefore, hereinafter, only the configuration different from the stages shown in FIG. 4 will be described.

6 and 7, the bidirectional driver 154 of each of the stages STAGE1 to STAGEn receives a first direction control signal BI_CTL and a second direction control signal BI_CTLB. Each bidirectional driver 154 outputs one of a first input signal and a second input signal as a first sub control signal in response to the first direction control signal BI_CTL and the second direction control signal BI_CTLB.

Specifically, the bidirectional driver 154 of the current stage receives the emission control signal output from the previous stage as a first input signal and receives the emission control signal output from the next stage as a second input signal. In addition, the bidirectional driver 154 of the first stage STAGE1 receives a start signal FLM as a first input signal, and the bidirectional driver 154 of the n-th stage STAGEn receives a start signal (FLM) as a second input signal. FLM) is provided.

For example, since there is no previous stage, the first emission control signal output from the first stage STAGE1 is provided to the second stage STAGE2 which is the next stage. The second emission control signal output from the second stage STAGE1 is provided to the third stage STAGE3 which is the next stage and the first stage STAGE1 which is the previous stage. Since there is no next stage, the n-th emission control signal output from the n-th stage STAGEn is provided to the n-1th stage STAGEn-1, which is the previous stage. The n-1th emission control signal output from the n-1th stage STAGEn-1 is provided to the next stage, the n-th stage STAGEn and the previous stage, the n-2th stage STAGEn-2.

The bidirectional driver 154 includes an eleventh transistor M11 and a twelfth transistor M12, respectively.

The gate terminal of the eleventh transistor M11 receives the first direction control signal BI_CTL, and the source terminal receives the first input signal. The gate terminal of the twelfth transistor M12 receives the second direction control signal BI_CTLB, and the source terminal receives the second input signal. Drain terminals of the eleventh and twelfth transistors M11 and M12 are connected to the source terminal of the first transistor M1 of the first signal processing unit 151.

In the case of the first stage STAGE1, the gate terminal of the eleventh transistor M11 of the bidirectional driver 154 of the first stage STAGE1 receives the first direction control signal BI_CTL, and the source terminal receives the start signal ( FLM) is provided. The gate terminal of the twelfth transistor M12 receives the second direction control signal BI_CTLB, and the source terminal receives the second emission control signal output from the second stage STAGE2. Drain terminals of the eleventh and twelfth transistors M11 and M12 are connected to the source terminal of the first transistor M1.

In the case of the n-th stage STAGEn, the gate terminal of the eleventh transistor M11 of the bidirectional driver 154 of the n-th stage STAGEn receives the first direction control signal BI_CTL, and the source terminal is n- The n-1th emission control signal output from the first stage STAGEn-1 is provided. The gate terminal of the twelfth transistor M12 receives the second direction control signal BI_CTLB, and the source terminal receives the start signal FLM. Drain terminals of the eleventh and twelfth transistors M11 and M12 are connected to the source terminal of the first transistor M1.

The gate terminal of the eleventh transistor M11 of the bidirectional driver 154 of each of the other stages STAGE2 to STAGEn-1 receives the first direction control signal BI_CTL, and the source terminal emits light output from the previous stage. It is provided with a control signal. The gate terminal of the twelfth transistor M11 receives the second direction control signal BI_CTLB, and the source terminal receives the emission control signal output from the next stage. Drain terminals of the eleventh and twelfth transistors M11 and M12 are connected to the source terminal of the first transistor M1.

The first direction control signal BI_CTL and the second direction control signal BI_CTLB have different levels. For example, when the first direction control signal BI_CTL has a first level (or a high level), the second direction control signal BI_CTLB has a second level (or a low level) having a level lower than the first level. Can have.

When the first direction control signal BI_CTL is at the second level, the eleventh transistor M11 of the bidirectional driver 154 of each of the stages STAGE1 to STAGEn is turned on, and the twelfth transistor M12 is turned off. do. Accordingly, the start signal FLM is provided to the bidirectional driver 154 of the first stage STAGE1. Also, a second light emission control signal output from the first stage STAGE1 is provided to the second stage STAGE2. That is, the stages STAGE1 to STAGEn of the emission control driver according to the second embodiment operate in the same manner as the stages illustrated in FIG. 4. Light emission control signals output from the stages STAGE1 to STAGEn are sequentially provided to the pixels starting from the first light emission control signal. Accordingly, pixels can be driven from top to bottom.

When the second direction control signal BI_CTLB is at the second level, the eleventh transistor M11 of the bidirectional driver 154 of each of the stages STAGE1 to STAGEn is turned off, and the twelfth transistor M12 is turned on. do. Accordingly, the start signal FLM is provided to the bidirectional driver 154 of the n-th stage STAGEn. Also, the nth light emission control signal output from the nth stage STAGEn is provided to the n-1th stage STAGEn-1. Through this operation, the emission control signals output from the stages STAGE1 to STAGEn are sequentially provided to the pixels starting from the n-th emission control signal. Accordingly, the pixels can be driven from the bottom to the top.

The emission control driver of the organic light emitting display device according to the second embodiment of the present invention that can be driven in both directions receives a first voltage VGL and a second voltage VGH, and receives a start signal FLM and a first clock. Light emission control signals may be generated in response to the signal CLK1 and the second clock signal CLK2. Accordingly, the configuration of the light emission control driver can be simplified.

8 is a detailed circuit diagram of a stage of an emission control driver of an organic light emitting diode display according to a third exemplary embodiment of the present invention.

8 is a circuit diagram of a first stage STAGE1 and a second stage STAGE2 of the emission control driver. However, substantially the plurality of stages STAGE1 to STAGEn of the light emission control driver have the same configuration and operate in the same manner. Accordingly, the configuration of the first stage STAGE1 will be described in detail below, and the configuration of the other stages STAGE2 to STAGEn will be briefly described.

The stages shown in FIG. 8 operate in the same manner as the stages shown in FIGS. 6 and 7 except that the configuration of the second signal processing unit is different. Therefore, hereinafter, only the configuration different from the stages shown in FIGS. 6 and 7 will be described.

Referring to FIG. 8, the bidirectional driver 154 of each of the stages STAGE1 to STAGEn receives a carry signal CA output from a previous stage as a first input signal and receives a carry signal CA output from a next stage. ) Is provided as a second input signal. In addition, the bidirectional driver 154 of the first stage STAGE1 receives a start signal FLM as a first input signal, and the bidirectional driver 154 of the n-th stage STAGEn receives a start signal FLM as a second input signal. ) Is provided.

The carry signal CA is output from the second signal processing unit 152 of each of the stages STAGE1 to STAGEn. To output the carry signal CA, the second signal processing unit 152 of each of the stages STAGE1 to STAGEn includes fourth to seventh transistors M4 to M7, and first and second capacitors C1 and C2. ), and thirteenth and fourteenth transistors M13 and M14. The configuration of the second signal processing unit 152 excluding the connection configuration of the first capacitor C1, the thirteenth transistor M13, and the fourteenth transistor M14 is the configuration of the second signal processing unit 152 shown in FIG. Is substantially the same as Accordingly, a connection configuration of the first capacitor C1, the thirteenth transistor M13, and the fourteenth transistor M14 of the second signal processing unit 152 of the first stage STAGE1 will be described below.

The gate terminal of the thirteenth transistor M13 is connected to the gate of the fifth transistor M5 and the second node N2, the source terminal is provided with the second voltage VGH, and the drain terminal is the fourth node N4. ).

The gate terminal of the 14th transistor M14 is connected to the first electrode of the first capacitor C1, the source terminal is connected to the fourth node N4, and the drain terminal receives the second clock signal CLK2. .

The first electrode of the first capacitor C1 is connected to the gate terminal of the 14th transistor M14 and the drain terminal of the fourth transistor M4, and the second electrode is connected to the fourth node N4.

The signal output from the fourth node N4 is defined as a carry signal CA, and is provided to the bidirectional driver 154 of the second stage STAGE2, which is a next stage.

The gap signal CA of each of the stages STAGE1 to STAGEn is provided to the bidirectional driving units 154 of the previous stage and the next stage. For example, since there is no previous stage, the carry signal CA output from the first stage STAGE1 is provided to the bidirectional driver 154 of the second stage STAGE2 which is the next stage. The carry signal CA output from the second stage STAGE1 is provided to the bidirectional driving units 154 of the third stage STAGE3 which is the next stage and the first stage STAGE1 which is the previous stage, respectively.

Since there is no next stage, the carry signal CA output from the n-th stage STAGEn is provided to the bidirectional driver 154 of the n-1th stage STAGEn-1 which is the previous stage. The carry signal CA output from the n-1th stage STAGEn-1 is the bidirectional driving units 154 of the n-th stage STAGEn as the next stage and the n-2th stage STAGEn-2 as the previous stage. ) Are provided respectively.

That is, the stages shown in FIG. 8 do not provide light emission control signals to the previous stage and the next stage, like the stages shown in FIGS. 6 and 7, but provide a carry signal to the previous stage and the next stage stages. Accordingly, the stages can be driven using a carry signal rather than an emission control signal.

The output of the carry signal CA of the first stage STGAE1 according to the driving of the thirteenth and fourteenth transistors M13 and M14 will be described in detail below with reference to FIG. 9. Further, the operation of the second stage STAGE driven by receiving the carry signal CA from the first stage STAGE1 will be described in detail below with reference to FIG. 10.

9 is a timing diagram for explaining the operation of the first stage shown in FIG. 8.

Although not shown in the drawing, the first direction control signal BI_CTL has a second level and the second direction control signal BT_CTLB has a first level. That is, the stages STAGE1 to STAGEn are driven from the top to the bottom.

Except for the addition of the voltage of the fourth node N4 output as the carry signal CA, the waveforms of the signals shown in FIG. 9 are the same as those of the signals shown in FIG. 5. That is, the first stage STAGE1 shown in FIG. 8 operates substantially the same as the first stage STAGE1 shown in FIG. 4 except for an operation of outputting the carry signal CA. Therefore, only a change in the voltage level of the fourth node N4 will be described below.

In a section except for the section N1_H in which the first node N1 has a first level, the first node N1 has a second level and a third level. When the first node N1 is at the second level and the third level, the fourteenth transistor M14 is turned on. That is, the second clock signal CLK2 is provided to the fourth node N4 in a period other than the period N1_H in which the first node N1 has the first level. Accordingly, the fourth node N4 has the same waveform as the second clock signal CLK2 in a period except for the period N1_H in which the first node N1 has the first level.

When the voltage of the first node N1 has the first level, the fourteenth transistor M14 is turned off. When the voltage of the first node N1 is converted from the second level to the first level, the voltage of the second node N2 is converted from the first level to the second level. When the voltage of the second node N2 has the second level, the thirteenth transistor M13 is turned on. The second voltage VGH is provided to the fourth node N4 through the turned-on thirteenth transistor M13. Accordingly, the voltage of the fourth node N4 has a first level. While the thirteenth transistor M13 is turned on, the voltage of the fourth node N4 maintains the first level. That is, during the period N2_L in which the voltage of the second node N2 has the second level, the voltage of the fourth node N4 maintains the first level.

In the absence of the fourteenth transistor M14, the second clock signal CLK2 is continuously provided to the first capacitor C1. Accordingly, the first capacitor C1 repeatedly charges the voltages of the first level and the second level. When the first capacitor C1 repeatedly charges the voltages of the first level and the second level, a delay of the second clock signal CLK2 may occur due to the load of the first capacitor C1. That is, the normal second clock signal CLK2 may not be provided to the second signal processing unit 152.

The fourteenth transistor M14 is turned off when the voltage of the first node N1 has a first level. Since the second clock signal CLK2 is not affected by the third capacitor C3 while the fourteenth transistor M14 is turned off, a signal delay of the second clock signal CLK2 may be prevented.

The thirteenth transistor M13 maintains the fourth node N4 at a constant level when the fourteenth transistor M14 is turned off. That is, when the fourteenth transistor M14 is turned off, the thirteenth transistor M13 is turned on to maintain the voltage of the fourth node N4 at the first level.

The emission control driver of the organic light emitting display device according to the third exemplary embodiment of the present invention includes a start signal FLM, a carry signal CA, a first clock signal CLK1, a second clock signal CLK2, and a second voltage. Light emission control signals can be generated using only (VGH). That is, separate control signals for initialization are not required in the light emission control driver 150. Accordingly, the configuration of the light emission control driver 150 can be simplified.

10 is a timing diagram for explaining the operation of the second stage shown in FIG. 8.

Referring to FIG. 10, the voltage level of the fourth node N4 of the first stage STAGE1 is provided to the second stage STAGE2 as a carry signal CA. At a first time t1, the carry signal CA and the second clock signal CLK2 have a second level, and the first clock signal CLK1 has a first level.

The second clock signal CLK2 having the second level is provided to the gate of the first transistor M1 and the gate of the third transistor M3. Accordingly, the first transistor M1 and the third transistor M3 are turned on.

The carry signal CA having a second level through the turned-on first transistor M1 is provided to the gate of the second transistor M2 and the first node N1. Accordingly, the second transistor M2 is turned on, and the voltage of the first node N1 has a second level.

A second clock signal CLK2 having a second level through the turned-on second transistor M2 and a first voltage VGL through the turned-on third transistor M3 are provided to the second node N2. . Accordingly, the voltage of the second node N2 has a second level.

The first clock signal CLK1 having the first level is provided to the fourth transistor M4 and the seventh transistor M7. Accordingly, the fourth and seventh transistors M4 and M7 are turned off.

Since the first node N1 has the second level, the eighth transistor M8 is turned on. The second voltage VGH is provided to the third node N3 through the turned-on eighth transistor M8. Accordingly, the third node N3 has a first level. Since the third node N3 has a first level, the ninth transistor M9 is turned off.

Since the first node N1 has a second level, the tenth transistor M10 is turned on. The first voltage VGL is provided to the first emission control line E1 by the turned-on tenth transistor M10. Therefore, the first light emission control signal has a second level.

At the second time t2, the carry signal CA, the first clock signal CLK1, and the second clock signal CLK2 have a first level. The first transistor M1 and the third transistor M3 are turned off by the second clock signal CLK2 having the first level.

Since the first node N1 is maintained at the second level, the second transistor M2 is turned on. A first clock signal CLK1 having a first level is provided to the second node N2 through the turned-on second transistor M2. Accordingly, the voltage of the second node N2 has a first level.

Since the first node N1 has a second level, the eighth transistor M8 and the tenth transistor M10 are turned on. Accordingly, since the second voltage VGH is provided to the third node N3 through the turned-on eighth transistor M8, the third node N3 maintains the first level.

Since the third node N3 has a first level and the first node N1 has a second level, the ninth transistor M9 is turned off and the tenth transistor M10 is turned on. Accordingly, the first light emission control signal maintains the second level.

The operation in which the potential of the first node N1 is changed due to the coupling of the first capacitor C1 at the third time t3 has been described in detail with reference to FIG. 5, and thus a description thereof will be omitted.

At a fourth time t4, the carry signal CA and the first clock signal CLK1 have a first level, and the second clock signal CLK2 has a second level.

The first transistor M1 is turned on by the second clock signal CLK2 having the second level, and the carry signal CA having the first level is provided to the first node N1. The voltage of the first node N1 has a first level. Since the first node N1 has a first level, the second transistor M2 and the tenth transistor M10 are turned off.

The third transistor M3 is turned on by the second clock signal CLK2 having the second level, and the first voltage VGL is provided to the second node N2. Accordingly, the voltage of the second node N2 has a second level.

The seventh transistor M7 is turned off by the first clock signal CLK1 having the first level. Since the voltage of the first node N1 has a first level, the eighth transistor M8 is turned off. The voltage of the third node N3 is maintained at the first level by the third capacitor C3. Since the voltage of the third node N3 maintains the first level, the ninth transistor M9 is turned off. As a result, the first light emission control signal maintains the second level.

At a fifth time t5, the carry signal CA and the second clock signal CLK2 have a first level, and the first clock signal CLK1 has a second level.

The first transistor M1 and the third transistor M3 are turned off by the second clock signal CLK2 having the first level. Since the voltage of the first node N1 maintains the first level, the second transistor M2, the eighth transistor M8, and the tenth transistor M10 are turned off.

The fourth transistor M4 and the seventh transistor M7 are turned on by the first clock signal CLK1 having the second level. Also, since the voltage of the second node N2 has a second level, the fifth transistor M5 and the sixth transistor M6 are turned on.

A second clock signal CLK2 having a second level is provided to the third node N3 through the turned-on sixth transistor M6 and the seventh transistor M7. Accordingly, the voltage of the third node N3 has the second level at the fifth time t5. Since the voltage of the third node N3 has the second level, the ninth transistor M9 is turned on. Since the ninth transistor M9 is turned on and the tenth transistor M10 is turned off, the first emission control signal has a first level.

At a sixth time t6, the carry signal CA and the second clock signal CLK2 have a second level, and the first clock signal CLK1 has a first level. Referring to the operation of the first time t1 described above, the first emission control signal has a second level at the sixth time t6.

By this operation, the current stage generates a light emission control signal in response to the first click signal CLK1, the second clock signal CLK2, and the carry signal CA provided from the previous stage. Further, the emission control signals output from the stages STAGE1 to STAGEn are sequentially shifted by a first period 1H and then output.

Although described with reference to the above embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the present invention described in the following claims. I will be able to. In addition, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, and all technical ideas within the scope of the following claims and equivalents should be construed as being included in the scope of the present invention. .

100: organic light emitting display device 110: display panel
120: timing controller 130: scan driver
140: data driver 150: light emission control driver
151: first signal processing unit 152: second signal processing unit
153: third signal processing unit 154: bidirectional driving unit

Claims (14)

Including a plurality of stages sequentially outputting light emission control signals through light emission control lines,
Each of the stages,
A first signal processor configured to receive a first voltage and generate a first signal and a second signal in response to the first sub control signal and the second sub control signal;
A second signal processing unit receiving a second voltage having a level higher than the first voltage and generating a third signal and a fourth signal in response to a third sub-control signal, the first signal, and the second signal; And
A third signal processing unit receiving the first voltage and the second voltage and generating the emission control signal in response to the third signal and the fourth signal,
The first signal processing unit of each stage is provided with the emission control signal output from the previous stage as the first sub-control signal, and the first signal processing unit of the first stage starts as the first sub-control signal Receive a signal,
When the third sub-control signal changes from the first level to the second level, the fourth signal changes from the second level to a third level,
When the start signal changes from the second level to the first level or after the start signal changes from the second level to the first level, the fourth signal of the first stage is Change from the second level to the first level,
The second level is lower than the first level, and the third level is lower than the second level. The method of claim 1,
When the second sub-control signal is converted from the first level to the second level, the fourth signal is A light emission control driver that changes from the second level to the first level. Includes a plurality of stages sequentially outputting light emission control signals through light emission control lines,
Each of the stages,
A first power source outputting a first voltage;
A second power supply outputting a second voltage higher than the first voltage;
A first light emission control line;
A first transistor including a source terminal receiving a first sub-control signal, a gate terminal receiving a second sub-control signal, and a drain terminal;
A ninth transistor including a gate terminal receiving a third signal, a source terminal receiving the second voltage, and a drain terminal connected to the first emission control line;
A tenth transistor including a gate terminal connected to the drain terminal of the first transistor, a source terminal connected to the first emission control line, and a drain terminal to which the first voltage is applied; And
A light emission control driver including a first capacitor including a first electrode receiving a third sub-control signal and a second electrode connected to the gate terminal of the tenth transistor. The method of claim 3,
A light emission control driver provided to a next stage as the first light emission control signal output from the first light emission control line as the first sub control signal. The method of claim 3,
A third capacitor including a first electrode receiving the second voltage and a second electrode connected to the gate terminal of the ninth transistor; And
A light emission control driver further comprising an eighth transistor including a gate terminal connected to the gate terminal of the tenth transistor, a source terminal receiving the second voltage, and a drain terminal connected to the gate terminal of the ninth transistor. The method of claim 5,
The light emission control driver further comprising a second capacitor including a first electrode and a second electrode connected to the gate terminal of the ninth transistor and receiving the third sub control signal. The method of claim 6,
Further comprising a sixth transistor including a gate terminal connected to the first electrode of the second capacitor, a drain terminal receiving the third sub control signal, and a source terminal connected to the second electrode of the second capacitor. Light emission control driver. The method of claim 7,
A second transistor including a gate terminal connected to the drain terminal of the first transistor, a drain terminal receiving the second sub control signal, and a source terminal connected to the first electrode of the second capacitor; And
A light emission control driver further comprising a third transistor including a gate terminal receiving the second sub-control signal, a source terminal connected to the source terminal of the second transistor, and a drain terminal receiving the first voltage. The method of claim 3,
The tenth transistor is controlled by three voltage levels of the drain terminal of the first transistor, the gate terminal of the tenth transistor, and a first node connected to the second electrode of the first capacitor. Driving part. The method of claim 9,
A light emission control driver provided to a next stage as the first light emission control signal output from the first light emission control line as the first sub control signal. The method of claim 9,
A third capacitor including a first electrode receiving the second voltage and a second electrode connected to the gate terminal of the ninth transistor; And
A light emission control driver further comprising an eighth transistor including a gate terminal connected to the gate terminal of the tenth transistor, a source terminal receiving the second voltage, and a drain terminal connected to the gate terminal of the ninth transistor. The method of claim 11,
The light emission control driver further comprising a second capacitor including a first electrode and a second electrode connected to the gate terminal of the ninth transistor and receiving the third sub control signal. The method of claim 12,
Further comprising a sixth transistor including a gate terminal connected to the first electrode of the second capacitor, a drain terminal receiving the third sub control signal, and a source terminal connected to the second electrode of the second capacitor. Light emission control driver. The method of claim 13,
A second transistor including a gate terminal connected to the drain terminal of the first transistor, a drain terminal receiving the second sub control signal, and a source terminal connected to the first electrode of the second capacitor; And
A light emission control driver further comprising a third transistor including a gate terminal receiving the second sub-control signal, a source terminal connected to the source terminal of the second transistor, and a drain terminal receiving the first voltage.

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