US8996959B2 - Adaptive copy-back method and storage device using same - Google Patents

Adaptive copy-back method and storage device using same Download PDF

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US8996959B2
US8996959B2 US13/716,360 US201213716360A US8996959B2 US 8996959 B2 US8996959 B2 US 8996959B2 US 201213716360 A US201213716360 A US 201213716360A US 8996959 B2 US8996959 B2 US 8996959B2
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error
copy
data
corrected
buffer
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US20130159815A1 (en
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Hyun-Uk Jung
Dong-gil Lee
Jin-Yeong Kim
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7205—Cleaning, compaction, garbage collection, erase control

Definitions

  • the inventive concept relates to methods of operating a storage device. More particularly, the inventive concept relates to adaptive copy-back methods for selectively performing copy-back operations in consideration of storage device performance. The inventive concept also relates to storage devices operating in this manner.
  • Non-volatile memory devices have enabled, for example, the replacement of the conventional hard disk drive (HDD) with the solid state drive (SSD).
  • the SSD typically arranges a plurality of non-volatile memory devices according to a plurality of channels.
  • the data storage space provided by the non-volatile memory devices of the SSD must be routinely managed to ensure efficient storage of data. Such management includes a so-called “garbage collection” process.
  • the garbage collection process essentially reallocates (or recycles) available memory space into larger and more useful memory blocks by consolidating a number of smaller or fractured memory blocks.
  • One or more copy-back operations are required to perform the garbage collection process.
  • a data access bottleneck to a buffer memory in the SSD may occur when non-volatile memory devices associated with multiple channels seek to simultaneously perform copy-back operations as part of overlapping garbage operations. This bottleneck may dramatically reduce performance of the SSD.
  • the inventive concept provides an adaptive copy-back method capable of suppressing performance reduction of a storage device due to a bottleneck phenomenon of accesses to a buffer memory in consideration of reliability of the storage device.
  • the inventive concept also provides a storage device performing a copy-back operation capable of suppressing performance reduction of a storage device due to a bottleneck phenomenon of accesses to a buffer memory in consideration of reliability of the storage device.
  • the inventive concept provides an adaptive copy-back method comprising; reading data from a source page of a non-volatile memory device and storing the data in a page buffer with the non-volatile memory device, performing error correction on the data stored in the page buffer according to a given unit size using error correction code (ECC) to determine a number of error-corrected bits and to generate error-corrected data, storing the error-corrected data in a buffer memory external to the non-volatile memory device, and selectively performing either an external copy-back process using the error-corrected stored in the buffer memory, or an internal copy-back operation using the data stored in the page buffer in accordance with the number of error-corrected bits.
  • ECC error correction code
  • the inventive concept provides an adaptive copy-back method comprising; determining whether a performance reduction condition occurs due to a bottleneck phenomenon related to input/output (I/O) accesses to a buffer memory of a storage device, selecting a first copy-back operation if the performance reduction condition occurs and selecting a second copy-back operation if the performance reduction condition does not occur, wherein upon selecting the first copy-back operation, data stored in a page buffer of a memory device is programmed in a target page of the memory device without accessing data stored in the buffer memory when a number of error-corrected bits per unit size of the data read from a source page to the page buffer is less than a threshold value, and upon selecting the second copy-back operation, reading error-corrected data stored in the buffer memory and programming the error-corrected data in the target page of the memory device.
  • I/O input/output
  • the inventive concept provides a storage device comprising; a non-volatile memory device comprising a page buffer that temporarily stores data read from at least one source page, a buffer memory external to the non-volatile memory device, and a memory controller that performs error correction on the data provided from the page buffer to generate error-corrected data and determine a number of error-correct bits per unit size of the data, stores the error-corrected data in the buffer memory, and then selectively performs, in view of the number of error-corrected bits per unit size of the data, one of an external copy-back operation using the error-corrected data stored in the buffer memory, and an internal copy-back operation using the data stored in the page buffer.
  • the inventive concept provides a method of operating a storage device including a non-volatile memory device having multiple non-volatile memory chips arranged in operation according to multiple channels and a volatile buffer memory, the method comprising; during a garbage collection process for the non-volatile memory device, determining whether a performance reduction condition exists by determining a number of the multiple channels accessing the buffer memory, and upon determining that the performance reduction condition exists, performing at least one copy-back operation.
  • the at least one copy-back operation will be an external copy-back operation that transfers data stored in the buffer memory to the non-volatile memory when a number of error-corrected bits per unit size for data stored in a page buffer of the non-volatile memory device exceeds a threshold value, and an internal copy-back operation that does not transfer data stored in the buffer memory to the non-volatile memory when the number of error-corrected bits per unit size for the data stored in the page buffer does not exceed the threshold value.
  • FIG. 1 is a block diagram of a memory system according to an embodiment of the inventive concept
  • FIG. 2 is a block diagram further illustrating the storage device of FIG. 1 ;
  • FIG. 3 is a conceptual diagram illustrating a number of channels and ways of the memory device illustrated in FIG. 1 ;
  • FIG. 4 is a block diagram illustrating a flash memory chip that may be used in the memory device of FIG. 1 ;
  • FIG. 5 is a block diagram further illustrating one possible arrangement for the memory cell array of the flash memory of FIG. 4 ;
  • FIG. 6 is a conceptual diagram illustrating various logical layers associated with firmware installed in the memory controller of FIG. 1 ;
  • FIG. 7 is a block diagram illustrating the bottleneck phenomenon related to accessing the buffer memory of FIG. 1 ;
  • FIG. 8 is a block diagram illustrating one possible approach to data processing during an external copy-back operation according to an embodiment of the inventive concept
  • FIG. 9 is a block diagram illustrating one possible approach to data processing during an internal copy-back operation according to an embodiment of the inventive concept.
  • FIG. 10 is a flowchart summarizing a garbage collection method according to an embodiment of the inventive concept
  • FIG. 11 is a flowchart summarizing an adaptive copy-back method according to an embodiment of the inventive concept
  • FIG. 12 is a more detailed flowchart summarizing the steps of selecting and performing the external or internal copy-back operation within the method of FIG. 11 ;
  • FIG. 13 is a more detailed flowchart summarizing the step of programming data in a target page within the method of FIG. 12 when an external copy-back operation is selected;
  • FIG. 14 is a flowchart summarizing an adaptive copy-back method according to another embodiment of the inventive concept.
  • FIG. 15 is a more detailed flowchart summarizing a copy-back method when the second copy-back operation is selected in the method of FIG. 14 ;
  • FIG. 16 is a graph illustrating variation in performance according to a number of operations allocated to channels and ways of the storage device of FIG. 1 ;
  • FIG. 17 is a block diagram of a computer system capable of incorporating a storage device according to an embodiment of the inventive concept
  • FIG. 18 is a block diagram of a memory card system capable of incorporating a storage device according to an embodiment of the inventive concept.
  • FIG. 19 is a block diagram of a network system capable of incorporating a storage device according to an embodiment of the inventive concept.
  • FIG. 1 is a general block diagram of a memory system 1000 according to an embodiment of the inventive concept.
  • the memory system 1000 comprises a host device 100 and a storage device 200 , where the storage device 200 includes a memory controller 210 , a buffer memory 220 , a memory device 230 , and a bus 240 .
  • the bus 240 is a signal transmission path (or collection of signal transmission paths) that may be used to communicate information (e.g., data, addresses, and/or control signals) between the other elements of the storage device 200 .
  • information e.g., data, addresses, and/or control signals
  • the memory device 230 is implemented using one or more non-volatile memory devices (e.g., flash memory devices) and that the storage device 200 operates as a SSD in relation to the host device 100 .
  • the memory controller 210 controls the execution of erase, write, and/or read operation by the memory device 230 in response to command(s) received from the host device 100 .
  • a plurality of channels may be formed between the memory controller 210 and the memory device 230 , wherein each channel is associated with a plurality of ways.
  • the term “way” may be understood as referring to a bank of memory devices.
  • One exemplary arrangement of channels and ways will be described hereafter with reference to FIG. 3 .
  • the memory device 230 may include one or more types of non-volatile memory other than, or additional to, the flash memory assumed in the working example.
  • the memory device 230 may include phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), etc.
  • PRAM phase change random access memory
  • FRAM ferroelectric random access memory
  • MRAM magnetic random access memory
  • the memory device 230 may include a combination of at least one non-volatile memory device and at least one volatile memory device, or may include a combination of two or more non-volatile memory devices.
  • the buffer memory 220 may be used to temporarily store data communicated between the memory controller 210 and memory device 230 , and/or data communicated between the storage device 200 and host device 100 .
  • the memory controller 210 will typically install firmware controlling data input and output (I/O) operations for the buffer memory 220 .
  • the buffer memory 220 may be physically disposed external to the memory controller 210 .
  • the buffer memory 220 may be disposed internal to the memory controller 210 .
  • the buffer memory 220 may be implemented using one or more random access memory (RAM) such as dynamic RAM (DRAM) and/or static RAM (SRAM).
  • RAM random access memory
  • DRAM dynamic RAM
  • SRAM static RAM
  • the memory controller 210 may also be used to control the overall operation of the storage device 200 . Specifically, the memory controller 210 may control write/read operations communicating data between the buffer memory 220 and memory device 230 in response to command(s) received from the host device 100 .
  • the firmware (hardware and/or software) installed within the memory controller 210 may additionally be used to control execution of a copy-back operation commonly performed as part of a garbage collection process. Examples of an adaptive copy-back method consistent with embodiments of the inventive concept will be described in relation to FIGS. 10 through 15 .
  • FIG. 2 is a block diagram further illustrating the storage device 200 and memory controller 210 of FIG. 1 .
  • the memory controller 210 includes a control unit 211 , an internal memory 212 , an error correction code (ECC) unit 213 , a host interface 214 , a memory interface 215 , and a bus 216 .
  • ECC error correction code
  • the bus 216 is a signal transmission path (or collection of signal transmission paths) that may be used to communicate information (e.g., data, addresses, and/or control signals) between the other elements of the memory controller 210 .
  • the control unit 211 may be used to control the overall operation of the memory controller 210 .
  • the control unit 211 , the internal memory 212 , and the ECC unit 213 may be implemented (i.e., fabricated) as a single chip using conventionally understood system on chip (SoC) technologies.
  • SoC system on chip
  • the control unit 211 , the internal memory 212 , the ECC unit 213 , the host interface 214 , and the memory interface 215 may be fabricated as two or more separate semiconductor devices assembled as a working system.
  • the internal memory 212 may be used to store program code and data required to control the operations performed by the storage device 200 .
  • the program code required to perform the adaptive copy-back methods illustrated in FIGS. 10 through 15 may be stored in the internal memory 212 .
  • the internal memory 212 may also be used to store metadata used to map addresses.
  • the control unit 211 may be used to control the storage device 200 to perform the adaptive copy-back method illustrated in FIGS. 10 through 15 according to the program code and data stored in the internal memory 212 .
  • the control unit 211 may also be used to schedule flash write operations so as to effectively distribute the resulting write data across a plurality of channels and ways within the memory device 230 .
  • the control unit 211 may be used to check the number of operations allocated to each channel and way.
  • the ECC unit 213 may be used to generate an ECC related to received data using conventionally understood algorithm(s) such as those used to generate Reed-Solomon (RS) code, Hamming code, cyclic redundancy code (CRC), etc. Also, during the read operation, the ECC unit 213 may be used to perform error detection and correction on received data using previously generated ECC together with the data.
  • the error correction performance for the ECC unit 213 is determined by the ECC engine being used. In certain embodiments, the unit size may be defined as a particular sector size. For example, an ECC engine capable of correcting a 12-bit error in a 512-byte sector may be included in the ECC unit 213 .
  • the ECC unit 213 may include a plurality of ECC engines corresponding to the number of channels connected to the memory device 230 . Each ECC engine may operate independently and may calculate the number of error-corrected bits in a unit size.
  • the host interface 214 operates according to one or more data communication protocol(s) designed to control the exchange of data between the host device 100 and storage device 200 .
  • the host interface 214 may be implemented as an Advanced Technology Attachment (ATA) interface, a Serial Advanced Technology Attachment (SATA) interface, a Parallel Advanced Technology Attachment (PATA) interface, a Universal Serial Bus (USB) or Serial Attached Small Computer System (SAS) interface, a Small Computer System Interface (SCSI), an embedded Multi Media Card (eMMC) interface, or a Unix File System (UFS) interface.
  • ATA Advanced Technology Attachment
  • SATA Serial Advanced Technology Attachment
  • PATA Parallel Advanced Technology Attachment
  • USB Universal Serial Bus
  • SAS Serial Attached Small Computer System
  • SCSI Small Computer System Interface
  • eMMC embedded Multi Media Card
  • UFS Unix File System
  • the host interface 214 may be used to exchange command, address, and/or data signals (and/or signal packets) between the host device 100 and the control unit 211 .
  • the memory interface 215 may be used to connected to the memory device 230 to the memory controller 210 . That is, the memory interface 215 may exchange control, address, and/or data signal(s) with the memory device 230 via a plurality of channels and ways under the control of the control unit 211 . In the working example, it is assumed that the memory interface 215 supports at least one of NAND flash memory and NOR flash memory.
  • the memory device 230 includes a plurality of flash memories connected to the memory interface 215 via the channels and ways.
  • a plurality of channels CH 0 through CH(N- 1 ) may be electrically connected to a plurality of flash memories 231 through 233 .
  • the channels CH 0 through CH(N- 1 ) may be independent buses capable of transmitting and receiving control signals, addresses, and data to and from corresponding flash memories 231 through 233 .
  • Different flash memories 231 through 233 connected to different channels CH 0 through CH(N- 1 ) may operate independently.
  • Each of the flash memories 231 through 233 may form a plurality of ways way 0 through way(M- 1 ).
  • M ways way 0 through way(M- 1 ) formed in each channel may be connected to each of M flash memories 231 through 233 .
  • the flash memory 231 may form the M ways way 0 through way(M- 1 ) in the channel CH 0 .
  • Flash memory chips 231 - 0 through 231 -(M- 1 ) respectively corresponding to the M ways way 0 through way(M- 1 ) may be connected to the channel CH 0 .
  • the above-described correlations may also be applied to each of the flash memories 232 through 233 .
  • Ways are units identifying flash memory chips having a common position along a respective channel (e.g., a “column” position in relation to a channel “row”).
  • Each flash memory chip may be identified according to a channel number and a way number.
  • a channel and a way of a flash memory chip for executing a command provided from the host device 100 may be determined based on a logical block address (LBA) transmitted from the host device 100 .
  • LBA logical block address
  • FIG. 4 is a block diagram illustrating in relevant portion a circuit structure for one flash memory chip (e.g., the flash memory chip 231 - 0 ) included in the memory device 230 of FIG. 2 .
  • one flash memory chip e.g., the flash memory chip 231 - 0
  • the flash memory chip 231 - 0 comprises a cell array 10 , a page buffer 20 , a control circuit 30 , and a row decoder 40 .
  • the cell array 10 is a region into which data is written by applying a certain voltage to a transistor.
  • the cell array 10 includes memory cells formed where a plurality of word lines WL 0 through WLm- 1 and a plurality of bit lines BL 0 through BLn- 1 cross each other.
  • m and n are natural numbers.
  • the cell array 10 may include a plurality of memory blocks. Each memory block includes pages corresponding to the word lines WL 0 through WLm- 1 . Each page includes a plurality of memory cells connected to each word line.
  • the flash memory chip 231 - 0 performs an erase operation in units of a block, and performs a program or read operation in units of a page.
  • the cell array 10 has a structure of cell strings.
  • Each cell string includes a string selection transistor SST connected to a string selection line SSL, a plurality of memory cells MC 0 through MCm- 1 respectively connected to the word lines WLO through WLm- 1 , and a ground selection transistor GST connected to a ground selection line GSL.
  • the string selection transistor SST is connected between a bit line and a string channel
  • the ground selection transistor GST is connected between the string channel and a common source line CSL.
  • the page buffer 20 is connected to the cell array 10 via the bit lines BL 0 through BLn- 1 .
  • the page buffer 20 temporarily stores data to be written into or data read from memory cells connected to a selected word line.
  • the control circuit 30 generates various voltages required to perform write or read, and erase operations, receives control signals, and controls overall operations of the flash memory chip 231 - 0 .
  • the row decoder 40 is connected to the cell array 10 via the string selection line SSL, the ground selection line GSL, and the word lines WL 0 through WLm- 1 .
  • the row decoder 40 receives an address and selects any one word line according to the received address.
  • the selected word line is connected to memory cells on which the write or read operation is to be performed.
  • the row decoder 40 applies voltages required to perform a program or read operation, e.g., a program voltage, a pass voltage, a read voltage, a string selection voltage, and a ground selection voltage, to the selected word line, unselected word lines, the string selection line SSL, and the ground selection line GSL.
  • a program voltage e.g., a program voltage, a pass voltage, a read voltage, a string selection voltage, and a ground selection voltage
  • Each memory cell may store one-bit data or two-or-more-bit data.
  • a memory cell for storing one-bit data is referred to as a single level cell (SLC).
  • a memory cell for storing two-or-more-bit data is referred to as a multi level cell (MLC).
  • An SLC has an erase or program state according to a threshold voltage.
  • a physical page of flash memory includes a spare region and ECC information is stored in the spare region.
  • one possible internal structure for the flash memory chip 231 - 0 may include a plurality of blocks, wherein each block includes a plurality of pages.
  • the flash memory chip 231 - 0 writes and reads data in page units, but electrically erases data in block units. Given the well-known characteristics of flash memory a block erase operation may be required before each write operation, as a direct overwrite capability is not provided.
  • the absence of a direct overwrite capability may not allow user defined write data from being written to a user-desired (host indicated) physical region of the SSD. Accordingly, if access to a region for writing or reading user data is requested by a user, address translation between a logical address for the region and a corresponding physical address to a physical region in which the user data is or is to be stored is required.
  • FIG. 6 is a conceptual diagram illustrating a logical layer hierarchy for firmware installed in the memory controller 210 of FIG. 2 .
  • a host interface layer (HIL) 101 functions to control an interface operation between the host device 100 and the host interface 214 .
  • Software or firmware for performing the function of the HIL 101 may be installed in the host interface 214 or may be stored in the internal memory 212 so as to be used to control operation of the host interface 214 .
  • a data cache layer (DCL) 102 functions to control a read or write operation of the internal memory 212 or the buffer memory 220 .
  • Software or firmware for performing the function of the DCL 102 may be installed in the control unit 211 or may be stored in the internal memory 212 so as to be used by the control unit 211 to control the read or write operation of the internal memory 212 or the buffer memory 220 .
  • a flash translation layer (FTL) 103 functions to translate a logical address provided from the host device 100 into a physical address for performing a read or write operation on the memory device 230 .
  • Software or firmware for performing the function of the FTL 103 may be installed in the control unit 211 or may be stored in the internal memory 212 .
  • the FTL 103 translates a logical address into a physical address by using mapping information included in metadata.
  • As an address mapping method a page or block mapping method may be used.
  • the page mapping method is a method of performing address mapping in units of a page
  • the block mapping method is a method of performing address mapping in units of a block.
  • a combined mapping method of the page and block mapping methods may be used.
  • a physical address indicates a location for storing data in the memory device 230 .
  • a flash interface layer (FIL) 104 functions to control an interface operation between the memory interface 215 and flash memories included in the memory device 230 .
  • Software or firmware for performing the function of the FIL 104 may be installed in the memory interface 215 or may be stored in the internal memory 212 .
  • Data input requests and/or data output requests (hereafter, collectively and singularly referred to as “I/O accesses”) to the buffer memory 220 may simultaneously occur via a number of the plurality of channels as part of ongoing garbage collection processes and/or as the result of I/O accesses resulting from command(s) received from the host device 100 .
  • I/O accesses to the buffer memory 220 may simultaneously occur via a plurality of channels. That is, the “collision” of I/O accesses by (e.g.,) a first channel 231 and a third channel 233 at the buffer memory 220 may markedly reduce the performance of the memory system 1000 when the combined effects of the multiple I/O accesses exceed the bandwidth capabilities of the buffer memory 220 .
  • FIG. 8 is a block diagram further illustrating data processing during an external copy-back operation according to an embodiment of the inventive concept.
  • FIG. 8 shows data processing in an external copy-back operation performed by one of a plurality of flash memory chips, e.g., the flash memory chip 231 - 0 , included in the memory device 230 illustrated in FIG. 2 .
  • the same external copy-back operation may also be performed by the other flash memory chips.
  • the memory controller 210 controls the storage device 200 to perform an external copy-back operation in the following order.
  • data is read from a source page of the flash memory chip 231 - 0 corresponding to a channel and a way, and is stored in a page buffer of the flash memory chip 231 - 0 (S 11 ).
  • the memory controller 210 receives the data from the page buffer of the flash memory chip 231 - 0 , error-corrects the received data using an ECC engine included in the ECC unit 213 , and stores the error-corrected data in the buffer memory 220 (S 12 ).
  • the memory controller 210 receives the data from the buffer memory 220 , adds ECC to the received data using the ECC engine, and stores the data in the page buffer of the flash memory chip 231 - 0 (S 13 ). Then, the data stored in the page buffer is programmed in a target page of a storage region of the flash memory chip 231 - 0 (S 14 ).
  • FIG. 9 is a block diagram illustrating data processing during an internal copy-back operation according to an embodiment of the inventive concept.
  • FIG. 9 shows data processing during an internal copy-back operation performed by one of a plurality of flash memory chips, e.g., the flash memory chip 231 - 0 , included in the memory device 230 illustrated in FIG. 2 .
  • the same internal copy-back operation may also be performed by the other flash memory chips.
  • the memory controller 210 controls the storage device 200 to perform an internal copy-back operation in the following order.
  • data is read from a source page of the flash memory chip 231 - 0 corresponding to a channel and a way, and is stored in a page buffer of the flash memory chip 231 - 0 (S 21 ).
  • the memory controller 210 receives the data from the page buffer of the flash memory chip 231 - 0 , error-corrects the received data by using an ECC engine included in the ECC unit 213 , and stores the error-corrected data in the buffer memory 220 (S 22 ).
  • the memory controller 210 controls the storage device 200 to program the data stored in the page buffer of the flash memory chip 231 - 0 in a target page of a storage region of the flash memory chip 231 - 0 without accessing the buffer memory 220 (S 23 ).
  • the bandwidth demands placed upon the buffer memory 220 are reduced in comparison with the external copy-back operation described above.
  • the memory controller 210 may control the storage device 200 to selectively perform either the external copy-back operation or the internal copy-back operation during garbage collection processes.
  • This type of “adaptive” copy-back operation for the storage device 200 by the control of the memory controller 210 will now be described with reference to FIGS. 10 through 15 .
  • a “free block” is a block within the flash memory chip that is available to store data.
  • a victim block may be a block currently storing data according to certain conditions, such as a block in which all pages are used up and not available to store data.
  • a selected victim block may be a memory block having a lowest “garbage collection cost”. Garbage collection cost falls for a particular block as the number of invalid pages in the block increases.
  • the memory controller 210 performs an adaptive copy-back method so as to control the storage device 200 to copy the data stored in valid page(s) of the victim block to an empty page of an active block (S 130 ).
  • an “active block” is a block in which data is stored, and indicates a block having empty page available for storing data. If an active block does not exist, the memory controller 210 controls the storage device 200 to copy the data stored in valid page(s) of the victim block to a free block.
  • FIG. 11 is a flowchart further describing an adaptive copy-back method according to an embodiment of the inventive concept.
  • the memory controller 210 controls the storage device 200 to read data from a source page of the memory device 230 and store the data in a page buffer (S 210 ).
  • the source page indicates a valid page included in a data block selected as a victim block. For example, referring to FIG. 8 , data read from a source page included in a storage region of the flash memory chip 231 - 0 is stored in a page buffer of the flash memory chip 231 - 0 .
  • the memory controller 210 then receives the data from the page buffer, performs error correction on the received data by using an ECC engine included in the ECC unit 213 , and calculates a number of error-corrected bits in relation to a given unit size (S 220 ).
  • the memory controller 210 then controls the storage device 200 to store the error-corrected data in the buffer memory 220 (S 230 ).
  • the memory controller 210 controls the storage device 200 to selectively perform an external or internal copy-back operation based on the number of error-corrected bits in a unit size (S 240 ). This particular operation (S 240 ) will be described in some additional detail with reference to FIG. 12 .
  • FIG. 12 is a flowchart further describing the step of selectively performing either an external copy-back operation or an internal copy-back operation based on the number of error-corrected bits in a unit size within the method of FIG. 11 .
  • the memory controller 210 determines whether the number “Ni” of error-corrected bits in a unit size exceeds a given threshold value “TH” (S 310 ).
  • the threshold value TH may be set to be less than a maximum number of error-correctable bits for the operative ECC engine given the unit size of data. For example, if the memory controller 210 includes an ECC engine capable of correcting up to 12 errant bits in a sector (unit size) of 512 bytes, then the threshold value TH may be set to 6. Alternatively, the threshold value TH may be set to some other value less than 12.
  • the data stored in a page buffer of the memory device 230 may include some error bits, the data may nonetheless be moved to a target page without necessarily performing error correction and then may be read from the target page to determine the threshold value TH within an error-correctable range. If one page includes a plurality of unit sizes, whether the number Ni of error-corrected bits exceeds the threshold value TH may be determined in relation to each unit size.
  • the memory controller 210 selects an external copy-back operation (S 320 ). For example, when one page includes a plurality of unit sizes, if the number Ni of error-corrected bits in any one of the unit sizes exceeds the threshold value TH, the external copy-back operation is selected.
  • the memory controller 210 selects an internal copy-back operation (S 330 ).
  • the memory controller 210 programs data in a target page of the memory device 230 according to the selected copy-back operation (S 340 ). For example, if the external copy-back operation is selected, the memory controller 210 reads data from the buffer memory 220 , adds an ECC to the read data, and programs the data in the target page of the memory device 230 . However, if the internal copy-back operation is selected, the memory controller 210 programs data stored in a page buffer of the memory device 230 , in the target page of the memory device 230 without accessing the buffer memory 220 .
  • FIG. 13 is a somewhat more detailed flowchart further describing the step of programming data in the target page when an external copy-back operation is selected according to the method of FIG. 12 .
  • the memory controller 210 reads data from the buffer memory 220 and outputs the data to the ECC unit 213 (S 410 ), and the ECC unit 213 adds an ECC to the data read from the buffer memory 220 (S 420 ).
  • the memory controller 210 controls the storage device 200 to transmit the ECC-added data to the memory device 230 and to store the data in a page buffer of the memory device 230 (S 430 ). Then, the memory controller 210 controls the storage device 200 to program the data stored in the page buffer, in a target page of the memory device 230 (S 440 ).
  • FIG. 14 is a flowchart of an adaptive copy-back method according to another embodiment of the inventive concept.
  • the adaptive copy-back method illustrated in FIG. 14 may be performed by the storage device 200 under the control of the memory controller 210 .
  • the memory controller 210 determines whether a given performance reduction condition occurs due to an access bottleneck for the buffer memory 220 of the storage device 200 (S 510 ).
  • the performance reduction condition may be determined based on the number of operations allocated to channels and ways of the storage device 200 .
  • the performance reduction condition may be set within a range of the number of operations allocated to channels and ways when a variation in a value of input/output operations per second (IOPS) according to a variation in the number of operations allocated to the channels and ways exceeds a reference value.
  • IOPS input/output operations per second
  • the value of IOPS represents the number of I/O accesses to the memory device 230 according to I/O commands per second.
  • FIG. 16 is a graph showing variations in performance according to the number of operations allocated to channels and ways of the storage device 200 illustrated in FIG. 1 .
  • the horizontal axis indicates a number of channels for selecting and performing an external copy-back operation when a copy-back operation is simultaneously performed in all channels. As indicated, a case when the number of channels is 0 means that an internal copy-back operation is simultaneously selected in all channels, and a case when the number of channels is 16 means that an external copy-back operation is simultaneously selected in all sixteen channels.
  • the vertical axis represents a value of thousands (“kilo”) of input/output operations per second (KIOPS) in the storage device 200 .
  • C 1 represents a case when a copy-back operation is performed in one way
  • C 2 represents a case when a copy-back operation is simultaneously performed in two ways
  • C 3 a case when a copy-back operation is simultaneously performed in three ways
  • C 4 a case when a copy-back operation is simultaneously performed in four ways.
  • a performance reduction condition may be set within a range of the number of operations allocated to channels and ways when a variation in a value of IOPS exceeds a target reference value based on the number of operations allocated to ways rather than channels.
  • the memory controller 210 selects a first copy-back operation during a garbage collection process (S 520 ).
  • the memory controller 210 selects a second copy-back operation during the garbage collection process (S 530 ).
  • the memory controller 210 controls the storage device 200 to perform the selected copy-back operation (S 540 ). If the first copy-back operation is selected, the memory controller 210 controls the storage device 200 to perform a copy-back operation according to the copy-back method illustrated in FIG. 11 . Otherwise, if the second copy-back operation is selected, the memory controller 210 controls the storage device 200 to perform a copy-back operation according to a copy-back method illustrated in FIG. 15 .
  • FIG. 15 is a somewhat more detailed flowchart describing a copy-back operation when the second copy-back operation is selected by the method of FIG. 14 .
  • the copy-back approach illustrated in FIG. 15 may be performed in the storage device 200 by the control of the memory controller 210 .
  • the memory controller 210 controls the storage device 200 to read data from a source page of the memory device 230 and to store the page in a page buffer (S 610 ).
  • a source page indicates a valid page included in a data block selected as a victim block. For example, referring to FIG. 8 , data read from a source page included in a storage region of the flash memory chip 231 - 0 is stored in a page buffer of the flash memory chip 231 - 0 .
  • the memory controller 210 receives the data from the page buffer and performs error correction on the received data by using an ECC engine included in the ECC unit 213 (S 620 ).
  • the memory controller 210 controls the storage device 200 to store the error-corrected data in the buffer memory 220 (S 630 ).
  • the memory controller 210 reads the data from the buffer memory 220 and adds an ECC to the read data (S 640 ).
  • the memory controller 210 controls the storage device 200 to transmit the ECC-added data to the memory device 230 and to program the transmitted data in a target page of the memory device 230 (S 650 ).
  • FIG. 17 is a block diagram of a computer system 2000 capable of incorporating a storage device consistent with an embodiment of the inventive concept.
  • the computer system 2000 includes a central processing unit (CPU) 2200 , a RAM 2300 , a user interface (UI) 2400 , and a storage device 2100 electrically connected via a bus 2600 .
  • the storage device 2100 includes a memory controller 2110 and a memory device 2120 .
  • the memory device 2120 may store via the memory controller 2110 data processed or to be processed by the CPU 2200 .
  • the storage device 2100 may be implemented as the storage device 200 illustrated in FIG. 1 .
  • the CPU 2200 may be implemented as the processor 210 - 1 of the host device 210 illustrated in FIG. 2 .
  • the computer system 2000 may further include a power supply 2500 .
  • the power supply 2500 of the computer system 2000 may be a battery and the computer system 2000 may additionally include a modem such as a baseband chipset. Also, it is well known to one of ordinary skill in the art that the computer system 2000 may further include, for example, an application chipset, a camera image processor (CIS), and a mobile DRAM and thus a detailed description thereof will not be provided here.
  • a modem such as a baseband chipset.
  • the computer system 2000 may further include, for example, an application chipset, a camera image processor (CIS), and a mobile DRAM and thus a detailed description thereof will not be provided here.
  • FIG. 18 is a block diagram of a memory card 3000 capable of incorporating a storage device according to an embodiment of the inventive concept.
  • the memory card 3000 includes a memory controller 3020 and a memory device 3010 .
  • the memory controller 3020 controls a write or read operation of data into or from the memory device 3010 in response to a request of an external host received via an I/O means 3030 .
  • the memory controller 3020 of the memory card 3000 may include, for example, an interface for interfacing between the host and the memory device 3010 , and RAM.
  • the memory card 3000 may be implemented as the storage device 200 illustrated in FIG. 1 .
  • the memory card 3000 may be implemented as a compact flash card (CFC), a micro drive, a smart media card (SMC), a multimedia card (MMC), a security digital card (SDC), a memory stick, or a USB flash memory driver.
  • CFC compact flash card
  • SMC smart media card
  • MMC multimedia card
  • SDC security digital card
  • memory stick or a USB flash memory driver.
  • FIG. 19 is a block diagram of a network system 4000 and a server system 4100 including an SSD 4110 according to an embodiment of the inventive concept.
  • the network system 4000 may include the server system 4100 and a plurality of terminals 4200 _ 1 through 4200 — n connected in a network.
  • the server system 4100 may include a server 4120 for processing requests received from the terminals 4200 _ 1 through 4200 — n connected in the network, and the SSD 4110 for storing data corresponding to the requests received from the terminals 4200 _ 1 through 4200 — n .
  • the SSD 4110 may be implemented as the storage device 200 illustrated in FIG. 1 .
  • the memory system 1000 illustrated in FIG. 1 may be mounted by using various types of packages, e.g., a package on package (POP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flat pack (TQFP), a small-outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi chip package (MCP), a wafer-level fabricated package (WFP), and a wafer-level processed stack package (WSP).
  • POP package on package
  • BGA ball grid array
  • CSP chip scale package
  • PLCC plastic leaded chip carrier
  • PDIP plastic dual in-

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