US8994123B2 - Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET) - Google Patents

Variation resistant metal-oxide-semiconductor field effect transistor (MOSFET) Download PDF

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US8994123B2
US8994123B2 US13/424,727 US201213424727A US8994123B2 US 8994123 B2 US8994123 B2 US 8994123B2 US 201213424727 A US201213424727 A US 201213424727A US 8994123 B2 US8994123 B2 US 8994123B2
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epitaxial layer
mosfet
layer
doping
source
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US20130049140A1 (en
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Asen Asenov
Gareth Roy
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Semiwise Ltd
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Gold Standard Simulations Ltd
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Definitions

  • the present invention generally relates to the manufacturing of metal-oxide-semiconductor field effect transistors (MOSFETs), and more particularly to MOSFETs manufactured for reproducibility of threshold voltages among otherwise identical transistors.
  • MOSFETs metal-oxide-semiconductor field effect transistors
  • Random variation in threshold voltage ( ⁇ V T ) of metal-oxide semiconductor (MOS) field effect transistors (MOSFETs) with high-K (high dielectric constant) metal gate stack is caused by some dominant factors: (i) random dopant fluctuations (RDF) in the well and in the pocket implant regions underneath the gate, which, among other things, cause variations in depletion layer thickness; (ii) line edge roughness (LER) which causes random variation in the length of the gate electrode resulting from random variations in profile of the etched gate; and, (iii) metal gate granularity (MGG) which causes random variations in the local work function due to the grain structure of the gate material.
  • RDF random dopant fluctuations
  • LER line edge roughness
  • MMGG metal gate granularity
  • RXF random extension fluctuations
  • FIG. 4 A cross-section 400 of a standard bulk MOSFET, formed in a gate-last process, is shown in FIG. 4 .
  • drain and source areas 420 of an opposite conductivity type are formed on bulk 410 of one conductivity type.
  • a SiO 2 isolation layer 430 is formed over the entire MOSFET transistor, with openings for connections 470 to respective drain and source terminals.
  • the gate is formed by having spacers 440 formed above the SiO 2 layer.
  • the SiO 2 is removed and typically replaced by a high-K dielectric stack 450 on top of which a metal gate 460 is formed.
  • the spacers are formed by repeating the deposition-and-etch process.
  • This scheme has three key components: a) placing a thin, approximately 10 nanometer (nm), minimally doped epitaxial layer immediately beneath the gate oxide; b) placing a thinner layer with a very high concentration of either acceptors for an NMOS device or donors for a PMOS device at the boundary of the thin epitaxial layer that is remote from the gate dielectric interface; and, c) incorporating a moderately heavily doped well layer beneath the un-doped epitaxial layer and the highly doped, thinner layer. Similar structures have been demonstrated by Fujita et al. as described in their paper “Advanced Channel Engineering Achieving Aggressive Reduction of V T Variation for Ultra-Low-Power Applications”, Electron Devices Meeting (IEDM), 2011 IEEE International, pp.
  • FIG. 5 A cross-section 500 of such an epitaxial transistor is shown in FIG. 5 .
  • the epitaxial layer 510 is deposited on the whole silicon wafer after the channel doping implantation through a sacrificial gate oxide and before the formation of the sacrificial polysilicon gate and the source drain regions 525 .
  • Hokazono, A., et al. in “25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)”, Electron Devices, IEEE Transactions on Electron Devices, vol. 58, no. 5, pp.
  • the delta doping layer in these simulations, is mostly depleted, and that layer provides the tool for adjusting the nominal value of the threshold voltage.
  • high temperature processing would substantially alter the doping profiles, compromising the expected benefits. This problem persists even though it is well known that certain complementary dopants, like carbon, can retard motion during thermal treatments, at least in n-channel devices.
  • a sequence of steps is employed: a) deposition of a high-K gate dielectric, typically by atomic layer deposition; b) deposition of a metal gate having a controlled work function to set the threshold voltage; and, c) deposition of a robust gate material, typically doped amorphous silicon.
  • a sequence above is augmented by chemical-mechanical polishing steps to assure the localization of the various layers.
  • this structure does not overcome the deficiencies resulting from RDF, LER or RXF.
  • the morphology of the metal in the gate last process does reduce the variations identified as MGG, compared to a gate first process.
  • FIG. 1 is a schematic cross-section of a MOSFET manufactured in accordance with the principles of the invention.
  • FIG. 2A is a schematic cross-section showing a substrate with shallow trench isolation and a properly implanted core well according to an embodiment of the invention.
  • FIG. 2B is a schematic cross-section showing a poly gate and drain/source implants according to an embodiment of the invention.
  • FIG. 2C is a schematic cross-section showing poly gate spacers, drain/source extension regions and heavy drain/source implants according to an embodiment of the invention.
  • FIG. 2D is a schematic cross-section showing poly gate and drain/source silicidation according to an embodiment of the invention.
  • FIG. 2E is a schematic cross-section showing deposition of a first interlayer dielectric according to an embodiment of the invention.
  • FIG. 2F is a schematic cross-section showing exposed poly gate after chemical/mechanical polish (CMP) according to an embodiment of the invention.
  • FIG. 2G is a schematic cross-section showing a cavity formed by sacrificing the poly gate according to an embodiment of the invention.
  • FIG. 2H is a schematic cross-section showing a recess formed into the well from within the cavity according to an embodiment of the invention.
  • FIG. 2I is a schematic cross-section showing a first layer and a second layer formed within the recess according to an embodiment of the invention.
  • FIG. 2J is a schematic cross-section showing a high-K dielectric layer, a metal gate layer and an optional polysilicon cap formed within the cavity according to an embodiment of the invention.
  • FIG. 2K is a schematic cross-section showing a MOSFET transistor having a gate formed according to an embodiment of the invention.
  • FIG. 3A is a diagram showing a conventional doping profile for short channel transistors.
  • FIG. 3B is a diagram showing a doping profile realized in a channel-last process scheme according to an embodiment of the invention.
  • FIG. 3C is a diagram showing a delta doping profile for use in a channel-last process scheme according to an embodiment of the invention.
  • FIG. 3D is a diagram showing a multiplicity of delta doping profiles for use in a channel-last process scheme according to an embodiment of the invention.
  • FIG. 3E is a diagram showing a slab doping profile, which might be realized either by low temperature, doped epitaxy or by atomic layer deposition of a thick doped layer, for use in a channel-last process scheme according to an embodiment of the invention.
  • FIG. 4 is a schematic cross-section of a standard bulk MOSFET (prior art).
  • FIG. 5 is a schematic cross-section of an epitaxial channel MOSFET (prior art).
  • FIG. 6 is a schematic cross-section of a channel-last MOSFET according to an embodiment of the invention.
  • FIG. 7 is a schematic cross-section of a channel-last MOSFET further comprising a delta layer according to an embodiment of the invention.
  • MOSFETs Metal-oxide-semiconductor field effect transistors
  • MOSFETs are manufactured using a high-K, metal, ‘channel-last’ process. Between spacers formed over a well area having separate drain and source areas, a cavity and then a recess into the well area are formed. The active region is formed on top of an optional thin highly doped layer over which an un-doped or lightly doped epitaxial layer is formed.
  • the high doping beneath the low doped epitaxial layer can be achieved utilizing low-temperature epitaxial growth (not to exceed 750° C. but preferably not exceeding 650° C.) with single or multiple delta doping, or slab doping.
  • This epitaxial growth may be effected using conventional low-temperature epitaxy, molecular beam epitaxy or atomic layer deposition.
  • a high-K dielectric stack is formed over the upper or epitaxial layer over which a metal gate is formed within the cavity boundaries.
  • a cap of poly-silicon or amorphous silicon is added on top of the metal gate.
  • incorporation into the manufacturing process a step of a very lightly doped, low temperature (such as 750° C. or lower, preferably not exceeding 650° C.) epitaxial layer within a cavity formed for the purpose of creation of a channel of a MOSFET that results in a “channel-last” process, reduces the diffusion of dopants from the heavily doped region beneath the low-doped epitaxial layer (or from the well if such a heavily doped region is not used) into the low-doped epitaxial layer.
  • the low-doped epitaxial layer reduces the variations in the MOSFETs' threshold voltage arising from random doping fluctuations (RDF).
  • the epitaxial growth retains the strain introduced or memorized in the transistor structure in order to enhance device performance.
  • the etching through the opening of the sacrificial poly-silicon gate reduces the random channel length fluctuations that arise from variations in the lateral position of the edge of the drain and source extension implants, i.e., random extension fluctuations (RXF).
  • RXF random extension fluctuations
  • the addition of the optional layer of increased doping beneath the low doped epitaxial layer reduces the short channel effects and the threshold voltage fluctuations related to line edge roughness (LER). It also offers a method of adjusting the threshold voltage to a desired value.
  • LER line edge roughness
  • FIG. 1 depicts an exemplary and non-limiting schematic cross-section of a MOSFET 100 manufactured in accordance with the principles of the invention.
  • a well 120 is manufactured in a substrate 110 , for example a silicon wafer, the well made of silicon or silicon-germanium, and typically doped to 10 18 to 10 19 ions per cm 3 .
  • the well may be a P-well or an N-well depending on the desired transistor type, N-channel or P-channel respectively.
  • a silicon-oxide (SiO 2 ) or nitrided silicon dioxide layer 185 provides isolation in surface areas as required for proper operation of the MOSFET 100 .
  • source and drain areas that are a combination of a low-doping area 130 and a high-doping area 132 , each such source and drain area being separated from the other by a sacrificial polysilicon gate 195 , though with some diffusion to extend each region slightly under the sacrificial polysilicon gate 195 .
  • Each highly doped area 132 has a silicide area 135 , used to electrically connect to the source and drain of the formed MOSFET and to reduce the access resistance.
  • Spacers 150 formed in a conventional manner over the low-doped source or drain area 130 , are used to define the gate region of the MOSFET, in a process that resembles a conventional MOS or ‘gate-last’ process and as described herein below in greater detail. In certain embodiments, spacers may be formed in two steps, as is known to those skilled in the art. A shallow trench 115 separates adjacent transistors.
  • the active channel is comprised of an optional first highly doped layer 160 such as a highly doped epitaxial ⁇ -layer, and a channel epitaxial layer 170 that is either un-doped or lightly doped.
  • the undoped or lightly doped epitaxial layer has a doping density typically in the range of zero to 10 17 ions/cm 3 .
  • the first layer is typically doped in the range of 10 12 to 10 14 ions/cm 2 .
  • An area density is used in this case due to the fact that this first layer 160 is very thin, and at the extreme, a monolayer.
  • the thickness of the first layer 160 is typically between 0.3 nm and 15 nm while the epitaxial layer 170 has a thickness of 1 nm to 25 nm.
  • a high-K dielectric stack 180 is formed having a typical effective oxide thickness ranging between 0.5 nm and 3 nm.
  • a metal gate 190 is formed having a typical thickness of 40 to 200 nm.
  • a polysilicon cap 195 is added as a layer on top of the metal gate 190 .
  • a dielectric layer 140 is further used as part of this structure. It should be therefore understood that the invention covers, without limitation, both a full MOSFET structure 100 as described hereinabove as well as a channel region of a MOSFET that is comprised of the layers 160 (optional), 170 , 180 and 190 and optionally layer 195 .
  • FIGS. 2A through 2K demonstrate schematically the exemplary and non-limiting processing steps taken in order to achieve the ‘channel-last’ MOSFET with a channel comprising the two layers of different materials, one or both of which may be epitaxial layers. In the typical, but probably not the only case, these materials are both silicon, differing only in their doping densities.
  • FIG. 2A shows a cross-section 200 A where a substrate 110 is prepared by creating shallow trench isolation 115 and implanting an appropriate well 120 for a desired transistor.
  • a SiO 2 or a nitrided SiO 2 layer 185 is formed over the entire surface, or in other embodiments on portions thereof, for at least electrical isolation purposes.
  • Such a layer 185 could be of a typical thickness of 3.5 nm that may range between 2 nm and 8 nm, but not limited thereto.
  • FIG. 2B cross-section 200 B, the formation of a sacrificial poly gate 195 is shown, using appropriate manufacturing masks, for example by deposition and directional etching. Drain and source extension areas 130 are also formed by implantation through the SiO 2 layer 185 , as well as any other pocket implants (not shown) if and when necessary and/or applicable.
  • the cross-section 200 C shows the spacers 150 that are created by deposition of nitride or a combination of nitride and oxide. Then anisotropic etching with vertical or tapered impact takes place. This selectively erodes the deposited sidewall material so the regions paralleling the wafer surface are removed, but vertical or tapered sections remain.
  • the spacer is formed by repeating the deposition-and-etch process. After first deposition-and-etch step, the shallow drain/source extensions are formed by ion implantation, plasma immersion doping or a suitable process. Then, another deposition and etch step is carried out to space the drain/source from the channel.
  • the heavily doped source and drain areas 132 can be implanted, typically using the spacers 150 as masks.
  • additional silicon or silicon/germanium may be deposited to elevate the top of the source and drain regions above the original silicon surface and to insert compressive strain in the p-channel MOSFET.
  • Silicon/Germanium (Si:Ge) or Silicon/Carbon (Si:C) stressors in some cases with a ⁇ shape, can also be embedded by partial etching of the source and drain regions and epitaxial regrowth of the stressors.
  • the cross-section 200 D shows the clearing of certain areas of the SiO 2 layer 185 to expose for example the drain and source areas 132 .
  • FIG. 2E shows a cross-section 200 E where a first interlayer dielectric 140 is deposited where in FIG. 2F the cross-section 200 F shows the result after chemical/mechanical polishing (CMP) of the first interlayer dielectric 140 up to the silicidation layer 135 of the poly gate 195 .
  • CMP chemical/mechanical polishing
  • silicide layer 135 on the poly gate 195 may or may not be lost by this step.
  • all values and ranges provided herein are exemplary only, and should not be considered as limiting the scope of the invention.
  • the gates that are to be manufactured using a ‘channel-last’ process are formed. This is achieved by first coating the area with a protective photoresist 810 , and patterning the photoresist as shown in cross-section 200 G of FIG. 2G . After patterning, the photoresist protects other devices that are not to be etched. Next, a self-aligned etching process is selected for its selectivity for the sacrificial gate material and its propensity not to etch the spacers 150 and other oxides in any significant manner ( FIG. 2G ). Then, a cavity 820 is formed in the area confined between the spacers 150 and which is not protected by the protective photoresist layer 810 . Any remaining poly gate 195 is etched off as well as the SiO 2 layer 185 that is within the cavity 820 .
  • FIG. 2H shows a cross-section 200 H depicting a processing step where, while maintaining the protective photoresist layer 810 a recess 910 is formed from within the cavity 820 into the well 120 .
  • a self-aligned, selective etch process (preferably a directional etch) may be used to create a 5 to 25 nm recess into the silicon.
  • an optional delta epitaxial layer 160 is grown in the recess 910 over which a lightly doped or un-doped epitaxial layer 170 is grown.
  • the epitaxial layer 160 may be referred to as a buried epitaxial layer and the epitaxial layer 170 may be referred to as the channel epitaxial layer.
  • the buried epitaxial layer and the channel epitaxial layer will be of the same conductivity type as the well.
  • the channel epitaxial layer 170 may be formed of silicon, but in certain instances it may be advantageous to grow the low-doped layer using some combination of silicon and germanium, or an alternate semiconducting material that is compatible with the underlying substrate.
  • the thickness of the epitaxial layer 170 is controlled such that the top surface of layer 170 is preferably, but not exclusively, in line with the silicon surface under the layer 185 , although the surface of layer 170 may be slightly recessed with respect to the lower level of spacer 185 . As shown in FIG. 2I , the lower surface of layer 185 coincides with the upper level of layer 170 .
  • the doping density of the delta layer 160 is chosen in combination with the un-doped epitaxial layer 170 thickness, the high-K gate stack thickness and the metal gate work function subsequently created to define the final, desired threshold voltage. These operations may be performed using atomic layer deposition or low temperature epitaxy, molecular beam epitaxy, or other suitable process.
  • the variation in threshold voltage ⁇ VT, for a transistor manufactured at a 35 nm or finer process that would otherwise be in the range of 50-100 mV, is reduced to the range of 20-40 mV when the invention is implemented for the same dimension process.
  • a basically standard bulk MOS manufacturing process may be employed with the invention disclosed herein and without the need to resort to complex solutions suggested by prior art technologies.
  • recess 910 sacrifices any source extension ions or drain extension ions that may have diffused into the channel region.
  • the positions of those ions reflect variations that arise from scattering events during ion implantation and/or from high temperature activation processes (900° C. or higher).
  • the formation of recess 910 eliminates those variations.
  • the use of any one of several low-temperature processes to reconstitute the channel minimizes the movement of the source extension and drain extension ions, substantially eliminating their contribution to RXF.
  • the etching of the overlap portion of the extensions improves the electrostatic integrity, improves the on current and reduces the overlap capacitances.
  • low temperature, e.g., 300-750° C., epitaxy processes are used to form both layers 160 and 170 ( FIG. 2I ). While it is essential that the charge associated with the depletion of layer 160 is essentially planar, there are several alternative doping strategies and corresponding doping profiles that can support this requirement. These profiles are representatively shown in FIGS. 3B through 3E .
  • FIG. 3A shows a channel doping profile that is representative of normal transistor construction. In standard processes, there are multiple implants forming the wells and channel regions of the transistors. The FIG. 3A profile is representative of the middle of the channel, with the combined effect of well implants, threshold voltage implants and pocket implants. The total well depth is typically 200 nm to 400 nm, but the FIG. 3 all show the 75 nm lying closest to the gate. In conventional CMOS technologies this region is normally highly doped with a shallow “threshold voltage” implant and pocket implants.
  • FIG. 3B shows the well profile of a simple ‘channel last’ structure, in which the highly doped region nearest to the gate has been etched away and replaced with a very low-doped, perhaps undoped epitaxial layer.
  • layer 160 has an extremely high doping density, e.g., 10 19 to 10 21 ions/cm 3 , which makes the formation of layer 160 especially critical.
  • the first instance, illustrated by FIG. 3C shows a single “delta” doped layer, which approximates a monolayer of semiconductor with 10 12 to 10 13 doping ions/cm 2 , which is equivalent to 10 20 or 10 21 doping ions per cm 3 .
  • Such a layer might be formed by low temperature epitaxy with in situ doping or by atomic layer deposition.
  • FIG. 3C depicts a diagram of a delta doping profile as described by Asenov et al. in the paper “Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1- ⁇ m MOSFETs with Epitaxial and ⁇ -Doped Channels,” IEEE Transactions on Electron Devices, Vol. 46, No. 8, August 1999, Pages 1718-1724, however used according to the invention in the context of a channel-last process.
  • FIG. 3C depicts a diagram of a delta doping profile as described by Asenov et al. in the paper “Suppression of Random Dopant-Induced Threshold Voltage Fluctuations in Sub-0.1- ⁇ m MOSFETs with Epitaxial and ⁇ -Doped Channels,” IEEE Transactions on Electron Devices, Vol. 46, No. 8, August 1999, Pages 1718-1724, however used according to the invention in the context of a channel-last process.
  • FIG. 3D shows multiple “delta” doping layers, which might be required if the deposition process precludes full activation of enough doping ions in a single monolayer. In this case all the delta layers would be ionized, in order to set the proper threshold voltage.
  • FIG. 3E shows an alternative in which layer 160 is very highly doped, but more or less uniformly through its thickness, which might be several nanometers. Again, this layer might be formed by low temperature epitaxy or atomic layer deposition. Except for the simple channel-last example in FIG. 3B , all these cases require very high peak doping densities, in the order of 10 19 to 10 21 or more active doping ions per cm 3 in layer 160 .
  • FIGS. 3B through 3E differ in their sensitivity to substrate bias.
  • the least sensitive structure is the pure “delta” doping as shown in FIG. 3C
  • the most sensitive is the “slab” doping as illustrated in FIG. 3E .
  • the other cases are intermediate.
  • a high-K dielectric stack 180 is formed in the cavity 820 over the channel epitaxial layer 170 .
  • This stack may be expected to have an effective dielectric constant K in excess of 6.
  • the high-K dielectric stack 180 consists of a thin layer of SiO 2 , typically 1 nm or less, capped by a layer of high-K dielectric, usually incorporating an oxide or oxynitride of hafnium.
  • All layers after the highly doped layer 160 are formed using a low-temperature (not exceeding 900° C., preferably not exceeding 750° C., and more preferably, not exceeding 650° C.) deposition methods. If the present invention is used in an integrated circuit also containing transistors formed by other fabrication techniques, all layers after the highly doped layer 160 , if used, should be formed after all high temperature operations for the entire integrated circuit have been performed so that the such layers are not heated to over 900° C., and more preferably 750° C. or 650° C. Thereafter the desired gate metal is deposited forming layer 190 , where the gate metal is chosen primarily for its work function as well as for manufacturing considerations.
  • FIG. 2K shows cross-section 200 K that depicts the structure after the removal of the excess high-K dielectric layer 180 , metal layer 190 and poly layer 195 , using for example CMP.
  • processing may continue by, for example, adding a second dielectric layer (not shown) and thereafter continuing with additional processing steps including, but not limited to, forming metallization connectivity layers.
  • N and P type MOS transistors different types of metal gates are needed to incorporate work functions appropriate for the desired NMOS and PMOS threshold voltages.
  • FIG. 6 shows a schematic cross-section 600 of a channel-last MOSFET according to an embodiment of the invention. Accordingly, the channel region between the source and drain areas 420 is removed by selective etching between the spacers 440 forming a cavity penetrating into the well area 410 , and as further explained hereinabove. Selective epitaxial growth is carried out to create a low-doped channel region 610 . A high-K dielectric region 450 forms the gate insulator over which the gate material 460 is formed.
  • FIG. 7 shows a schematic cross-section 700 of a channel-last MOSFET according to another embodiment of the invention.
  • the channel region is removed by selective etching between the spaces created by the spacers 440 , as explained in further detail hereinabove.
  • a layer 710 that is highly doped, for example, an epitaxial ⁇ -layer as discussed hereinabove, is first formed in the channel region after which a selective epitaxial growth is carried out to create a low-doped channel region 610 before the channel is sealed with a high-K dielectric insulator layer 450 and the gate material 460 .
  • an embodiment of the “channel-last” process comprises of the building of the MOSFET's channel in a recess of a cavity etched into the well area between a drain area and a source area of the MOSFET.
  • the channel may comprise an un-doped or lightly doped epitaxial layer that is grown in the recess of the cavity.
  • an initial layer is formed in the recess of the cavity that is a single or multi-delta layer or a slab doped area.
  • the invention disclosed herein describes a general well which may be an N-well or a P-well, and hence suitable for a channel of a PMOS or NMOS transistor respectively.
  • the electrostatic characteristics of partially depleted SOI (silicon-on-insulator) transistors are sufficiently similar to bulk semiconductors that all the techniques described in this invention are equally applicable to partially depleted SOI devices.
  • a person of ordinary skill-in-the-art would readily understand that the invention can be adapted for use in a plurality of ways, including integrated circuits where all transistors or a portion thereof are manufactured using the techniques disclosed hereinabove.

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