US8982520B2 - USB port overvoltage protection - Google Patents

USB port overvoltage protection Download PDF

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US8982520B2
US8982520B2 US12/364,144 US36414409A US8982520B2 US 8982520 B2 US8982520 B2 US 8982520B2 US 36414409 A US36414409 A US 36414409A US 8982520 B2 US8982520 B2 US 8982520B2
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signal
impedance
transmission line
overvoltage protection
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US20100073837A1 (en
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Alexei A. Predtetchenski
Hans L. Magnusson
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Microchip Technology Inc
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Standard Microsystems LLC
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers

Definitions

  • This invention relates to electronic circuits, and more particularly, to an efficient method of input/output (I/O) port overvoltage protection of a high-speed port.
  • I/O input/output
  • USB Universal Serial Bus
  • USB-IF USB Implementers Forum
  • a USB interface is a master/slave architecture. From the frame of reference of a USB interface, the master is referred to as the “upstream” device, or host/hub, and the slave as the “downstream” device.
  • the interface consists of four wires: D+, D ⁇ , VBUS, and Ground.
  • the two data lines, D+ and D ⁇ , are for bi-directional data transfer and use differential drive techniques.
  • the wires VBUS and Ground are used to distribute power from the upstream host to the downstream device.
  • upstream and downstream are from the point-of-view of a particular USB interface.
  • USB devices are linked in series through hubs.
  • a USB hub is a device that allows many USB devices to be connected to a single USB port on the host computer or another hub. Each hub has one upstream port and a number of downstream ports. The upstream port connects the hub (directly or through other hubs) to the host. Other hubs or devices may be attached to the downstream ports.
  • USB hubs may be built into equipment, such as computer keyboards, computer monitors, a personal computer (PC), a smartphone, a video game console, an automotive infotainment system comprising one or more of a navigation application with real-time traffic, a hands-free communication application, and an audio/video storage and playback application; or other.
  • USB ports in vehicles, such as in dashboards or center consoles, that permit the connection of USB peripheral devices to the in-vehicle entertainment system, or infotainment system.
  • a portable audio player may be allowed to play audio and to control and display functions using the vehicle's own system.
  • Ford Motor Company's SYNC system is one example.
  • USB hubs introduces design issues not previously considered in industry specifications, such as the USB 2.0 Specification from the USB Implementers Forum.
  • the original applications for USB hubs were intended primarily for connecting digital devices, or USB peripheral devices, both together and to host computers while operating at a low voltage.
  • the maximum allowable voltage levels on the data and power lines of USB interfaces are less than the voltage levels used on lines both within automotive electronic modules and on wiring external to automotive electronic modules.
  • the USB data and power lines are typically powered up to 5V, and an automotive battery is able to supply 12V.
  • USB lines within an automotive dashboard or center console may be destroyed in the event they are shorted to the positive potential of a 12V automotive battery.
  • Many manufacturers of electrical automobile systems refer to the International Organization for Standardization (ISO) 7637 for defining electrical transient protection, which allows higher voltages than typical USB voltage levels.
  • ISO International Organization for Standardization
  • USB IF eye pattern diagrams may be used to diagnose signal-integrity problems that corrupt serial data in digital-communication systems.
  • Test Points 2 and 3 of the USB 2.0 Specification addresses new manners by which generation of eye pattern diagrams for packetized data are performed.
  • the USB 2.0 Specification describes difficult requirements to meet for overvoltage protection devices such as the rise and fall times, signal levels, and pulse skew of a corresponding eye pattern diagram. Even further, overvoltage protection of the data lines may be more difficult due to the high-speed data rate support of 480 MBits/sec for these data lines. At this speed the capacitance and inductance of the circuit board, connectors, and any additional circuitry becomes critical. These high-frequency capacitive and inductance effects make it difficult to satisfy all of the above requirements.
  • an interfacing system for connecting peripheral devices to a computing system comprises ports for conveying serial communications bi-directional signals and an overvoltage protection circuit.
  • the overvoltage protection circuit prevents an overvoltage condition on one port in response to an overvoltage event on a corresponding second port.
  • the overvoltage protection circuit is able to transmit the bidirectional signal between the two ports without signal attenuation defined by an industry standard specification such as Universal Serial Bus (USB) Implementers Forum (IF) eye pattern diagram test.
  • the interfacing system connects USB peripheral devices to an automotive infotainment system comprising an automotive battery potiential greater than a USB power supply.
  • the overvoltage protection circuit is configured to have a small footprint, and, therefore, does not utilize a power reference and comparator circuit.
  • the ports are configured to convey serial communications bi-directional signals with a high-speed data rate mode. The method is able to transmit these signals without signal attenuation defined by an industry standard specification such as Universal Serial Bus (USB) Implementers Forum (IF) eye pattern diagram test.
  • USB Universal Serial Bus
  • IF Implementers Forum
  • FIG. 1 is a generalized block diagram illustrating one embodiment of a computing system utilizing multiple peripheral devices.
  • FIG. 2 is a generalized block diagram illustrating one embodiment of a data bus interface with an overvoltage protection circuit.
  • FIG. 3 is a generalized flow diagram illustrating one embodiment of a method for overvoltage protection for a data bus interface connected to a high-voltage system.
  • computing system 100 utilizing a data bus interface to couple multiple peripheral devices is shown. This embodiment does not include all examples of functional blocks, control logic, and interfaces required both within and outside processing node 110 .
  • computing system 100 may comprise two or more processing nodes 110 . The embodiment shown is for a simple illustrative purpose.
  • Computing system 100 includes at least one processing node 110 .
  • processing node 110 is an automotive infotainment system operating from a 12V automobile battery, wherein processing node 110 comprises one or more of a navigation application with real-time traffic, a hands-free communication application, an audio/video storage and playback application, or other.
  • Processing node 110 may include system bus 120 , processing unit 114 , memory subsystem 112 , interface logic 140 , Universal Serial Bus (USB) host 130 , and USB hub core 132 .
  • USB Universal Serial Bus
  • the illustrated functionality of processing node 110 is incorporated upon a single integrated circuit.
  • the illustrated functionality of processing node 110 may be provided on a system-on-chip (SOC), on separate semiconductor chips on a motherboard or card, or other.
  • SOC system-on-chip
  • processing unit 114 includes one or more processor cores, wherein each processor core includes circuitry for executing instructions according to a predefined instruction set. For example, the x86 instruction set architecture (ISA) may be selected. Alternatively, the Alpha, PowerPC, or any other instruction set architecture may be selected. Each processor core may be implemented to simultaneously execute multiple software threads of a software application. In another embodiment, processing unit 114 includes one or more application specific integrated circuits (ASICs) or microcontrollers. In addition, processing unit 114 may include one or more digital signal processors (DSPs), graphic processing units (GPUs), analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Other data processing semiconductor chip designs included within processing unit 114 are possible and contemplated. Further, physically, these data processing designs may be implemented outside of processing unit 114 for interfacing reasons, on-die routing and signal integrity reasons, or other reasons.
  • DSPs digital signal processors
  • GPUs graphic processing units
  • ADCs analog-to-digital converter
  • processing unit 114 accesses memory storage for data and instructions or commands. Although not shown, it is possible an ASIC, or other data processing die, may receive a command directly from an outside source via interface 140 .
  • a cache memory subsystem implemented as a L1 cache structure configured to store blocks of data, and possibly with an additional L2 cache structure, is integrated within processing unit 114 .
  • Memory subsystem 112 is implemented as a L2 or L3 cache structure and may be directly coupled to processing unit 114 . If a requested block is not found in an integrated cache structure or memory subsystem 112 , then a read request may be generated and transmitted to a memory controller not shown in order to access outside memory to which the missing block is mapped.
  • memory subsystem 112 may comprise any suitable memory devices in addition to a cache structure.
  • these memories may comprise one or more RAMBUS dynamic random access memories (DRAMs), synchronous DRAMs (SDRAMs), DRAM, static RAM, sequential storage elements such as flip-flops and latches, etc.
  • DRAMs RAMBUS dynamic random access memories
  • SDRAMs synchronous DRAMs
  • DRAM static RAM
  • sequential storage elements such as flip-flops and latches, etc.
  • System bus 120 is configured to respond to control packets received on the links to which processing node 110 is coupled, to generate control packets in response to processing unit 114 and/or memory subsystems 112 , to generate probe commands and response packets in response to transactions selected by a memory controller not shown, and to route packets for which node 110 is an intermediate node to other nodes through interface logic 140 .
  • Interface logic 140 may include logic to receive packets and synchronize the packets to an internal clock used by system bus 120 .
  • Processing node 110 may be coupled to one or more peripheral devices 150 a - 150 d .
  • peripheral devices 150 a - 150 d may be collectively referred to as peripheral devices 150 .
  • peripheral devices 150 may include portable storage devices, gamepads, smartphones, personal data assistants (PDAs), portable audio/video players, cameras, or other.
  • PDAs personal data assistants
  • a peripheral device 150 may consist of several logical sub-devices that are referred to as device functions.
  • a single peripheral device 150 may provide several functions. For example, a portable DVD player has both a video device function and built-in speakers, which is an audio device function.
  • Peripheral devices 150 may typically operate at low voltage levels such as 5V wherein processing node 110 may be communicatively coupled to a 12V automobile battery. Should an overvoltage event occur, such as the 12V potential of the automobile battery is temporarily shorted to an input/output (I/O) port within data bus logic located in interface logic 140 , then I/O port may be permanently damaged.
  • I/O input/output
  • serial data communications such as a Universal Serial Bus (USB)
  • USB Universal Serial Bus
  • a USB system has an asymmetric design, consisting of a USB host 130 comprising one or more USB host controllers, a USB hub core 132 comprising a multitude of downstream USB ports, and multiple peripheral devices 150 connected in a tiered-star topology. Additional USB hubs 132 may be included in the tiers, allowing branching into a tree structure with up to five tier levels. USB devices, such as peripheral devices 150 and USB hubs 132 , are linked in series through USB hubs 132 .
  • One hub known as a root hub, may be built into a host controller within USB host 130 .
  • a USB host 130 may have multiple host controllers and each host controller may provide one or more USB ports.
  • USB host 130 connects a host system, such as processing node 110 , to other network and storage devices, such as peripheral devices 150 .
  • a host controller interface is a register level interface, which allows a host controller within USB host 130 to communicate with the operating system of processing node 110 .
  • the HCI may include digital logic engines in Field Programmable Gate Arrays (FPGAs) in addition to analog circuitry to manage the high-speed differential signals.
  • FPGAs Field Programmable Gate Arrays
  • HCI may require a device driver, or a Host Controller Driver (HCD).
  • HCI Host Controller Driver
  • Two modern versions of HCI include an Open Host Controller Interface (OHCI) and an Enhanced Host Controller Interface (EHCI). They are embedded in the USB host 130 , which routes the differing USB speeds accordingly without user intervention.
  • USB hub core 132 supports low-speed (LS) transfers, or 1.5 Mbit/s, full-speed (FS) transfers, or 12 Mbit/s, and high-speed (HS) transfers, or 480 Mbit/s.
  • LS low-speed
  • FS full-speed
  • HS high-speed
  • USB HS signals may introduce different circuit effects than LS or FS signals due to the behavior of capacitances coupled to corresponding data lines. These effects are discussed in more detail later.
  • the interfaces between USB hub core 132 and both USB host 130 and interface 140 may include USB 2.0 Transceiver Macrocell Interface (UTMI) or an extended version (UTMI+).
  • the interfaces may include UTMI+ Low Pin Interface (ULPI), which is a 12-pin interface standard for connecting USB core logic to a USB transceiver.
  • ULPI may be implemented as a wrapper around both UTMI+ and a physical layer (PHY) in order to reduce pin count in Hi-Speed (HS) USB systems.
  • interface logic 140 may comprise buffers for receiving packets from an outside link and for buffering packets to be transmitted upon the link.
  • Computing system 100 may employ any suitable flow control mechanism for transmitting data.
  • Interface logic 140 may include a physical layer (PHY), which may be integrated into most USB systems in order to provide a bridge between the digital and modulated parts of the interface.
  • PHY connects a link layer device to a physical medium such as an optical fibre or copper cable.
  • a PHY typically includes a Physical Coding Sublayer (PCS) and a Physical Medium Dependent (PMD) sublayer.
  • PCS Physical Coding Sublayer
  • PMD Physical Medium Dependent
  • the PCS encodes and decodes the data that is transmitted and received. The purpose of the encoding is to make it easier for the receiver to recover the signal.
  • the PMD consists of a transceiver for the physical medium.
  • FIG. 2 one embodiment of a data bus interface with an overvoltage protection circuit connected to a high-voltage system is shown.
  • a USB peripheral device 150 may be connected to an automotive infotainment system such as processing node 110 via an interface, such as interface logic 140 .
  • a peripheral device's power line, or VBUS, Ground, and two data lines, D+ and D ⁇ , are connected to corresponding lines within interface logic 140 that couple these signals to a downstream port of a USB hub.
  • a portable media player may be plugged-in to a USB receptacle in a dashboard of an automobile.
  • the D+ data line of the portable media player may be coupled to ConnectorData 1 230 in FIG. 2 .
  • the corresponding D ⁇ data line of the portable media player may be coupled to ConnectorData 2 232 in FIG. 2 .
  • the data lines PortData 1 202 and PortData 2 204 may be coupled to a corresponding upstream port of the USB interface, which is coupled to USB wires routed within the interior of the automobile to a downstream port of a USB host.
  • overvoltage event such as a 12V potential of an automobile battery is temporarily shorted to a USB line, may permanently damage the line and corresponding ports. Therefore, a method of protection may be required for the interface connections.
  • overvoltage protection may be needed at the USB in-dash receptacle where a USB peripheral device is plugged-in. Such a device, protection circuit 210 , is shown in FIG. 2 and will be described in further detail shortly. Similar overvoltage protection may be required at the interface between the USB host downstream port and the USB wires routed to the in-dash USB receptacle both of which are not shown but would have a similar topology as that depicted in FIG. 2 .
  • the overvoltage protection method may differ between the VBUS and Ground lines and the data lines due to different electrical characteristics.
  • protection for the VBUS line may be simpler than protection for the two data lines.
  • Methods including a diode bridge, such as bridge 220 , an integrated circuit containing a voltage reference and a comparator for overvoltage detection and correction in combination with a bulk capacitor, such as capacitor 226 , for electrostatic discharge (ESD) correction have been used and are known to those skilled in the art.
  • ESD electrostatic discharge
  • a short circuit to the Ground line may occur or an over-current condition inside the peripheral device that is connected to the USB port.
  • One manner to protect a USB IC port may be to incorporate a variable-resistance device between the USB IC port and an external USB connector, such as ConnectorData 1 230 and ConnectorData 2 232 , respectively.
  • the protection device is a quick-switch (Q-Switch), such as a MOSFET transistor, controlled by an overvoltage detector. During an overvoltage event, the detector disengages the Q-Switch.
  • Q-Switch quick-switch
  • an NMOS transistor is used as a Q-Switch with its gate terminal used as a threshold detector, similar to simple Q-Switch level translation applications.
  • transistor 216 When the voltage level on node A or node B reaches the threshold voltage of transistor 216 of FIG. 2 , transistor 216 enters an ON state and, in one embodiment, may provide a low series resistance between the drain and source terminals, such as 1 to 2 ohms. This low series resistance value may be appreciably smaller than the impedance of the transmission line coupled to node A. For example, this transmission line may have a 90 ohm resistance and transistor 216 provides a low series resistance that is only 2.2% of this value.
  • LS low-speed
  • FS full-speed
  • transistor 216 In order to transmit high-speed (HS) USB signal levels comprising a data rate of 480 MBits/sec, there may be several restrictions for the parameters of the Q-Switch, or transistor 216 .
  • transistor 216 should have a low series resistance (drain-to-source) value in the ON state.
  • transistor 216 should only introduce a small capacitance-to-ground value in the ON state.
  • the necessary parameter ranges may be 1 to 2 ohms of series resistance and a maximum of 10 to 20 picoFarads (pF) of capacitance to ground.
  • these parameter restrictions will aid in transistor 216 switching to an OFF state quickly enough so as not to expose the protected USB ports, which are coupled to lines 202 and 204 , to high-voltage ringing associated with the short event.
  • the drain and source terminals of transistor 216 are bypassed by a series RC chain, resistor 212 and capacitor 214 , in order to prevent the circuit from excessive ringing when the switch is disengaged, or switches to an OFF state, in the presence of an inductive high-current source.
  • a suppression of ringing may occur with a 22 ohm resistor 212 and a 10 nF capacitor 214 .
  • resistor 218 is incorporated into protection circuit 210 .
  • the USB signal path flows from line 230 to transistor 218 to line 202 , or vice-versa, since the USB signal path is bi-directional. Without resistor 218 , the USB signal path may be shorted by the parasitic capacitances of transistor 218 to the gate terminal of transistor 218 , or VBUS.
  • transistor 216 has a gate-to-drain parasitic capacitance, Cgd, between line 230 and the gate terminal.
  • transistor 218 has gate-to-source parasitic capacitance, Cgs, between line 202 and the gate terminal.
  • transistor 216 may switch due to transistor 216 is a symmetric device and the USB signal path is bi-directional. If transistor 216 has a low drain-to-source series resistance, Rds, in the ON state, such as 1 to 2 ohms, as desired, then the two parasitic capacitances, Cgd and Cgs, appear in parallel between the gate terminal and the USB signal path.
  • Rds drain-to-source series resistance
  • a capacitor may easily passes high frequencies and appears to be a virtual short circuit to very high frequencies.
  • the capacitive reactance depends on frequency, and resultingly, the voltage and current likewise vary with frequency.
  • a capacitor offers infinite reactance to a DC signal and nearly zero reactance to a very high frequency signal.
  • a modern transistor such as transistor 216 of protection circuit 210 , that has a 1 ohm Rds value and is able to hold a 20V potential on its terminals typically has a 25 pF to 50 pF range for each of Cgs and Cgd.
  • These high parasitic capacitance values for Cgs and Cgd in combination with a high-frequency signal, such as a high-speed USB signal of 480 Mbits/s, will create a low reactance from the USB signal path to the gate terminal of transistor 216 .
  • USB lines In contrast, the transmission line impedance of USB lines is typically 90 Ohms. The resultant shorting of the USB signal path to the gate terminal due to this small 6.6 ohm impedance will disrupt both the signal integrity of the USB signal path and a USB-IF high-speed eye pattern diagram test. If a transistor with a very low parasitic capacitance is chosen, then it would have a larger unacceptable Rds value and other USB tests would fail.
  • the 6.6 ohm impedance of the given example may be increased above the value of the USB line impedance since resistor 218 is in series with the capacitances Cgd and Cgs.
  • resistor 218 is chosen to have a resistance of 330 ohms
  • the resulting impedance is more than three times greater than the transmission line impedance. Now the shunting effect is much smaller, and both the signal integrity of the USB line may be satisfactory and the USB-IF eye pattern diagram test may be satisfied.
  • FIG. 3 illustrates a method 300 for overvoltage protection for a data bus interface connected to a high-voltage system.
  • Method 300 may be modified by those skilled in the art in order to derive alternative embodiments.
  • the steps in this embodiment are shown in sequential order. However, some steps may occur in a different order than shown, some steps may be performed concurrently, some steps may be combined with other steps, and some steps may be absent in another embodiment.
  • a high-voltage system is powered up and executes applications in block 302 .
  • the high-voltage system is an automotive infotainment system with one or more USB ports that operate at lower voltages.
  • a protection switch within the system operates in an ON state while maintaining signal integrity in a High-Speed (HS) data rate mode.
  • the protection switch is a nmos transistor, such as transistor 216 of protection circuit 210 , utilized to connect a USB integrated circuit (IC) port to an external connector for a peripheral device. If an overvoltage event occurs, such as a USB wires shorting to a high potential of an automotive battery (conditional block 306 ), then in block 308 the protection switch quickly turns off in order to prevent damage to a USB IC port. For example, a wire-harness may be accidentally pierced during assembly and later cause shorts between the automotive 12V battery and the USB wires used in an infotainment system.
  • a circuit such as protection circuit 210 may both protect USB IC ports while preserving formal conformance to USB-IF Eye Diagram tests in LS, FS, and HS modes.

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9891684B2 (en) 2016-04-06 2018-02-13 Hewlett-Packard Development Company, L.P. USB type-C dual-role power ports
US20190044322A1 (en) * 2017-08-04 2019-02-07 Dell Products L.P. Over-voltage detection and port protection
US10579118B2 (en) 2016-01-06 2020-03-03 Hewlett-Packard Development Company, L.P. Detection circuits
US20210226444A1 (en) * 2020-01-22 2021-07-22 Infineon Technologies Ag Overvoltage Protection Circuit and Device

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101847859B (zh) * 2009-03-25 2013-08-07 深圳富泰宏精密工业有限公司 接口设备及使用该接口设备的电子装置
KR101743518B1 (ko) * 2010-08-12 2017-06-20 에스프린팅솔루션 주식회사 화상형성장치 및 화상형성장치용 회로 기판
TWI422111B (zh) * 2010-11-30 2014-01-01 Himax Tech Ltd 過電壓保護電路
CN102609065A (zh) * 2011-01-19 2012-07-25 鸿富锦精密工业（深圳）有限公司 过流保护装置
US8689033B2 (en) 2011-07-27 2014-04-01 Freescale Semiconductor, Inc. Power supply and data signal interface circuit with overvoltage protection
US8806255B2 (en) 2011-08-31 2014-08-12 Hewlett-Packard Development Company, L.P. Interface connection control based on voltage at input rail
US9142982B2 (en) * 2011-11-14 2015-09-22 Mediatek Inc. Method and apparatus for performing charging port detection control
US8990592B2 (en) 2012-01-25 2015-03-24 Smsc Holdings S.A.R.L. Overcoming limited common-mode range for USB systems
US9015393B2 (en) * 2012-03-13 2015-04-21 Nokia Corporation Master-slave interface
US8767370B2 (en) 2012-07-25 2014-07-01 International Business Machines Corporation Providing noise protection in a signal transmission system
US9099864B2 (en) 2013-01-25 2015-08-04 Apple Inc. Electronic device with connector fault protection circuitry
WO2014117866A1 (en) * 2013-02-01 2014-08-07 SMSC Holdings, S.a.r.l. Overcoming limited common-mode range for usb sytems
US10164423B2 (en) * 2014-08-19 2018-12-25 Microchip Technology Incorporated Method and system for ground plane isolation
US9977475B2 (en) * 2014-09-30 2018-05-22 Apple Inc. Over voltage protection for a communication line of a bus
CN105739663B (zh) * 2014-12-11 2018-10-12 鸿富锦精密工业(武汉)有限公司 Usb电源控制电路
WO2016153576A1 (en) * 2015-03-20 2016-09-29 Dialog Semiconductor Inc. Soft-short overvoltage protection for data lines in quick charge usb charger
US10784695B2 (en) * 2015-08-13 2020-09-22 Apple Inc. Reducing transient currents in receptacle circuitry during plug extraction
US20170168979A1 (en) * 2015-12-09 2017-06-15 Qualcomm Incorporated Capacitively coupling differential data lines of a usb2 physical layer interface transceiver (phy) to one or more components of a high speed module in response to a transition of the phy into high speed mode
KR102538837B1 (ko) 2016-10-05 2023-06-01 삼성전자 주식회사 과전압 방지를 위한 전자 장치
JP6688216B2 (ja) * 2016-12-28 2020-04-28 キヤノン株式会社 電子機器および制御方法
US11175722B2 (en) 2017-04-20 2021-11-16 Hewlett-Packard Development Company, L.P. Computing device power management
US11112844B2 (en) 2017-05-24 2021-09-07 Qualcomm Incorporated Universal serial bus (USB) type-C and power delivery port with scalable power architecture
KR102692156B1 (ko) 2018-02-21 2024-08-07 삼성전자주식회사 외부 전자 장치와 연결된 신호 단자에 감지된 전압의 크기에 따라 외부 전자 장치로 출력하는 전압을 제어 하기 위한 방법 및 전자 장치
US10855069B2 (en) 2018-04-17 2020-12-01 Texas Instruments Incorporated USB type-C/PD controller having integrated VBUS to CC short protection
US10381787B1 (en) * 2018-05-21 2019-08-13 Cypress Semiconductor Corporation Voltage protection for universal serial bus type-C (USB-C) connector systems
WO2020000371A1 (zh) * 2018-06-29 2020-01-02 华为技术有限公司 一种usb座运行电路以及终端
US11088540B2 (en) 2018-10-30 2021-08-10 Semiconductor Components Industries, Llc Switch circuit with high voltage protection that reduces leakage currents
CN109921959A (zh) * 2019-03-22 2019-06-21 维沃移动通信有限公司 一种参数调整方法及通信设备
TWI762296B (zh) 2021-05-03 2022-04-21 威鋒電子股份有限公司 保護電路以及集線器晶片
TWI806093B (zh) * 2021-07-12 2023-06-21 致伸科技股份有限公司 一種電流偵測與電流保護機制之校準方法與運用該方法之校準裝置
US11764783B1 (en) 2022-05-20 2023-09-19 Semiconductor Components Industries, Llc Driver for mitigating high-voltage surges at host and sink interface devices

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946175A (en) * 1998-02-17 1999-08-31 Winbond Electronics Corp. Secondary ESD/EOS protection circuit
US6633470B2 (en) 2000-12-19 2003-10-14 Intersil Americas Inc. Overvoltage protection circuit for bidirectional transmission gate
US6775121B1 (en) 2002-08-09 2004-08-10 Tii Network Technologies, Inc. Power line surge protection device
US7085117B2 (en) 2003-10-02 2006-08-01 Axiohm Transaction Solutions, Inc. EMC immunity improvements to USB interface
US20060267606A1 (en) * 2005-05-31 2006-11-30 Joseph Groshong Signal probe and probe assembly
US7190564B2 (en) * 2004-09-30 2007-03-13 The Bergquist Torrington Company Snubber circuit
US20080165457A1 (en) * 2007-01-10 2008-07-10 William James Premerlani Micro-Electromechanical System Based Electric Motor Starter
US20090109587A1 (en) * 2007-10-26 2009-04-30 Caterpillar Inc. Over voltage protection for reduced level electrical signal interfaces
US7649726B2 (en) 2004-08-16 2010-01-19 National Instruments Corporation Protection circuit for general-purpose digital I/O lines
US20100169511A1 (en) * 2008-12-31 2010-07-01 Dunstan Robert A Universal serial bus host to host communications

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5946175A (en) * 1998-02-17 1999-08-31 Winbond Electronics Corp. Secondary ESD/EOS protection circuit
US6633470B2 (en) 2000-12-19 2003-10-14 Intersil Americas Inc. Overvoltage protection circuit for bidirectional transmission gate
US6775121B1 (en) 2002-08-09 2004-08-10 Tii Network Technologies, Inc. Power line surge protection device
US7085117B2 (en) 2003-10-02 2006-08-01 Axiohm Transaction Solutions, Inc. EMC immunity improvements to USB interface
US7649726B2 (en) 2004-08-16 2010-01-19 National Instruments Corporation Protection circuit for general-purpose digital I/O lines
US7190564B2 (en) * 2004-09-30 2007-03-13 The Bergquist Torrington Company Snubber circuit
US20060267606A1 (en) * 2005-05-31 2006-11-30 Joseph Groshong Signal probe and probe assembly
US20080165457A1 (en) * 2007-01-10 2008-07-10 William James Premerlani Micro-Electromechanical System Based Electric Motor Starter
US20090109587A1 (en) * 2007-10-26 2009-04-30 Caterpillar Inc. Over voltage protection for reduced level electrical signal interfaces
US20100169511A1 (en) * 2008-12-31 2010-07-01 Dunstan Robert A Universal serial bus host to host communications

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10579118B2 (en) 2016-01-06 2020-03-03 Hewlett-Packard Development Company, L.P. Detection circuits
US9891684B2 (en) 2016-04-06 2018-02-13 Hewlett-Packard Development Company, L.P. USB type-C dual-role power ports
US20190044322A1 (en) * 2017-08-04 2019-02-07 Dell Products L.P. Over-voltage detection and port protection
US10680432B2 (en) * 2017-08-04 2020-06-09 Dell Products L.P. Over-voltage detection and port protection
US20210226444A1 (en) * 2020-01-22 2021-07-22 Infineon Technologies Ag Overvoltage Protection Circuit and Device
US11791624B2 (en) * 2020-01-22 2023-10-17 Infineon Technologies Ag Overvoltage protection circuit and device

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