US8969154B2 - Methods for fabricating semiconductor device structures and arrays of vertical transistor devices - Google Patents

Methods for fabricating semiconductor device structures and arrays of vertical transistor devices Download PDF

Info

Publication number
US8969154B2
US8969154B2 US13/215,968 US201113215968A US8969154B2 US 8969154 B2 US8969154 B2 US 8969154B2 US 201113215968 A US201113215968 A US 201113215968A US 8969154 B2 US8969154 B2 US 8969154B2
Authority
US
United States
Prior art keywords
gate
forming
trench
insulator
metal seeds
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active, expires
Application number
US13/215,968
Other versions
US20130049120A1 (en
Inventor
Gurtej S. Sandhu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
US Bank NA
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SANDHU, GURTEJ S.
Priority to US13/215,968 priority Critical patent/US8969154B2/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to EP12825988.4A priority patent/EP2748856B1/en
Priority to PCT/US2012/051711 priority patent/WO2013028685A2/en
Priority to CN201280041260.2A priority patent/CN103765595B/en
Priority to KR1020147003763A priority patent/KR101570945B1/en
Priority to JP2014527242A priority patent/JP5883508B2/en
Publication of US20130049120A1 publication Critical patent/US20130049120A1/en
Priority to US14/629,555 priority patent/US9356155B2/en
Application granted granted Critical
Publication of US8969154B2 publication Critical patent/US8969154B2/en
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON TECHNOLOGY, INC.
Priority to US15/167,765 priority patent/US10002935B2/en
Assigned to MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT reassignment MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT PATENT SECURITY AGREEMENT Assignors: MICRON TECHNOLOGY, INC.
Assigned to U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: MICRON TECHNOLOGY, INC.
Priority to US16/004,908 priority patent/US10446692B2/en
Assigned to JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC.
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Priority to US16/587,921 priority patent/US11011647B2/en
Assigned to MICRON TECHNOLOGY, INC. reassignment MICRON TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Assigned to MICRON SEMICONDUCTOR PRODUCTS, INC., MICRON TECHNOLOGY, INC. reassignment MICRON SEMICONDUCTOR PRODUCTS, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Priority to US17/313,646 priority patent/US11652173B2/en
Active legal-status Critical Current
Adjusted expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78642—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H10B99/22—Subject matter not provided for in other groups of this subclass including field-effect components
    • H01L27/1052—
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out

Definitions

  • the invention in various embodiments, relates generally to the field of integrated circuit design and fabrication. More particularly, this disclosure relates to vertically-oriented transistors and methods for fabricating the transistors.
  • Fabricating a semiconductor device, such as a transistor, upon a substrate necessarily leads to occupation of a certain surface area of the substrate by the footprint of the device. Often, the available surface area of a given substrate is limited, and maximizing the use of the substrate requires maximizing the density of devices fabricated on the substrate. Minimizing the dimensions of components of a device, such as a transistor, accommodates minimizing the overall footprint of the device and maximizing of the device density. This accommodates formation of a greater number of devices on a given substrate.
  • Transistors are often constructed upon the primary surface of the substrate.
  • the primary surface is generally the uppermost, exterior surface of the substrate.
  • the primary surface of the substrate is considered to define a horizontal plane and direction.
  • FET Field effect transistor
  • FET Field effect transistor
  • Transistor structures that have channel regions that are primarily parallel to the primary surface of the substrate are referred to as planar FET structures, and those having channel regions that are generally perpendicular to the primary surface of the substrate are referred to as vertical FET (“VFET”) transistor structures.
  • VFET vertical FET
  • planar FET devices can be distinguished from VFET devices based upon both the direction of current flow as well as on the general orientation of the channel region.
  • VFET devices are devices in which the current flow between the source and drain regions of the device is primarily substantially orthogonal to the primary surface of the substrate.
  • Planar FET devices are devices in which the current flow between source and drain regions is primarily parallel to the primary surface of the substrate.
  • a VFET device includes a vertical, so-called “mesa,” also referred to in the art as a so-called “fin,” that extends upward from the underlying substrate. This mesa forms part of the transistor body. Generally, a source region and a drain region are located at the ends of the mesa while one or more gates are located on one or more surfaces of the mesa or fin. Upon activation, current flows through the channel region within the mesa.
  • VFETs are generally thinner in width (i.e., in the dimension in a plane parallel to the horizontal plane defined by the primary surface of the substrate) than planar FETs. Therefore, vertical transistors are conducive to accommodating increased device packing density and are conducive for inclusion within a cross-point memory array. In such an array, multiple VFETs are ordered in stacked rows and columns. However, even with this arrangement, the packing density is at least partially limited by the minimal dimensions of the components of the vertical transistor, including the gate and channel components.
  • Scaling or otherwise reducing the dimensions of transistor components depends, at least in part, on the limitations of conventional semiconductor fabrication techniques, physical limitations of materials used in the fabrication, and minimal properties required for fabricating an operational device.
  • a gate thickness of greater than 5 nanometers is generally required.
  • the total width of the device must take into account twice the width of the gate material. Therefore, a typical VFET surround gate will have at least 10 nanometers of the VFET device's width consumed by the gate conductor.
  • FIG. 1 is a cross-sectional, top and front perspective, schematic view of a vertical field effect transistor of an embodiment of the present disclosure
  • FIGS. 2-11 are cross-sectional, top and front perspective, schematic views of a semiconductor device structure during various stages of processing according to an embodiment of the present disclosure.
  • FIGS. 12-21 are cross-sectional, top and front perspective, schematic views of a semiconductor device structure during various stages of processing according to another embodiment of the present disclosure.
  • a semiconductor device structure, an array of vertical transistor devices, and methods for fabricating such structures or devices are disclosed.
  • the vertical transistor device and array of VFETs all include thin gate conductors, making the present VFET structure and method conducive in high-device-density integrated circuit designs, including cross-point memory arrays.
  • the term “substrate” means and includes a base material or construction upon which materials, such as vertical field effect transistors, are formed.
  • the substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode or a semiconductor substrate having one or more layers, structures or regions formed thereon.
  • the substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material.
  • the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates or silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation or other semiconductor or optoelectronic materials, such as silicon-germanium (Si 1-x Ge x ), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP).
  • SOI silicon-on-insulator
  • SOS silicon-on-sapphire
  • SOOG silicon-on-glass
  • epitaxial layers of silicon on a base semiconductor foundation or other semiconductor or optoelectronic materials such as silicon-germanium (Si 1-x Ge x ), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphi
  • graphene means and includes a poly-cyclic aromatic molecule having a plurality of carbon atoms that are connected to each other by covalent bonds.
  • the plurality of carbon atoms may form a plurality of six-member rings, which function as a standard repeating unit, and may further include a five-membered ring and/or a seven-membered ring.
  • the graphene may be a one atom thick material of the six-member rings in which the carbon atoms are covalently bonded and have sp 2 hybridization.
  • the graphene may include the monolayer of graphene. Alternatively, the graphene may include multiple monolayers of graphene stacked upon one another.
  • the graphene may have a maximum thickness of about 5 nanometers. If multiple monolayers of graphene are used, the graphene may be used as a gate in a semiconductor device structure. If a one atom thick material is used, the graphene may be used as a switchable material.
  • first may describe various elements, components, regions, layers, and/or sections, none of which are limited by these terms. These terms are used only to distinguish one element, component, region, material, layer, or section from another element, component, region, material, layer, or section.
  • first element a first component
  • first region a first material
  • first layer a first section
  • second element a second element, a second component, a second region, a second material, a second layer, or second section without departing from the teachings herein.
  • spatially relative terms such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features.
  • the term “below” can encompass both an orientation of above and below, depending on the context in which the tern is used, which will be evident to one of ordinary skill in the art.
  • the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • reference to an element as being “on” another element means and includes the element being directly on top of, adjacent to, underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to, underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
  • the terms “comprises,” “comprising,” “includes,” and/or “including” specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
  • Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes or regions as illustrated but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box shaped may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.
  • the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, and physical vapor deposition (“PVD”).
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • PVD physical vapor deposition
  • the materials may be grown in situ.
  • the technique for depositing or growing the material may be selected by a person of ordinary skill in the art.
  • removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching, abrasive planarization, or other known material-removal methods.
  • FIG. 1 is a cross-sectional, front and top perspective view of a schematic of a VFET 100 semiconductor device having a structure of the present disclosure.
  • the VFET 100 includes a mesa 120 extending above a substrate 50 such that a bottom side 125 of the mesa 120 sits on a horizontally planar upper surface of the substrate 50 .
  • the mesa 120 extends above the substrate 50 in a direction perpendicular to the substrate 50 .
  • the mesa 120 has a first side 121 and a second side 122 that is opposite and substantially parallel to the first side 121 .
  • a channel region 130 passes through the mesa 120 between the first side 121 and the second side 122 .
  • the channel region 130 is configured to allow current to flow between a source region (not shown) and a drain region (not shown).
  • a top side 126 of the mesa 120 may be in operable communication with an electrode (not shown) or interconnect (not shown).
  • a first gate 140 is provided on the first side 121 of the mesa 120 .
  • the first gate 140 is operative to control current flow in the channel region 130 .
  • a second gate 140 may be provided on the second side 122 of the mesa 120 , as well, the second gate 140 being operative to control, in conjunction with the first gate 140 , current flow in the channel region 130 of the mesa 120 .
  • Each gate 140 includes a gate insulator 160 and an overlying gate conductor 150 .
  • the gate insulator 160 may be provided directly on the first and/or second sides 121 , 122 of the mesa 120 .
  • the gate conductor 150 may be provided directly on the gate insulator 160 and may surround the vertical sides of the mesa 120 , i.e., may surround the first side 121 , the second side 122 , a third side 123 , and a fourth side 124 of the mesa 120 .
  • the third side 123 and fourth side 124 may be opposite and parallel one another and arranged perpendicularly to the first side 121 and the second side 122 .
  • the gate 140 is provided only on the first side 121 of the mesa 120 . In still other embodiments, the gate 140 is provided only on the first side 121 and second side 122 of the mesa 120 , but not on the third side 123 or the fourth side 124 .
  • the gate conductor 150 of the sidewall gate structure 140 substantially overlies the entire exterior surface of the gate insulator 160 (i.e., the surface of the gate insulator 160 that is opposite and substantially parallel to the surface of the gate insulator 160 that is proximate to the mesa 120 ).
  • the gate conductor 150 of the gate 140 overlies only a portion of the exterior surface of the gate insulator 160 .
  • the gate conductor 150 is structured as a ring-gate conductor.
  • the gate conductor 150 of the present VFET 100 is a gate conductor, defining a gate conductor thickness G (i.e., the dimension of the shortest side of the gate conductor 150 , when such gate conductor 150 is construed as having a three-dimensional box shape) of less than or equal to about 5 nanometers. Therefore, according to the depicted VFET 100 having a pair of gates 140 , the thickness of the gate conductor 150 contributes twice the thickness G of the gate conductor 150 to the overall width C of one formed VFET cell ( FIG. 11 and FIG. 21 ).
  • the thickness G of the gate conductor 150 may be less than the thickness I of the gate insulator 160 , which is defined by the dimension of the shortest side of the gate insulator 160 , when such gate insulator 160 is construed as having a three-dimensional box shape.
  • the gate conductor 150 may be formed from graphene, or at least a portion of the gate conductor 150 may include graphene.
  • Graphene exhibits high electrical conductivity and has a single atom body thickness. Therefore, graphene possesses great potential for high-speed electronics.
  • graphene is a one-atom thick planar sheet of sp 2 -bonded carbon atoms that are densely packed in a honeycomb lattice such that the carbon atoms of graphene sheets are connected to each other in an extended array of hexagonal rings. Individual graphene sheets may be stacked. Therefore, the gate conductor 150 may include a plurality of layers of graphene. If multiple monolayers of graphene are used, the graphene may be used as the gate conductor 150 . If a one atom thick material is used, the graphene may be used as a switchable material in the semiconductor device.
  • a semiconductor device structure including the vertical transistor devices comprises a mesa extending above a substrate and a first gate on the first side of the mesa is disclosed.
  • the mesa comprises a channel region between a first side and a second side of the mesa.
  • the first gate comprises a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator.
  • FIGS. 2-11 depict various stages of processing of a plurality of vertical transistors in accordance with embodiments of the present method for fabricating a semiconductor device, such as a VFET 100 device, as well as for fabricating an array 300 ( FIG. 10 ) of vertical transistor devices 100 .
  • the present method includes forming a plurality of metal seeds 110 upon a substrate 50 .
  • the metal seeds 110 are spaced from one another and arranged in parallel.
  • the metal seeds 110 may be formed at pitch.
  • Each metal seed 110 includes a first side 111 , second side 112 , bottom side 115 , and top side 116 . According to the depiction in FIG.
  • the metal seeds 110 are positioned such that the bottom side 115 of each metal seed 110 is adjacent to the substrate 50 , and the top side 116 of each metal seed 110 is opposite the bottom side 115 and directed upward from substrate 50 .
  • the first side 111 of one metal seed 110 is positioned opposite and parallel to the second side 112 of a neighboring metal seed 110 .
  • the metal seeds 110 may be evenly spaced from one another, arranged in parallel, such that each metal seed 110 is separated from each adjacent and parallel metal seed 110 by a trench having a width M equal to a first distance.
  • the metal seeds 110 may be spaced unevenly from one another such that one metal seed 110 is spaced further from a first neighboring metal seed 110 than it is spaced from a second neighboring metal seed 110 .
  • the metal seeds 110 may be spaced unevenly such that one metal seed 110 is spaced further from a neighboring metal seed 110 at a first end than it is spaced from the neighboring metal seed 110 at a second end.
  • the material of the metal seed 110 may be any metal conducive for forming a gate conductor 150 , such as a gate conductor of graphene, thereupon.
  • a gate conductor of graphene such as a gate conductor of graphene
  • copper, nickel, iridium, ruthenium, combinations thereof, and solid mixtures containing any or all of these metals may be used as the material of the metal seed 110 .
  • the metal seed 110 may be formed from copper, such as polycrystalline copper.
  • the method for fabricating a semiconductor device further includes forming a conductor material upon each of the plurality of metal seeds 110 to form a gate conductor 150 , including gate conductor sidewalls aligning each of the first sides 111 and second sides 112 of the metal seeds 110 .
  • the conductor material may be formed conformally over the first side 111 , second side 112 , and top side 116 of the metal seeds 110 .
  • the conductor material of the gate conductors 150 may be formed by any suitable technique, including, but not limited to, CVD, ALD, plasma-enhanced ALD, or other known methods. Portions of the conductor material overlying an upper surface of the substrate 50 , if any, may be removed by conventional techniques, exposing the substrate 50 .
  • the conductor material of the gate conductor 150 may be formed of graphene.
  • Various methods of forming graphene are known.
  • graphene may be formed using ALD, CVD, or other known methods.
  • the graphene may be formed directly upon the exterior surface of the metal seeds 110 .
  • the conductor material may overlay at least the first side 111 , top side 116 , and second side 112 of each metal seed 110 of the plurality of metal seeds 110 , but may not overlay the upper surface of the substrate 50 .
  • the gate conductor 150 formed from graphene may have a thickness of only one atom.
  • the gate conductor 150 formed from graphene may include bi-, tri-, or other multi-layer graphene.
  • the conductor material may be formed so as to form the depicted gate conductor 150 sidewalls and topwall and to overlay the upper surface of the substrate 50 .
  • the semiconductor device may be thereafter suitably processed to remove the conductor material overlying the substrate 50 , such as using photolithography, etching, or other known methods, to produce, at least, gate conductor 150 sidewalls overlying the first side 111 and second side 112 of each of the metal seeds 110 , but not on the upper surface of the substrate 50 positioned between the metal seeds 110 .
  • the present method further includes forming an insulator material upon each of the plurality of gate conductor 150 sidewalls to form a plurality of gate insulator 160 sidewalls.
  • the method may further include forming the insulator material upon a gate conductor 150 topwall or top side 116 of the metal seeds 110 .
  • the method may further include forming the insulator material upon a gate conductor 150 bottomwall positioned between the metal seeds 110 or upon an exposed substrate 50 surface positioned between the metal seeds 110 .
  • the insulator material may be conformally formed over the gate conductor 150 sidewalls and topwall and the remaining exposed substrate 50 surface.
  • the insulator material is formed upon each of the gate conductor 150 sidewalls and topwall and the remaining exposed substrate 50 surface.
  • Forming the insulator material upon the gate conductor 150 sidewalls may include forming a seed material directly upon the gate conductor 150 sidewalls before forming the insulator material upon the gate conductor 150 sidewalls.
  • the formed gate insulator 160 sidewalls may include both the seed material and the insulator material.
  • a first gate insulator 160 sidewall of the plurality of gate insulator 160 sidewalls is separated from a second gate insulator 160 sidewall of the plurality by a first trench 170 .
  • first trench width T is less than the first distance of width M ( FIG. 2 ) separating the metal seeds 110 .
  • the first trench width T is equal to the width M decreased by twice the thickness of the insulator material of the first gate insulator 160 and twice the thickness of the conductor material of the first gate conductor 150 .
  • the gate insulator 160 sidewalls, topwall, or bottomwall may be formed by any suitable technique, including, but not limited to, CVD, ALD, plasma-enhanced ALD, PVD, or other known methods.
  • the gate insulator 160 is formed by ALD.
  • the insulator material of the gate insulator 160 may be any suitable insulative material.
  • the gate insulator 160 may be formed from an oxide.
  • the present method may further include filling the first trenches 170 with a second insulator material 180 .
  • the second insulator material 180 may not only fill the first trenches 170 , but may also cover the gate insulator 160 topwall. Filling the first trenches 170 with the second insulator material 180 may be accomplished by any suitable method, including, without limitation, by spin coating, blanket coating, CVD, or other known methods.
  • the second insulator material 180 may be formed from any suitable insulative material.
  • the second gate insulator 160 may be formed from a conventional interlayer dielectric (“ILD”) material, such as silicon oxide or silicon nitride.
  • ILD interlayer dielectric
  • filling the trenches 170 with the second insulator material 180 may include filling only the trenches 170 with the second insulator material 180 , and not overlying the second insulator material 180 upon the top sides 116 of the metal seeds 110 , the topwall of the gate conductor 150 material, or the topwall of the gate insulator 160 material.
  • the method may further include, if necessary, removing portions of the second insulator material 180 , portions of the gate insulator 160 material, and portions of the gate conductor 150 material, to expose the top sides 116 of the metal seeds 110 .
  • This may be accomplished by any suitable method, including, without limitation, planarization methods such as abrasive planarization, chemical mechanical polishing or planarization (“CMP”) or an etching process.
  • planarization methods such as abrasive planarization, chemical mechanical polishing or planarization (“CMP”) or an etching process.
  • the method may further include removing the metal seeds 110 and filling the spaces once occupied by the metal seeds 110 with a material having a melting temperature greater than the metal temperature of the material forming the metal seeds 110 .
  • the re-filled material may be configured to withstand, without substantial deformation, higher fabrication temperatures than the metal seeds 110 could withstand.
  • the method may further include selectively removing segments of the second insulator material 180 to expose underlying sections of the substrate 50 .
  • the removed segments of second insulator material 180 may be spaced segments.
  • the removed segments define a plurality of cavities 200 in the second insulator material 180 .
  • the removal of the segments of second insulator material 180 may be accomplished by patterning in a direction orthogonal to the substrate 50 , such as by use of a photomask 190 that leaves exposed the top surface of ordered segments of second insulator material 180 .
  • Etching or any other suitable method may be used to remove the segments of second insulator material 180 in accordance with the photomask 190 pattern, as depicted in FIG. 8 , after which, the photomask 190 may be removed ( FIG. 9 ).
  • each cavity 200 is formed in a three-dimensional box shape, such that a first side 201 is parallel and opposite to a second side 202 of the cavity 200 , each of which is bordered and defined by a gate insulator 160 sidewall.
  • a third side 203 and fourth side 204 of each cavity 200 are also parallel and opposite one another, being bordered and defined by remaining second insulator material 180 .
  • a bottom side 205 of each cavity 200 may be bordered and defined by gate insulator 160 material, as shown in FIG. 8 .
  • the gate insulator 160 material may then be removed, as by etching or other known material-removal methods, and the gate insulator 160 material re-formed on the gate conductor 150 material. This intermediate process of removing and reforming the gate insulator 160 material may accommodate forming a gate insulator 160 material of optimal electrical quality in the resulting array 300 of vertical transistor devices.
  • the photomask 190 may be further utilized to remove the sections of the gate insulator 160 material overlaying the substrate 50 so as to expose those sections of the substrate 50 that were covered, as depicted in FIG. 9 , before the photomask 190 is removed. Thereafter, the bottom side 205 of each cavity 200 is bordered and defined by the exposed upper surface of the substrate 50 . The top side 206 of each cavity 200 remains open.
  • the present method for forming a semiconductor device further includes filling the cavities 200 with a channel material.
  • the channel material forms mesas 120 bordered, as shown in FIG. 1 , on a first side 121 by a first gate insulator 160 sidewall, bordered on a second side 122 by a second gate insulator 160 sidewall, and bordered on a third side 123 and fourth side 124 by remaining second insulator material 180 .
  • the mesas 120 of a column of VFET devices may be spaced apart by second insulator material 180 .
  • the channel material of the mesas 120 may be, without limitation, amorphous silicon, polycrystalline silicon, epitaxial-silicon, indium gallium zinc oxide (InGaZnOx) (“IGZO”), among others.
  • the channel material is IGZO.
  • each gate conductor 150 sidewall remains bordered by a gate insulator 160 sidewall and one of the metal seeds 110 .
  • the semiconductor device structure of the present disclosure may include a first metal seed 110 provided on a first gate conductor 150 sidewall and a second metal seed 110 provided on the second gate conductor 150 sidewall.
  • the present method may further include removing the metal seeds 110 .
  • Removing the metal seeds 110 may be accomplished with any suitable technique, such as etching. Removing the metal seeds 110 produces second trenches 210 positioned between a pair of oppositely-disposed gate conductor 150 sidewalls. Therefore, an array 300 of VFETs 100 is formed, each VFET device 100 having at least one gate conductor 150 .
  • a method for fabricating a semiconductor device structure comprises forming a plurality of metal seed materials upon a substrate, forming a conductor material upon each of the plurality of metal seed materials to form a plurality of gate conductors, forming an insulator material upon each of the plurality of gate conductors to form a plurality of gate insulators, and filling the first trench with a channel material to form a channel region.
  • a first gate insulator of the plurality of gate insulators is separated from a second gate insulator of the plurality of gate insulators by a first trench.
  • the disclosed array 300 of vertical transistor devices includes a first plurality of mesas 120 disposed on the substrate 50 .
  • the first plurality of mesas 120 may include the mesas 120 of a column of formed VFET devices 100 .
  • Each of the mesas 120 of the first plurality of mesas 120 has a first side 121 ( FIG. 1 ) and a second side 122 ( FIG. 1 ) opposite the first side 121 .
  • the first sides 121 of the mesas 120 within the first plurality of mesas 120 are aligned with one another, and the second sides 122 of the mesas 120 within the first plurality of mesas 120 are aligned with one another.
  • the array 300 further includes a first plurality of segments of insulator material, such as segments of remaining second insulator material 180 , each of the segments of insulator material 180 separating one of the mesas 120 from another mesa 120 within the first plurality of mesas 120 .
  • the array 300 further includes a gate insulator 160 sidewall provided along the first sides 121 of the mesas 120 of the first plurality of mesas 120 .
  • a gate conductor 150 sidewall is provided along the gate insulator 160 sidewall.
  • the gate conductor 150 may include graphene in one or more layers.
  • a single gate insulator 160 sidewall and single gate conductor 150 sidewall are components of a single gate 140 extending along the entirety of a column of mesas 120 of VFET devices 100 , on the first sides 121 of the mesas 120 .
  • a series of separated gates 140 may extend along the first side 121 of the mesas 120 of a column of mesas 120 of VFET devices 100 .
  • the array 300 may further include, as depicted in FIG. 11 , a second gate insulator 160 sidewall provided along the second sides 122 of the mesas 120 of the first plurality of semiconductor mesas 120 .
  • the array 300 may further include a second gate conductor 150 sidewall provided along the second gate insulator 160 sidewall.
  • the second gate conductor 150 may include graphene in one or more layers.
  • a single gate insulator 160 sidewall and single gate conductor 150 sidewall are components of a single gate 140 extending along the entirety of a column of mesas 120 of VFET devices 100 , on the second sides 122 of the mesas 120 .
  • a series of separated gated 140 may extend along the second side 122 of the mesas 120 of a column of mesas 120 of VFET devices 100 .
  • the mesas 120 within the VFET devices 100 of the array 300 may define channel regions 130 ( FIG. 1 ) passing between the first side 121 and second side 122 of the mesa 120 .
  • the channel region 130 may be in communication with a source region (not shown) and drain region (not shown).
  • the source and drain regions may be formed by any suitable technique known in the art.
  • the array 300 of vertical transistor devices 100 may further include one or more additional pluralities of mesas 120 with the same array 300 as the first plurality of mesas 120 .
  • the pluralities of mesas 120 may be spaced from one another, evenly and in parallel, by second trenches 210 .
  • Each column of the array 300 has a width defined by the exterior surfaces of a pair of gate conductor 150 sidewalls, which width C may be the width of each individual VFET device 100 .
  • Width C of each VFET device 100 is equal to or about equal to width M ( FIG. 2 ) of the trench separating the originally-formed metal seeds 110 . Therefore, the final width C of the VFET device 100 may be scalable by adjusting the width M of the formed metal seeds 110 .
  • the metal seeds 110 are formed at pitch, where “pitch” is known in the industry to refer to the distance between identical points in neighboring features. Notably, the pitch of the metal seeds 110 is equal to or essentially equal to the resulting pitch of the formed VFET devices 100 .
  • An array of vertical transistor devices comprises a first plurality of mesas extending above a substrate, a first plurality of segments of insulator material, first gate insulators along the first sides of the mesas of the first plurality of mesas, and first gate conductors along the first gate insulators, the first gate conductors comprising graphene.
  • Each mesa of the first plurality of mesas has a first side and a second side opposite the first side, the first sides aligned with one another, and the second sides aligned with one another.
  • Each segment of insulator material separates one of the mesas from another mesa within the first plurality of mesas.
  • a method for fabricating an array of vertical transistor devices comprises forming a plurality of metal seeds upon a substrate, forming a conductor material upon each of the plurality of metal seeds to form a plurality of gate conductors, forming a first insulator material upon each of the plurality of gate conductors to form a plurality of gate insulators, filling the first trench with a second insulator material, removing segments of the second insulator material to expose underlying sections of the substrate and to define a plurality of cavities, and filling the plurality of cavities with a channel material to form channel regions bordered on a first side by the first gate insulators and bordered on a second side by the second gate insulators.
  • a first gate insulator of the plurality of gate insulators is separated from a second gate insulator of the plurality of gate insulators by a first trench.
  • the formed VFET device 100 and array 300 may be thereafter subjected to additional processing to form top contacts, metal interconnects, additional stacked layers of VFET 100 arrays 300 , and the like, the result of which may be the formation of a cross-point memory array.
  • the additional processing may be conducted by conventional techniques, which are not described in detail herein.
  • an array of vertical transistor devices 100 wherein the gate conductor 150 sidewalls are further provided along a vertical side of a metal seed line 110 .
  • the gate conductor 150 sidewalls of the array 300 of VFET devices 100 may be provided along the first side 111 and/or second side 112 of metal seeds 110 .
  • FIGS. 12-21 depict various stages of processing a plurality of vertical transistors in accordance with another embodiment of the present method for fabricating a semiconductor device, such as a VFET 100 device, as well as for fabricating an array 300 of vertical transistor devices 100 .
  • FIGS. 12 and 13 depict identical stages of processing as those depicted in FIGS. 2 and 3 , respectively.
  • the description of FIG. 12 is equivalent to the description of FIG. 2
  • the description of FIG. 13 is equivalent to the description of FIG. 3 .
  • the present embodiment of the method for forming a semiconductor device includes, following forming a conductor material upon the metal seeds 110 so as to form a gate conductor 150 , forming an insulator material upon each of the plurality of gate conductor 150 sidewalls to faun a plurality of gate insulator 160 sidewalls.
  • the method of the present embodiment further includes forming the insulator material upon a gate conductor 150 topwall or top side 116 of the metal seeds 110 .
  • the insulator material may be formed conformally.
  • the formed gate insulator 160 sidewalls may be evenly spaced from one another, such that each first trench 170 , defined between opposing gate insulator 160 sidewalls, defines a width T ( FIG. 14 ).
  • the method of the present embodiment includes leaving portions of the substrate 50 located within the first trenches 170 exposed. Leaving the portions of the substrate 50 within the first trenches 170 exposed may be accomplished by forming the insulator material only upon the first side 111 , second side 112 , and/or top side 116 of the metal seeds 110 , but not upon the substrate 50 within the first trenches 170 .
  • Leaving the portions of the substrate 50 within the first trenches 170 exposed may alternatively be accomplished by forming the insulator material upon the first side 111 , second side 112 , and top side 116 of the metal seeds 110 and also upon the substrate 50 within the first trenches 170 , followed by removal of the gate insulator 160 bottomwall (i.e., the insulator material covering the substrate 50 within the first trenches 170 ).
  • the removal of the insulator material may be accomplished by any suitable technique, including etching.
  • the insulator material of the gate insulator 160 sidewalls may be formed by any suitable technique, including, but not limited to, ALD, plasma-enhanced ALD, PVD, or other known methods.
  • the insulator material of the gate insulator 160 may comprise any suitable insulative material.
  • the material of the gate insulator 160 may be an oxide.
  • the present embodiment of the method may further include filling the first trench 170 ( FIG. 14 ) with a second insulator material 180 .
  • the second insulator material 180 may not only fill the first trenches 170 , covering the exposed substrate 50 , but may also cover the gate insulator 160 top wall. Filling the first trenches 170 with the second insulator material 180 may be accomplished by any suitable method, including, without limitation, by spin coating, blanket coating, CVD, PVD, in situ growth, or other known methods.
  • the second insulator material 180 may be any suitable insulative material.
  • the second insulator material 180 may be a conventional ILD material, such as silicon nitride.
  • the present embodiment of the method may further include, if necessary, removing portions of the second insulator material 180 , portions of the gate insulator 160 material, and portions of the gate conductor 150 material, to expose the top sides 116 of the metal seeds 110 .
  • This may be accomplished by any suitable method, including, without limitation, abrasive planarization methods such as chemical mechanical polishing or planarization (“CMP”) or an etching process.
  • CMP chemical mechanical polishing or planarization
  • the present embodiment of the method may further include selectively removing segments of the second insulator material 180 to expose sections of the substrate 50 underlying the segments of second insulator material 180 removed. This may be accomplished as described above with reference to FIGS. 7 through 9 .
  • the bottom side 205 of each cavity 200 is bordered by and defined by an exposed upper surface of the substrate 50 .
  • the top side 206 of each cavity 200 remains open.
  • FIGS. 20 and 21 depict identical stages of processing as those depicted in FIGS. 10 and 11 , respectively.
  • the description of FIG. 20 is equivalent to the description of FIG. 10
  • the description of FIG. 21 is equivalent to the description of FIG. 11 .
  • the formed VFET device 100 ( FIG. 1 ) and array 300 , depicted in FIG. 21 may be thereafter subjected to additional processing to form top contacts, metal interconnects, additional stacked layers of arrays 300 of VFET devices 100 , and the like, the result of which may be the formation of a cross-point memory array.
  • the additional processing may be conducted by conventional techniques, which are not described in detail herein.
  • the VFET device 100 and array 300 may be used in a memory access device (not shown) that includes a memory cell (not shown) electrically coupled to the VFET device 100 .
  • the memory cell includes a top electrode (not shown) and a bottom electrode (not shown), which is coupled to a contact (not shown) for the drain.
  • the source is coupled to another contact.
  • the VFET device 100 is turned “on” and current flows through the channel region 130 and memory cell.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.

Description

TECHNICAL FIELD
The invention, in various embodiments, relates generally to the field of integrated circuit design and fabrication. More particularly, this disclosure relates to vertically-oriented transistors and methods for fabricating the transistors.
BACKGROUND
Fabricating a semiconductor device, such as a transistor, upon a substrate necessarily leads to occupation of a certain surface area of the substrate by the footprint of the device. Often, the available surface area of a given substrate is limited, and maximizing the use of the substrate requires maximizing the density of devices fabricated on the substrate. Minimizing the dimensions of components of a device, such as a transistor, accommodates minimizing the overall footprint of the device and maximizing of the device density. This accommodates formation of a greater number of devices on a given substrate.
Transistors are often constructed upon the primary surface of the substrate. The primary surface is generally the uppermost, exterior surface of the substrate. The primary surface of the substrate is considered to define a horizontal plane and direction.
Field effect transistor (“FET”) structures, which include a channel region between a pair of source/drain regions and a gate configured to electrically connect the source/drain regions to one another through the channel region, can be divided amongst two broad categories based on the orientations of the channel regions relative to the primary surface of the substrate. Transistor structures that have channel regions that are primarily parallel to the primary surface of the substrate are referred to as planar FET structures, and those having channel regions that are generally perpendicular to the primary surface of the substrate are referred to as vertical FET (“VFET”) transistor structures. Because current flow between the source and drain regions of a transistor device occurs through the channel region, planar FET devices can be distinguished from VFET devices based upon both the direction of current flow as well as on the general orientation of the channel region. VFET devices are devices in which the current flow between the source and drain regions of the device is primarily substantially orthogonal to the primary surface of the substrate. Planar FET devices are devices in which the current flow between source and drain regions is primarily parallel to the primary surface of the substrate.
A VFET device includes a vertical, so-called “mesa,” also referred to in the art as a so-called “fin,” that extends upward from the underlying substrate. This mesa forms part of the transistor body. Generally, a source region and a drain region are located at the ends of the mesa while one or more gates are located on one or more surfaces of the mesa or fin. Upon activation, current flows through the channel region within the mesa.
VFETs are generally thinner in width (i.e., in the dimension in a plane parallel to the horizontal plane defined by the primary surface of the substrate) than planar FETs. Therefore, vertical transistors are conducive to accommodating increased device packing density and are conducive for inclusion within a cross-point memory array. In such an array, multiple VFETs are ordered in stacked rows and columns. However, even with this arrangement, the packing density is at least partially limited by the minimal dimensions of the components of the vertical transistor, including the gate and channel components.
Scaling or otherwise reducing the dimensions of transistor components depends, at least in part, on the limitations of conventional semiconductor fabrication techniques, physical limitations of materials used in the fabrication, and minimal properties required for fabricating an operational device. For example, to form a typical gate metal having the properties to achieve the necessary level of low electrical resistance, a gate thickness of greater than 5 nanometers is generally required. Using a gate metal of 5 nm thickness in a VFET device having a surround gate, the total width of the device must take into account twice the width of the gate material. Therefore, a typical VFET surround gate will have at least 10 nanometers of the VFET device's width consumed by the gate conductor.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional, top and front perspective, schematic view of a vertical field effect transistor of an embodiment of the present disclosure;
FIGS. 2-11 are cross-sectional, top and front perspective, schematic views of a semiconductor device structure during various stages of processing according to an embodiment of the present disclosure; and
FIGS. 12-21 are cross-sectional, top and front perspective, schematic views of a semiconductor device structure during various stages of processing according to another embodiment of the present disclosure.
 DETAILED DESCRIPTION
A semiconductor device structure, an array of vertical transistor devices, and methods for fabricating such structures or devices are disclosed. The vertical transistor device and array of VFETs all include thin gate conductors, making the present VFET structure and method conducive in high-device-density integrated circuit designs, including cross-point memory arrays.
As used herein, the term “substrate” means and includes a base material or construction upon which materials, such as vertical field effect transistors, are formed. The substrate may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate comprising a layer of semiconductive material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates, such as silicon-on-sapphire (“SOS”) substrates or silicon-on-glass (“SOG”) substrates, epitaxial layers of silicon on a base semiconductor foundation or other semiconductor or optoelectronic materials, such as silicon-germanium (Si1-xGex), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP). Furthermore, when reference is made to a “wafer” or “substrate” in the following description, previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation.
As used herein, the term “graphene” means and includes a poly-cyclic aromatic molecule having a plurality of carbon atoms that are connected to each other by covalent bonds. The plurality of carbon atoms may form a plurality of six-member rings, which function as a standard repeating unit, and may further include a five-membered ring and/or a seven-membered ring. The graphene may be a one atom thick material of the six-member rings in which the carbon atoms are covalently bonded and have sp2 hybridization. The graphene may include the monolayer of graphene. Alternatively, the graphene may include multiple monolayers of graphene stacked upon one another. In this regard, the graphene may have a maximum thickness of about 5 nanometers. If multiple monolayers of graphene are used, the graphene may be used as a gate in a semiconductor device structure. If a one atom thick material is used, the graphene may be used as a switchable material.
As used herein, while the terms “first,” “second,” “third,” etc., may describe various elements, components, regions, layers, and/or sections, none of which are limited by these terms. These terms are used only to distinguish one element, component, region, material, layer, or section from another element, component, region, material, layer, or section. Thus, “a first element,” “a first component,” “a first region,” “a first material,” “a first layer,” or “a first section” discussed below could be termed a second element, a second component, a second region, a second material, a second layer, or second section without departing from the teachings herein.
As used herein, spatially relative terms, such as “beneath,” “below,” “lower,” “bottom,” “above,” “upper,” “top,” “front,” “rear,” “left,” “right,” and the like, may be used for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Unless otherwise specified, the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” or “under” or “on bottom of” other elements or features would then be oriented “above” or “on top of” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below, depending on the context in which the tern is used, which will be evident to one of ordinary skill in the art. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, reference to an element as being “on” another element means and includes the element being directly on top of, adjacent to, underneath, or in direct contact with the other element. It also includes the element being indirectly on top of, adjacent to, underneath, or near the other element, with other elements present therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
As used herein, the terms “comprises,” “comprising,” “includes,” and/or “including” specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
As used herein, “and/or” includes any and all combinations of one or more of the associated listed items.
As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
The illustrations presented herein are not meant to be actual views of any particular component, structure, device, or system, but are merely idealized representations that are employed to describe embodiments of the present disclosure.
Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments described herein should not be construed as limited to the particular shapes or regions as illustrated but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as box shaped may, typically, have rough and/or nonlinear features. Moreover, sharp angles that are illustrated may be rounded. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the present claims.
The following description provides specific details, such as material types, material thicknesses, and processing conditions in order to provide a thorough description of embodiments of the disclosed devices and methods. However, a person of ordinary skill in the art will understand that the embodiments of the devices and methods may be practiced without employing these specific details. Indeed, the embodiments of the devices and methods may be practiced in conjunction with conventional semiconductor fabrication techniques employed in the industry.
The fabrication processes described herein do not form a complete process flow for processing semiconductor device structures. The remainder of the process flow is known to those of ordinary skill in the art. Accordingly, only the methods and semiconductor device structures necessary to understand embodiments of the present devices and methods are described herein.
Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma enhanced ALD, and physical vapor deposition (“PVD”). Alternatively, the materials may be grown in situ. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art.
Unless the context indicates otherwise, the removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching, abrasive planarization, or other known material-removal methods.
Reference will now be made to the drawings, where like numerals refer to like components throughout. The drawings are not necessarily drawn to scale.
FIG. 1 is a cross-sectional, front and top perspective view of a schematic of a VFET 100 semiconductor device having a structure of the present disclosure. The VFET 100 includes a mesa 120 extending above a substrate 50 such that a bottom side 125 of the mesa 120 sits on a horizontally planar upper surface of the substrate 50. The mesa 120 extends above the substrate 50 in a direction perpendicular to the substrate 50. The mesa 120 has a first side 121 and a second side 122 that is opposite and substantially parallel to the first side 121. A channel region 130 passes through the mesa 120 between the first side 121 and the second side 122. In use and operation, the channel region 130 is configured to allow current to flow between a source region (not shown) and a drain region (not shown). A top side 126 of the mesa 120 may be in operable communication with an electrode (not shown) or interconnect (not shown).
A first gate 140 is provided on the first side 121 of the mesa 120. The first gate 140 is operative to control current flow in the channel region 130. A second gate 140 may be provided on the second side 122 of the mesa 120, as well, the second gate 140 being operative to control, in conjunction with the first gate 140, current flow in the channel region 130 of the mesa 120.
Each gate 140 includes a gate insulator 160 and an overlying gate conductor 150. The gate insulator 160 may be provided directly on the first and/or second sides 121, 122 of the mesa 120. The gate conductor 150 may be provided directly on the gate insulator 160 and may surround the vertical sides of the mesa 120, i.e., may surround the first side 121, the second side 122, a third side 123, and a fourth side 124 of the mesa 120. In such embodiments, the third side 123 and fourth side 124 may be opposite and parallel one another and arranged perpendicularly to the first side 121 and the second side 122.
In other embodiments of the present VFET 100 structure, the gate 140 is provided only on the first side 121 of the mesa 120. In still other embodiments, the gate 140 is provided only on the first side 121 and second side 122 of the mesa 120, but not on the third side 123 or the fourth side 124.
According to the embodiment of the present VFET 100 structure depicted in FIG. 1, the gate conductor 150 of the sidewall gate structure 140 substantially overlies the entire exterior surface of the gate insulator 160 (i.e., the surface of the gate insulator 160 that is opposite and substantially parallel to the surface of the gate insulator 160 that is proximate to the mesa 120). In other embodiments of the VFET 100 structure, the gate conductor 150 of the gate 140 overlies only a portion of the exterior surface of the gate insulator 160. In some such embodiments, the gate conductor 150 is structured as a ring-gate conductor.
The gate conductor 150 of the present VFET 100 is a gate conductor, defining a gate conductor thickness G (i.e., the dimension of the shortest side of the gate conductor 150, when such gate conductor 150 is construed as having a three-dimensional box shape) of less than or equal to about 5 nanometers. Therefore, according to the depicted VFET 100 having a pair of gates 140, the thickness of the gate conductor 150 contributes twice the thickness G of the gate conductor 150 to the overall width C of one formed VFET cell (FIG. 11 and FIG. 21). The thickness G of the gate conductor 150 may be less than the thickness I of the gate insulator 160, which is defined by the dimension of the shortest side of the gate insulator 160, when such gate insulator 160 is construed as having a three-dimensional box shape.
The gate conductor 150 may be formed from graphene, or at least a portion of the gate conductor 150 may include graphene. Graphene exhibits high electrical conductivity and has a single atom body thickness. Therefore, graphene possesses great potential for high-speed electronics. Generally, graphene is a one-atom thick planar sheet of sp2-bonded carbon atoms that are densely packed in a honeycomb lattice such that the carbon atoms of graphene sheets are connected to each other in an extended array of hexagonal rings. Individual graphene sheets may be stacked. Therefore, the gate conductor 150 may include a plurality of layers of graphene. If multiple monolayers of graphene are used, the graphene may be used as the gate conductor 150. If a one atom thick material is used, the graphene may be used as a switchable material in the semiconductor device.
A semiconductor device structure including the vertical transistor devices comprises a mesa extending above a substrate and a first gate on the first side of the mesa is disclosed. The mesa comprises a channel region between a first side and a second side of the mesa. The first gate comprises a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator.
FIGS. 2-11 depict various stages of processing of a plurality of vertical transistors in accordance with embodiments of the present method for fabricating a semiconductor device, such as a VFET 100 device, as well as for fabricating an array 300 (FIG. 10) of vertical transistor devices 100. With particular reference to FIG. 2, the present method includes forming a plurality of metal seeds 110 upon a substrate 50. The metal seeds 110 are spaced from one another and arranged in parallel. The metal seeds 110 may be formed at pitch. Each metal seed 110 includes a first side 111, second side 112, bottom side 115, and top side 116. According to the depiction in FIG. 2, the metal seeds 110 are positioned such that the bottom side 115 of each metal seed 110 is adjacent to the substrate 50, and the top side 116 of each metal seed 110 is opposite the bottom side 115 and directed upward from substrate 50. The first side 111 of one metal seed 110 is positioned opposite and parallel to the second side 112 of a neighboring metal seed 110. The metal seeds 110 may be evenly spaced from one another, arranged in parallel, such that each metal seed 110 is separated from each adjacent and parallel metal seed 110 by a trench having a width M equal to a first distance. In other embodiments, the metal seeds 110 may be spaced unevenly from one another such that one metal seed 110 is spaced further from a first neighboring metal seed 110 than it is spaced from a second neighboring metal seed 110. In still other embodiments, the metal seeds 110 may be spaced unevenly such that one metal seed 110 is spaced further from a neighboring metal seed 110 at a first end than it is spaced from the neighboring metal seed 110 at a second end.
The material of the metal seed 110 may be any metal conducive for forming a gate conductor 150, such as a gate conductor of graphene, thereupon. For example, without limitation, copper, nickel, iridium, ruthenium, combinations thereof, and solid mixtures containing any or all of these metals may be used as the material of the metal seed 110. As a more particular example, the metal seed 110 may be formed from copper, such as polycrystalline copper.
With reference to FIG. 3, the method for fabricating a semiconductor device, such as a VFET device 100, or VFET array 300, further includes forming a conductor material upon each of the plurality of metal seeds 110 to form a gate conductor 150, including gate conductor sidewalls aligning each of the first sides 111 and second sides 112 of the metal seeds 110. The conductor material may be formed conformally over the first side 111, second side 112, and top side 116 of the metal seeds 110. The conductor material of the gate conductors 150 may be formed by any suitable technique, including, but not limited to, CVD, ALD, plasma-enhanced ALD, or other known methods. Portions of the conductor material overlying an upper surface of the substrate 50, if any, may be removed by conventional techniques, exposing the substrate 50.
The conductor material of the gate conductor 150 may be formed of graphene. Various methods of forming graphene are known. U.S. Pat. No. 7,071,258, which issued Jul. 4, 2006, to Jang et al.; U.S. Pat. No. 7,015,142, which issued Mar. 21, 2006, to DeHeer et al.; U.S. Pat. No. 6,869,581, which issued Mar. 22, 2005, to Kishi et al.; U.S. Patent Application Publication No. 2011/0123776, which published May 26, 2011, for Shin et al.; and U.S. Patent Application Publication No. 2006/0099750, which published May 11, 2006, for DeHeer et al. describe various methods of forming graphene. Any such suitable technique may be used to form the gate conductor 150 from graphene on the metal seeds 110. For example, without limitation, in some embodiments, graphene may be formed using ALD, CVD, or other known methods.
In such embodiments, the graphene may be formed directly upon the exterior surface of the metal seeds 110. According to the depiction of FIG. 3, the conductor material may overlay at least the first side 111, top side 116, and second side 112 of each metal seed 110 of the plurality of metal seeds 110, but may not overlay the upper surface of the substrate 50. Regardless of how formed, the gate conductor 150 formed from graphene may have a thickness of only one atom. Alternatively, the gate conductor 150 formed from graphene may include bi-, tri-, or other multi-layer graphene.
In other embodiments of the disclosed method, the conductor material may be formed so as to form the depicted gate conductor 150 sidewalls and topwall and to overlay the upper surface of the substrate 50. The semiconductor device may be thereafter suitably processed to remove the conductor material overlying the substrate 50, such as using photolithography, etching, or other known methods, to produce, at least, gate conductor 150 sidewalls overlying the first side 111 and second side 112 of each of the metal seeds 110, but not on the upper surface of the substrate 50 positioned between the metal seeds 110.
With reference to FIG. 4, the present method further includes forming an insulator material upon each of the plurality of gate conductor 150 sidewalls to form a plurality of gate insulator 160 sidewalls. The method may further include forming the insulator material upon a gate conductor 150 topwall or top side 116 of the metal seeds 110. The method may further include forming the insulator material upon a gate conductor 150 bottomwall positioned between the metal seeds 110 or upon an exposed substrate 50 surface positioned between the metal seeds 110. The insulator material may be conformally formed over the gate conductor 150 sidewalls and topwall and the remaining exposed substrate 50 surface. Thus, according to the depiction in FIG. 4, the insulator material is formed upon each of the gate conductor 150 sidewalls and topwall and the remaining exposed substrate 50 surface. Forming the insulator material upon the gate conductor 150 sidewalls may include forming a seed material directly upon the gate conductor 150 sidewalls before forming the insulator material upon the gate conductor 150 sidewalls. As such, the formed gate insulator 160 sidewalls may include both the seed material and the insulator material. As formed, a first gate insulator 160 sidewall of the plurality of gate insulator 160 sidewalls is separated from a second gate insulator 160 sidewall of the plurality by a first trench 170. Because the metal seeds 110 may be evenly spaced in parallel from one another, the formed gate insulator 160 sidewalls may be evenly spaced from one another, such that each first trench 170 defines a first trench width T. First trench width T is less than the first distance of width M (FIG. 2) separating the metal seeds 110. The first trench width T is equal to the width M decreased by twice the thickness of the insulator material of the first gate insulator 160 and twice the thickness of the conductor material of the first gate conductor 150.
The gate insulator 160 sidewalls, topwall, or bottomwall may be formed by any suitable technique, including, but not limited to, CVD, ALD, plasma-enhanced ALD, PVD, or other known methods. In one embodiment, the gate insulator 160 is formed by ALD. The insulator material of the gate insulator 160 may be any suitable insulative material. For example, without limitation, the gate insulator 160 may be formed from an oxide.
With reference to FIG. 5, the present method may further include filling the first trenches 170 with a second insulator material 180. The second insulator material 180 may not only fill the first trenches 170, but may also cover the gate insulator 160 topwall. Filling the first trenches 170 with the second insulator material 180 may be accomplished by any suitable method, including, without limitation, by spin coating, blanket coating, CVD, or other known methods. The second insulator material 180 may be formed from any suitable insulative material. For example, without limitation, the second gate insulator 160 may be formed from a conventional interlayer dielectric (“ILD”) material, such as silicon oxide or silicon nitride.
In other embodiments of the disclosed method, filling the trenches 170 with the second insulator material 180 may include filling only the trenches 170 with the second insulator material 180, and not overlying the second insulator material 180 upon the top sides 116 of the metal seeds 110, the topwall of the gate conductor 150 material, or the topwall of the gate insulator 160 material.
With reference to FIG. 6, the method may further include, if necessary, removing portions of the second insulator material 180, portions of the gate insulator 160 material, and portions of the gate conductor 150 material, to expose the top sides 116 of the metal seeds 110. This may be accomplished by any suitable method, including, without limitation, planarization methods such as abrasive planarization, chemical mechanical polishing or planarization (“CMP”) or an etching process.
The method may further include removing the metal seeds 110 and filling the spaces once occupied by the metal seeds 110 with a material having a melting temperature greater than the metal temperature of the material forming the metal seeds 110. As such, the re-filled material may be configured to withstand, without substantial deformation, higher fabrication temperatures than the metal seeds 110 could withstand.
With reference to FIGS. 7 through 9, the method may further include selectively removing segments of the second insulator material 180 to expose underlying sections of the substrate 50. The removed segments of second insulator material 180 may be spaced segments. The removed segments define a plurality of cavities 200 in the second insulator material 180. The removal of the segments of second insulator material 180 may be accomplished by patterning in a direction orthogonal to the substrate 50, such as by use of a photomask 190 that leaves exposed the top surface of ordered segments of second insulator material 180. Etching or any other suitable method may be used to remove the segments of second insulator material 180 in accordance with the photomask 190 pattern, as depicted in FIG. 8, after which, the photomask 190 may be removed (FIG. 9).
According to the depicted method, each cavity 200 is formed in a three-dimensional box shape, such that a first side 201 is parallel and opposite to a second side 202 of the cavity 200, each of which is bordered and defined by a gate insulator 160 sidewall. A third side 203 and fourth side 204 of each cavity 200 are also parallel and opposite one another, being bordered and defined by remaining second insulator material 180.
Where the method, in forming gate insulator 160 material results in gate insulator 160 bottomwalls formed upon the substrate 50, a bottom side 205 of each cavity 200 may be bordered and defined by gate insulator 160 material, as shown in FIG. 8. In some embodiments, the gate insulator 160 material may then be removed, as by etching or other known material-removal methods, and the gate insulator 160 material re-formed on the gate conductor 150 material. This intermediate process of removing and reforming the gate insulator 160 material may accommodate forming a gate insulator 160 material of optimal electrical quality in the resulting array 300 of vertical transistor devices.
The photomask 190 may be further utilized to remove the sections of the gate insulator 160 material overlaying the substrate 50 so as to expose those sections of the substrate 50 that were covered, as depicted in FIG. 9, before the photomask 190 is removed. Thereafter, the bottom side 205 of each cavity 200 is bordered and defined by the exposed upper surface of the substrate 50. The top side 206 of each cavity 200 remains open.
With reference to FIG. 10, the present method for forming a semiconductor device, such as a VFET device 100 or an array of VFETs 300, further includes filling the cavities 200 with a channel material. The channel material forms mesas 120 bordered, as shown in FIG. 1, on a first side 121 by a first gate insulator 160 sidewall, bordered on a second side 122 by a second gate insulator 160 sidewall, and bordered on a third side 123 and fourth side 124 by remaining second insulator material 180. The mesas 120 of a column of VFET devices may be spaced apart by second insulator material 180.
Filling the cavities 200 with the channel material to form the mesas 120 may be accomplished with any suitable technique, including, without limitation, spin coating, blanket coating, CVD, ALD, plasma-enhanced ALD, PVD, in situ growth, or other known methods. The channel material of the mesas 120 may be, without limitation, amorphous silicon, polycrystalline silicon, epitaxial-silicon, indium gallium zinc oxide (InGaZnOx) (“IGZO”), among others. In one embodiment, the channel material is IGZO.
As depicted in FIG. 10, following the filling of the cavities 200 with the channel material to form the mesas 120, each gate conductor 150 sidewall remains bordered by a gate insulator 160 sidewall and one of the metal seeds 110. The semiconductor device structure of the present disclosure, therefore, may include a first metal seed 110 provided on a first gate conductor 150 sidewall and a second metal seed 110 provided on the second gate conductor 150 sidewall.
As depicted in FIG. 11, the present method may further include removing the metal seeds 110. Removing the metal seeds 110 may be accomplished with any suitable technique, such as etching. Removing the metal seeds 110 produces second trenches 210 positioned between a pair of oppositely-disposed gate conductor 150 sidewalls. Therefore, an array 300 of VFETs 100 is formed, each VFET device 100 having at least one gate conductor 150.
A method for fabricating a semiconductor device structure is also disclosed. The method comprises forming a plurality of metal seed materials upon a substrate, forming a conductor material upon each of the plurality of metal seed materials to form a plurality of gate conductors, forming an insulator material upon each of the plurality of gate conductors to form a plurality of gate insulators, and filling the first trench with a channel material to form a channel region. A first gate insulator of the plurality of gate insulators is separated from a second gate insulator of the plurality of gate insulators by a first trench.
With further regard to FIG. 11, the disclosed array 300 of vertical transistor devices includes a first plurality of mesas 120 disposed on the substrate 50. The first plurality of mesas 120 may include the mesas 120 of a column of formed VFET devices 100. Each of the mesas 120 of the first plurality of mesas 120 has a first side 121 (FIG. 1) and a second side 122 (FIG. 1) opposite the first side 121. The first sides 121 of the mesas 120 within the first plurality of mesas 120 are aligned with one another, and the second sides 122 of the mesas 120 within the first plurality of mesas 120 are aligned with one another.
The array 300 further includes a first plurality of segments of insulator material, such as segments of remaining second insulator material 180, each of the segments of insulator material 180 separating one of the mesas 120 from another mesa 120 within the first plurality of mesas 120.
The array 300 further includes a gate insulator 160 sidewall provided along the first sides 121 of the mesas 120 of the first plurality of mesas 120. A gate conductor 150 sidewall is provided along the gate insulator 160 sidewall. The gate conductor 150 may include graphene in one or more layers. According to the array 300 of vertical transistor devices 100 depicted in FIG. 11, a single gate insulator 160 sidewall and single gate conductor 150 sidewall are components of a single gate 140 extending along the entirety of a column of mesas 120 of VFET devices 100, on the first sides 121 of the mesas 120. Alternatively, a series of separated gates 140 may extend along the first side 121 of the mesas 120 of a column of mesas 120 of VFET devices 100.
The array 300 may further include, as depicted in FIG. 11, a second gate insulator 160 sidewall provided along the second sides 122 of the mesas 120 of the first plurality of semiconductor mesas 120. The array 300 may further include a second gate conductor 150 sidewall provided along the second gate insulator 160 sidewall. The second gate conductor 150 may include graphene in one or more layers. According to the array 300 of vertical transistor devices 100 (FIG. 1) depicted in FIG. 11, a single gate insulator 160 sidewall and single gate conductor 150 sidewall are components of a single gate 140 extending along the entirety of a column of mesas 120 of VFET devices 100, on the second sides 122 of the mesas 120. Alternatively, a series of separated gated 140 may extend along the second side 122 of the mesas 120 of a column of mesas 120 of VFET devices 100.
The mesas 120 within the VFET devices 100 of the array 300 may define channel regions 130 (FIG. 1) passing between the first side 121 and second side 122 of the mesa 120. The channel region 130 may be in communication with a source region (not shown) and drain region (not shown). The source and drain regions may be formed by any suitable technique known in the art.
The array 300 of vertical transistor devices 100 may further include one or more additional pluralities of mesas 120 with the same array 300 as the first plurality of mesas 120. The pluralities of mesas 120 may be spaced from one another, evenly and in parallel, by second trenches 210.
Each column of the array 300 has a width defined by the exterior surfaces of a pair of gate conductor 150 sidewalls, which width C may be the width of each individual VFET device 100. Width C of each VFET device 100 is equal to or about equal to width M (FIG. 2) of the trench separating the originally-formed metal seeds 110. Therefore, the final width C of the VFET device 100 may be scalable by adjusting the width M of the formed metal seeds 110. In addition, the metal seeds 110 are formed at pitch, where “pitch” is known in the industry to refer to the distance between identical points in neighboring features. Notably, the pitch of the metal seeds 110 is equal to or essentially equal to the resulting pitch of the formed VFET devices 100.
An array of vertical transistor devices is disclosed. The array comprises a first plurality of mesas extending above a substrate, a first plurality of segments of insulator material, first gate insulators along the first sides of the mesas of the first plurality of mesas, and first gate conductors along the first gate insulators, the first gate conductors comprising graphene. Each mesa of the first plurality of mesas has a first side and a second side opposite the first side, the first sides aligned with one another, and the second sides aligned with one another. Each segment of insulator material separates one of the mesas from another mesa within the first plurality of mesas.
A method for fabricating an array of vertical transistor devices is also disclosed. The method comprises forming a plurality of metal seeds upon a substrate, forming a conductor material upon each of the plurality of metal seeds to form a plurality of gate conductors, forming a first insulator material upon each of the plurality of gate conductors to form a plurality of gate insulators, filling the first trench with a second insulator material, removing segments of the second insulator material to expose underlying sections of the substrate and to define a plurality of cavities, and filling the plurality of cavities with a channel material to form channel regions bordered on a first side by the first gate insulators and bordered on a second side by the second gate insulators. A first gate insulator of the plurality of gate insulators is separated from a second gate insulator of the plurality of gate insulators by a first trench.
It will be understood that the formed VFET device 100 and array 300 may be thereafter subjected to additional processing to form top contacts, metal interconnects, additional stacked layers of VFET 100 arrays 300, and the like, the result of which may be the formation of a cross-point memory array. The additional processing may be conducted by conventional techniques, which are not described in detail herein.
With reference back to FIG. 10, also disclosed is an array of vertical transistor devices 100, wherein the gate conductor 150 sidewalls are further provided along a vertical side of a metal seed line 110. For example, without limitation, the gate conductor 150 sidewalls of the array 300 of VFET devices 100 may be provided along the first side 111 and/or second side 112 of metal seeds 110.
FIGS. 12-21 depict various stages of processing a plurality of vertical transistors in accordance with another embodiment of the present method for fabricating a semiconductor device, such as a VFET 100 device, as well as for fabricating an array 300 of vertical transistor devices 100. FIGS. 12 and 13 depict identical stages of processing as those depicted in FIGS. 2 and 3, respectively. The description of FIG. 12 is equivalent to the description of FIG. 2, and the description of FIG. 13 is equivalent to the description of FIG. 3.
With reference to FIG. 14, the present embodiment of the method for forming a semiconductor device includes, following forming a conductor material upon the metal seeds 110 so as to form a gate conductor 150, forming an insulator material upon each of the plurality of gate conductor 150 sidewalls to faun a plurality of gate insulator 160 sidewalls. The method of the present embodiment further includes forming the insulator material upon a gate conductor 150 topwall or top side 116 of the metal seeds 110. The insulator material may be formed conformally. Because the metal seeds 110 may be evenly spaced in parallel from one another, the formed gate insulator 160 sidewalls may be evenly spaced from one another, such that each first trench 170, defined between opposing gate insulator 160 sidewalls, defines a width T (FIG. 14).
The method of the present embodiment includes leaving portions of the substrate 50 located within the first trenches 170 exposed. Leaving the portions of the substrate 50 within the first trenches 170 exposed may be accomplished by forming the insulator material only upon the first side 111, second side 112, and/or top side 116 of the metal seeds 110, but not upon the substrate 50 within the first trenches 170. Leaving the portions of the substrate 50 within the first trenches 170 exposed may alternatively be accomplished by forming the insulator material upon the first side 111, second side 112, and top side 116 of the metal seeds 110 and also upon the substrate 50 within the first trenches 170, followed by removal of the gate insulator 160 bottomwall (i.e., the insulator material covering the substrate 50 within the first trenches 170). The removal of the insulator material may be accomplished by any suitable technique, including etching.
The insulator material of the gate insulator 160 sidewalls may be formed by any suitable technique, including, but not limited to, ALD, plasma-enhanced ALD, PVD, or other known methods. The insulator material of the gate insulator 160 may comprise any suitable insulative material. For example, without limitation, the material of the gate insulator 160 may be an oxide.
With reference to FIG. 15, the present embodiment of the method may further include filling the first trench 170 (FIG. 14) with a second insulator material 180. The second insulator material 180 may not only fill the first trenches 170, covering the exposed substrate 50, but may also cover the gate insulator 160 top wall. Filling the first trenches 170 with the second insulator material 180 may be accomplished by any suitable method, including, without limitation, by spin coating, blanket coating, CVD, PVD, in situ growth, or other known methods. The second insulator material 180 may be any suitable insulative material. For example, without limitation, the second insulator material 180 may be a conventional ILD material, such as silicon nitride.
With reference to FIG. 16, the present embodiment of the method may further include, if necessary, removing portions of the second insulator material 180, portions of the gate insulator 160 material, and portions of the gate conductor 150 material, to expose the top sides 116 of the metal seeds 110. This may be accomplished by any suitable method, including, without limitation, abrasive planarization methods such as chemical mechanical polishing or planarization (“CMP”) or an etching process.
With reference to FIGS. 17 through 19, the present embodiment of the method may further include selectively removing segments of the second insulator material 180 to expose sections of the substrate 50 underlying the segments of second insulator material 180 removed. This may be accomplished as described above with reference to FIGS. 7 through 9.
According to the present embodiment of the method, the bottom side 205 of each cavity 200 is bordered by and defined by an exposed upper surface of the substrate 50. The top side 206 of each cavity 200 remains open.
FIGS. 20 and 21 depict identical stages of processing as those depicted in FIGS. 10 and 11, respectively. The description of FIG. 20 is equivalent to the description of FIG. 10, and the description of FIG. 21 is equivalent to the description of FIG. 11.
It will be understood that the formed VFET device 100 (FIG. 1) and array 300, depicted in FIG. 21, may be thereafter subjected to additional processing to form top contacts, metal interconnects, additional stacked layers of arrays 300 of VFET devices 100, and the like, the result of which may be the formation of a cross-point memory array. The additional processing may be conducted by conventional techniques, which are not described in detail herein.
The VFET device 100 and array 300 may be used in a memory access device (not shown) that includes a memory cell (not shown) electrically coupled to the VFET device 100. The memory cell includes a top electrode (not shown) and a bottom electrode (not shown), which is coupled to a contact (not shown) for the drain. The source is coupled to another contact. Upon biasing of the source contact, the gate 140, and the top electrode, the VFET device 100 is turned “on” and current flows through the channel region 130 and memory cell.
While the disclosed device structures and methods are susceptible to various modifications and alternative forms in implementation thereof, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the present invention is not intended to be limited to the particular forms disclosed. Rather, the present invention encompasses all modifications, combinations, equivalents, variations, and alternatives falling within the scope of the present disclosure as defined by the following appended claims and their legal equivalents.

Claims (18)

What is claimed is:
1. A method for fabricating a semiconductor device structure, comprising:
forming a plurality of metal seeds upon a substrate;
forming a conductor material upon each of the plurality of metal seeds to form a plurality of gate conductors;
forming an insulator material upon each of the plurality of gate conductors to form a plurality of gate insulators, a first gate insulator of the plurality of gate insulators separated from a second gate insulator of the plurality of gate insulators by a first trench; and
filling the first trench with a channel material to form a channel region.
2. The method of claim 1, wherein forming a plurality of metal seeds comprises forming the plurality of metal seeds such that the metal seeds are spaced from one another by a first distance and arranged in parallel.
3. The method of claim 2, wherein forming the insulator material upon each of the plurality of gate conductors to form the plurality of gate insulators comprises forming the insulator material such that the first trench has a width less than the first distance.
4. The method of claim 1, wherein forming a conductor material upon each of the plurality of metal seeds comprises forming at least one graphene layer upon each of the plurality of metal seeds.
5. A method for fabricating an array of vertical transistor devices, comprising:
forming a plurality of metal seeds upon a substrate;
forming a conductor material upon each of the plurality of metal seeds to form a plurality of gate conductors;
forming a first insulator material upon each of the plurality of gate conductors to form a plurality of gate insulators, a first gate insulator of the plurality of gate insulators separated from a second gate insulator of the plurality of gate insulators by a first trench;
filling the first trench with a second insulator material;
removing segments of the second insulator material to expose underlying sections of the substrate and to define a plurality of cavities; and
filling the plurality of cavities with a channel material to form channel regions bordered on a first side by the first gate insulators and bordered on a second side by the second gate insulators.
6. The method of claim 5, wherein forming a conductor material upon each of the plurality of metal seeds comprises forming at least one graphene monolayer upon each vertical side of the plurality of metal seeds.
7. The method of claim 5, wherein forming a first insulator material upon each of the plurality of gate conductors comprises overlaying an oxide material upon each vertical side of the plurality of gate conductors.
8. The method of claim 5, wherein filling the first trench with a second insulator material comprises filling the first trench with silicon oxide or silicon nitride.
9. The method of claim 5, further comprising, after filling the plurality of cavities with the channel material, removing the plurality of metal seeds.
10. The method of claim 5, wherein removing segments of the second insulator material comprises selectively removing equally-spaced segments of the second insulator material to expose equally-spaced sections of the underlying substrate and to define the plurality of cavities, and wherein the plurality of cavities are equally-spaced.
11. The method of claim 1, wherein filling the first trench with a channel material comprises:
filling the first trench with another insulator material;
removing at least one segment of the another insulator material to form at least one cavity; and
filling the at least one cavity with the channel material to form the channel region.
12. The method of claim 1, further comprising, after filling the first trench with the channel material, removing the plurality of metal seeds.
13. A method for fabricating at least one semiconductor device structure, comprising:
forming metal seeds on a substrate to define a trench between sidewalls of the metal seeds;
forming, in the trench, a conductor material and an insulator material on the sidewalls of the metal seeds to define a narrower trench than the trench between the metal seeds; filling at least a portion of the narrower trench with a channel material to form at least one channel region disposed between the sidewalls of the metal seeds; and removing the metal seeds to leave the at least one semiconductor device structure defining a width equal to a width of the trench.
14. The method of claim 13, wherein forming, in the trench, a conductor material and an insulator material on the sidewalls of the metal seeds comprises forming the insulator material after forming the conductor material.
15. The method of claim 13, wherein forming, in the trench, a conductor material and an insulator material comprises conformally forming the conductor material on the sidewalls of the metal seeds.
16. The method of claim 13, wherein filling at least a portion of the narrower trench with a channel material comprises filling at least the portion of the narrower trench with indium gallium zinc oxide.
17. The method of claim 13, wherein forming, in the trench, a conductor material and an insulator material on the sidewalls of the metal seeds comprises forming the conductor material to a lesser thickness than a thickness of the insulator material.
18. The method of claim 13, wherein filling at least a portion of the narrower trench with a channel material comprises:
filling the narrower trench with another insulator material;
removing segments of the another insulator material to define cavities in the another insulator material; and
filling the cavities with the channel material to form an array of channel regions.
US13/215,968 2011-08-23 2011-08-23 Methods for fabricating semiconductor device structures and arrays of vertical transistor devices Active 2033-06-12 US8969154B2 (en)

Priority Applications (11)

Application Number Priority Date Filing Date Title
US13/215,968 US8969154B2 (en) 2011-08-23 2011-08-23 Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
EP12825988.4A EP2748856B1 (en) 2011-08-23 2012-08-21 Semiconductor device structures including vertical transistor devices, arrays of vertical transistor devices, and methods of fabrication
PCT/US2012/051711 WO2013028685A2 (en) 2011-08-23 2012-08-21 Semiconductor device structures including vertical transistor devices, arrays of vertical transistor devices, and methods of fabrication
CN201280041260.2A CN103765595B (en) 2011-08-23 2012-08-21 Semiconductor device structures including vertical transistor devices, arrays of vertical transistor devices, and methods of fabrication
KR1020147003763A KR101570945B1 (en) 2011-08-23 2012-08-21 Semiconductor device structures including vertical transistor devices, arrays of vertical transistor devices, and methods of fabrication
JP2014527242A JP5883508B2 (en) 2011-08-23 2012-08-21 Vertical transistor element, semiconductor element structure including an array of vertical transistor elements, and manufacturing method
US14/629,555 US9356155B2 (en) 2011-08-23 2015-02-24 Semiconductor device structures and arrays of vertical transistor devices
US15/167,765 US10002935B2 (en) 2011-08-23 2016-05-27 Semiconductor devices and structures and methods of formation
US16/004,908 US10446692B2 (en) 2011-08-23 2018-06-11 Semiconductor devices and structures
US16/587,921 US11011647B2 (en) 2011-08-23 2019-09-30 Semiconductor devices comprising channel materials
US17/313,646 US11652173B2 (en) 2011-08-23 2021-05-06 Methods of forming a semiconductor device comprising a channel material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/215,968 US8969154B2 (en) 2011-08-23 2011-08-23 Methods for fabricating semiconductor device structures and arrays of vertical transistor devices

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US14/629,555 Division US9356155B2 (en) 2011-08-23 2015-02-24 Semiconductor device structures and arrays of vertical transistor devices
US14/629,555 Continuation US9356155B2 (en) 2011-08-23 2015-02-24 Semiconductor device structures and arrays of vertical transistor devices

Publications (2)

Publication Number Publication Date
US20130049120A1 US20130049120A1 (en) 2013-02-28
US8969154B2 true US8969154B2 (en) 2015-03-03

Family

ID=47742422

Family Applications (6)

Application Number Title Priority Date Filing Date
US13/215,968 Active 2033-06-12 US8969154B2 (en) 2011-08-23 2011-08-23 Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US14/629,555 Active US9356155B2 (en) 2011-08-23 2015-02-24 Semiconductor device structures and arrays of vertical transistor devices
US15/167,765 Active US10002935B2 (en) 2011-08-23 2016-05-27 Semiconductor devices and structures and methods of formation
US16/004,908 Active US10446692B2 (en) 2011-08-23 2018-06-11 Semiconductor devices and structures
US16/587,921 Active US11011647B2 (en) 2011-08-23 2019-09-30 Semiconductor devices comprising channel materials
US17/313,646 Active 2031-11-30 US11652173B2 (en) 2011-08-23 2021-05-06 Methods of forming a semiconductor device comprising a channel material

Family Applications After (5)

Application Number Title Priority Date Filing Date
US14/629,555 Active US9356155B2 (en) 2011-08-23 2015-02-24 Semiconductor device structures and arrays of vertical transistor devices
US15/167,765 Active US10002935B2 (en) 2011-08-23 2016-05-27 Semiconductor devices and structures and methods of formation
US16/004,908 Active US10446692B2 (en) 2011-08-23 2018-06-11 Semiconductor devices and structures
US16/587,921 Active US11011647B2 (en) 2011-08-23 2019-09-30 Semiconductor devices comprising channel materials
US17/313,646 Active 2031-11-30 US11652173B2 (en) 2011-08-23 2021-05-06 Methods of forming a semiconductor device comprising a channel material

Country Status (6)

Country Link
US (6) US8969154B2 (en)
EP (1) EP2748856B1 (en)
JP (1) JP5883508B2 (en)
KR (1) KR101570945B1 (en)
CN (1) CN103765595B (en)
WO (1) WO2013028685A2 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140231751A1 (en) * 2013-02-15 2014-08-21 Kabushiki Kaisha Toshiba Semiconductor device
US9755071B1 (en) 2016-06-30 2017-09-05 International Business Machines Corporation Merged gate for vertical transistors
US10002935B2 (en) 2011-08-23 2018-06-19 Micron Technology, Inc. Semiconductor devices and structures and methods of formation
US20200066917A1 (en) * 2018-08-27 2020-02-27 Micron Technology, Inc. Transistors comprising two-dimensional materials and related semiconductor devices, systems, and methods
US10854549B2 (en) 2018-12-31 2020-12-01 Micron Technology, Inc. Redistribution layers with carbon-based conductive elements, methods of fabrication and related semiconductor device packages and systems
US10943953B2 (en) 2017-08-31 2021-03-09 Micron Technology, Inc. Semiconductor devices, hybrid transistors, and related methods
US11189588B2 (en) 2018-12-31 2021-11-30 Micron Technology, Inc. Anisotropic conductive film with carbon-based conductive regions and related semiconductor assemblies, systems, and methods
US11282833B2 (en) 2018-11-16 2022-03-22 Samsung Electronics Co., Ltd. Semiconductor device
US11335788B2 (en) 2017-08-31 2022-05-17 Micron Technology, Inc. Semiconductor devices, transistors, and related methods for contacting metal oxide semiconductor devices

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6161431B2 (en) * 2013-06-27 2017-07-12 株式会社半導体エネルギー研究所 Semiconductor device
KR102140148B1 (en) 2013-11-29 2020-07-31 삼성전자주식회사 Memory device including two-dimensional material and methods of manufacturing and operating the same
US9812604B2 (en) * 2014-05-30 2017-11-07 Klaus Y. J. Hsu Photosensing device with graphene
US9847233B2 (en) * 2014-07-29 2017-12-19 Taiwan Semiconductor Manufacturing Company Limited Semiconductor device and formation thereof
JP6430302B2 (en) 2015-03-13 2018-11-28 東芝メモリ株式会社 Nonvolatile semiconductor memory device
WO2016156659A1 (en) * 2015-04-01 2016-10-06 Picosun Oy Ald-deposited graphene on a conformal seed layer
US9690627B2 (en) 2015-09-01 2017-06-27 International Business Machines Corporation Redeployable resource forecasting
US9947592B2 (en) * 2015-11-16 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices and methods of forming the same
KR102573407B1 (en) * 2016-08-24 2023-08-30 삼성전자주식회사 Semiconductor device and method for fabricating the same
US9786760B1 (en) 2016-09-29 2017-10-10 International Business Machines Corporation Air gap and air spacer pinch off
US9947664B1 (en) 2016-10-14 2018-04-17 International Business Machines Corporation Semiconductor device and method of forming the semiconductor device
US10622458B2 (en) 2017-05-19 2020-04-14 International Business Machines Corporation Self-aligned contact for vertical field effect transistor
US10636789B2 (en) 2017-05-26 2020-04-28 Qualcomm Incorporated Transistor with low resistivity carbon alloy
CN108933174B (en) * 2017-05-27 2021-09-14 中芯国际集成电路制造(上海)有限公司 Fin field effect transistor and forming method thereof
US10134739B1 (en) 2017-07-27 2018-11-20 Globalfoundries Inc. Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array
EP3857609A4 (en) * 2018-10-09 2022-06-15 Micron Technology, Inc. Methods of forming a device, and related devices and electronic systems
TWI743568B (en) 2018-10-09 2021-10-21 美商美光科技公司 Devices including vertical transistors, and related methods
US11398571B2 (en) * 2018-10-09 2022-07-26 Micron Technology, Inc. Devices and electronic systems including vertical transistors, and related methods
US10629732B1 (en) * 2018-10-09 2020-04-21 Micron Technology, Inc. Elevationally-extending transistors, devices comprising elevationally-extending transistors, and methods of forming a device comprising elevationally-extending transistors
KR102669149B1 (en) 2019-01-10 2024-05-24 삼성전자주식회사 Semiconductor devices
CN110391250A (en) * 2019-06-21 2019-10-29 长江存储科技有限责任公司 A kind of three-dimensional storage and preparation method thereof
CN113823676B (en) * 2020-06-18 2023-07-04 联华电子股份有限公司 Semiconductor device and method for manufacturing the same
EP4040500A1 (en) * 2021-02-04 2022-08-10 Infineon Technologies AG Transistor device and method of manufacturing

Citations (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903189A (en) 1988-04-27 1990-02-20 General Electric Company Low noise, high frequency synchronous rectifier
US5107321A (en) 1990-04-02 1992-04-21 National Semiconductor Corporation Interconnect method for semiconductor devices
US5460988A (en) 1994-04-25 1995-10-24 United Microelectronics Corporation Process for high density flash EPROM cell
US5578513A (en) * 1993-09-17 1996-11-26 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor device having a gate all around type of thin film transistor
US5824577A (en) 1995-02-16 1998-10-20 National Semiconductor Corporation MOSFET with reduced leakage current
US5899735A (en) 1997-09-19 1999-05-04 Vanguard International Semiconductor Corporation Method for making low-resistance contacts between polysilicon and metal silicide on semiconductor integrated circuits
US6165826A (en) 1994-12-23 2000-12-26 Intel Corporation Transistor with low resistance tip and method of fabrication in a CMOS process
US6218276B1 (en) 1997-12-22 2001-04-17 Lsi Logic Corporation Silicide encapsulation of polysilicon gate and interconnect
US6300198B1 (en) 1997-03-19 2001-10-09 Siemens Aktiengesellschaft Method for producing a vertical MOS-transistor
US6406962B1 (en) * 2001-01-17 2002-06-18 International Business Machines Corporation Vertical trench-formed dual-gate FET device structure and method for creation
US20030211695A1 (en) * 2002-05-13 2003-11-13 Ching-Yu Chang Methods of fabricating high density mask rom cells
US20040032553A1 (en) * 2002-08-16 2004-02-19 Lg.Philips Lcd Co., Ltd. Flat display device
US20040053431A1 (en) * 2002-09-13 2004-03-18 Industrial Technology Research Institute Method of forming a flexible thin film transistor display device with a metal foil substrate
US20050019993A1 (en) * 2003-07-24 2005-01-27 Deok-Hyung Lee Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
US6869581B2 (en) 2001-11-27 2005-03-22 Fuji Xerox Co., Ltd. Hollow graphene sheet structure, electrode structure, process for the production thereof, and device thus produced
WO2005079182A2 (en) 2004-01-22 2005-09-01 International Business Machines Corporation Vertical fin-fet mos devices
US6940113B2 (en) 2001-06-28 2005-09-06 Sharp Laboratories Of America, Inc. Trench isolated cross-point memory array
US20060046395A1 (en) 2004-09-01 2006-03-02 Nirmal Ramaswamy Forming a vertical transistor
US7015142B2 (en) 2003-06-12 2006-03-21 Georgia Tech Research Corporation Patterned thin film graphite devices and method for making same
US7071258B1 (en) 2002-10-21 2006-07-04 Nanotek Instruments, Inc. Nano-scaled graphene plates
US20070023839A1 (en) * 2005-07-27 2007-02-01 International Business Machines Corporation Finfet gate formed of carbon nanotubes
US20070235819A1 (en) * 2006-03-14 2007-10-11 Atsushi Yagishita Semiconductor device and method for manufacturing the same
US20080049486A1 (en) 2006-08-28 2008-02-28 Qimonda Ag Transistor, memory cell array and method for forming and operating a memory device
US20080099814A1 (en) 2006-10-30 2008-05-01 Qimonda Ag Integrated circuit and method for production
US7432557B1 (en) * 2003-07-08 2008-10-07 Advanced Micro Devices, Inc. FinFET device with multiple channels
US20080315282A1 (en) * 2006-02-09 2008-12-25 Samsung Electronics Co., Ltd. Semiconductor Devices Including Transistors Having Three Dimensional Channels
US20090047749A1 (en) * 2007-08-13 2009-02-19 Au Optronics Corp. Methods of manufacturing thin film transistor and display device
US7518182B2 (en) 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US20090181502A1 (en) 2008-01-16 2009-07-16 Texas Instruments Incorporated Method for fabricating graphene transistors on a silicon or soi substrate
US20100025660A1 (en) 2008-07-31 2010-02-04 University Of Connecticut Semiconductor devices, methods of manufacture thereof and articles comprising the same
US20100102292A1 (en) 2007-03-02 2010-04-29 Nec Corporation Semiconductor device using graphene and method of manufacturing the same
US7732859B2 (en) 2007-07-16 2010-06-08 International Business Machines Corporation Graphene-based transistor
US20100155843A1 (en) * 2007-06-21 2010-06-24 Commissariat A L'energie Atomique Field effect transistor with alternate electrical contacts
US7745290B2 (en) * 2006-07-03 2010-06-29 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor device including fin-fet
US7767525B2 (en) 2004-08-26 2010-08-03 Micron Technology, Inc. Methods of forming vertical transistor structures
US20100213435A1 (en) 2009-02-24 2010-08-26 Shosuke Fujii Switching device and nonvolatile memory device
US20100237336A1 (en) 2006-06-29 2010-09-23 University Of Florida Research Foundation, Inc. Nanotube enabled, gate-voltage controlled light emitting diodes
US20100258787A1 (en) 2009-04-08 2010-10-14 Electronics And Telecommunications Research Institute Field effect transistor having graphene channel layer
US20100270512A1 (en) 2009-04-27 2010-10-28 Hitachi, Ltd. Electrically connected graphene-metal electrode device, and electronic device, electronic integrated circuit and electro-optical integrated circuit using same
US20100295120A1 (en) 2009-05-20 2010-11-25 Gurtej Sandhu Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
US20100295119A1 (en) 2009-05-20 2010-11-25 Gurtej Sandhu Vertically-oriented semiconductor selection device for cross-point array memory
US20110041980A1 (en) 2009-08-24 2011-02-24 Tae-Whan Kim Electronic device utilizing graphene electrodes and ogranic/inorganic hybrid composites and method of manufacturing the electronic device
US20110045202A1 (en) 2007-08-31 2011-02-24 Micron Technology, Inc. Formation of Carbon-Containing Material
US20110114919A1 (en) * 2009-11-13 2011-05-19 International Business Machines Corporation Self-aligned graphene transistor
US20110123776A1 (en) 2009-11-13 2011-05-26 Samsung Electronics Co., Ltd. Graphene laminate and method of preparing the same
US7952088B2 (en) * 2008-07-11 2011-05-31 International Business Machines Corporation Semiconducting device having graphene channel
US20110206934A1 (en) * 2010-02-22 2011-08-25 International Business Machines Corporation Graphene formation utilizing solid phase carbon sources
US20110210395A1 (en) * 2005-12-16 2011-09-01 Freescale Semiconductor, Inc. Transistors with immersed contacts
US20110220865A1 (en) * 2010-03-11 2011-09-15 Kabushiki Kaisha Toshiba Transistor and manufacturing method thereof
US20110253983A1 (en) * 2008-08-29 2011-10-20 Advanced Micro Devices, Inc. Sidewall graphene devices for 3-d electronics
US20110291196A1 (en) * 2010-05-31 2011-12-01 Globalfoundries Inc. Self-Aligned Multiple Gate Transistor Formed on a Bulk Substrate
US8101474B2 (en) * 2010-01-06 2012-01-24 International Business Machines Corporation Structure and method of forming buried-channel graphene field effect device
US20120074387A1 (en) * 2010-09-23 2012-03-29 Sean King Microelectronic transistor having an epitaxial graphene channel layer
US20120145998A1 (en) * 2009-09-21 2012-06-14 International Business Machines Corporation Local Bottom Gates for Graphene and Carbon Nanotube Devices
US20120205719A1 (en) * 2010-11-19 2012-08-16 Micron Technology, Inc. Double gated 4f2 dram chc cell and methods of fabricating the same
US20120220102A1 (en) * 2010-11-22 2012-08-30 Zvi Or-Bach Semiconductor device and structure
US20120258587A1 (en) * 2011-04-07 2012-10-11 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Method of Forming Graphene on a Surface
US20120264272A1 (en) * 2010-12-27 2012-10-18 Micron Technology, Inc. Methods Of Forming A Nonvolatile Memory Cell And Methods Of Forming An Array Of Nonvolatile Memory Cells Array Of Nonvolatile Memory Cells
US20120313170A1 (en) * 2011-06-10 2012-12-13 International Business Machines Corporation Fin-Last Replacement Metal Gate FinFET
US8344358B2 (en) * 2010-09-07 2013-01-01 International Business Machines Corporation Graphene transistor with a self-aligned gate
US20130005102A1 (en) * 2008-04-03 2013-01-03 Micron Technology, Inc. Data Cells with Drivers and Methods of Making and Operating the Same
US20130122668A1 (en) * 2010-09-07 2013-05-16 International Business Machines Corporation Method for forming and structure of a recessed source/drain strap for a mugfet
US20130230958A1 (en) * 2009-12-02 2013-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-Gate Semiconductor Device and Method
US8546198B2 (en) * 2008-12-22 2013-10-01 Electronics And Telecommunications Research Institute Method of manufacturing transparent transistor with multi-layered structures
US20140061650A1 (en) * 2006-01-09 2014-03-06 Technion Research And Development Foundation Ltd. Transistor structures and methods of fabrication thereof
US20140124729A1 (en) * 2011-06-10 2014-05-08 Seoul National University R&Db Foundation 3-dimensional (3d) non-volatile memory device and method of fabricating the same
US20140225068A1 (en) * 2010-12-17 2014-08-14 Samsung Electronics Co., Ltd. Graphene electronic device and method of fabricating the same

Family Cites Families (139)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63131056A (en) * 1986-11-20 1988-06-03 Terumo Corp Fet electrode
US5308782A (en) * 1992-03-02 1994-05-03 Motorola Semiconductor memory device and method of formation
US5468661A (en) * 1993-06-17 1995-11-21 Texas Instruments Incorporated Method of making power VFET device
JP3403231B2 (en) * 1993-05-12 2003-05-06 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US5874745A (en) * 1997-08-05 1999-02-23 International Business Machines Corporation Thin film transistor with carbonaceous gate dielectric
US5907170A (en) * 1997-10-06 1999-05-25 Micron Technology, Inc. Circuit and method for an open bit line memory cell with a vertical transistor and trench plate trench capacitor
JP2003209122A (en) * 2002-01-16 2003-07-25 Seiko Epson Corp Organic semiconductor device
US6777761B2 (en) * 2002-08-06 2004-08-17 International Business Machines Corporation Semiconductor chip using both polysilicon and metal gate devices
US6821834B2 (en) * 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
JP2004304167A (en) * 2003-03-20 2004-10-28 Advanced Lcd Technologies Development Center Co Ltd Wiring, display device and method for forming the same
US7456476B2 (en) * 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
JPWO2005022637A1 (en) * 2003-08-28 2007-11-01 日本電気株式会社 Semiconductor device having fin-type field effect transistor
KR100578130B1 (en) * 2003-10-14 2006-05-10 삼성전자주식회사 Multi silicon fins for finfet and method for fabricating the same
US7105390B2 (en) * 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
KR100612419B1 (en) * 2004-10-19 2006-08-16 삼성전자주식회사 Semiconductor devices having a fin transistor and a plannar transistor and methods of forming the same
US7381608B2 (en) * 2004-12-07 2008-06-03 Intel Corporation Method for making a semiconductor device with a high-k gate dielectric and a metal gate electrode
US20080121932A1 (en) * 2006-09-18 2008-05-29 Pushkar Ranade Active regions with compatible dielectric layers
KR100630746B1 (en) * 2005-05-06 2006-10-02 삼성전자주식회사 Multi-bit and multi-level non-volatile memory device and methods of operating and fabricating the same
US7205601B2 (en) * 2005-06-09 2007-04-17 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET split gate EEPROM structure and method of its fabrication
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US8188551B2 (en) * 2005-09-30 2012-05-29 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
KR100652433B1 (en) * 2005-09-08 2006-12-01 삼성전자주식회사 Non volatile memory device capable of multi-bit storage
JP2007080995A (en) * 2005-09-13 2007-03-29 Toshiba Corp Semiconductor device
US7479421B2 (en) * 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7498211B2 (en) * 2005-12-28 2009-03-03 Intel Corporation Independently controlled, double gate nanowire memory cell with self-aligned contacts
US7473946B2 (en) * 2006-02-22 2009-01-06 International Business Machines Corporation CMOS structure and method including multiple crystallographic planes
US7842558B2 (en) * 2006-03-02 2010-11-30 Micron Technology, Inc. Masking process for simultaneously patterning separate regions
JP2007258485A (en) * 2006-03-23 2007-10-04 Toshiba Corp Semiconductor device and its manufacturing method
US20070246765A1 (en) * 2006-03-30 2007-10-25 Lars Bach Semiconductor memory device and method for production
US7714386B2 (en) * 2006-06-09 2010-05-11 Northrop Grumman Systems Corporation Carbon nanotube field effect transistor
KR100739532B1 (en) * 2006-06-09 2007-07-13 삼성전자주식회사 Method of forming a buried bit line
US10540704B2 (en) * 2007-09-06 2020-01-21 Mohammad A. Mazed System and method for machine learning based user application
KR100836761B1 (en) * 2006-12-08 2008-06-10 삼성전자주식회사 Finfet and method of manufacturing the same
KR101334181B1 (en) * 2007-04-20 2013-11-28 삼성전자주식회사 Thin Film Transistor having selectively crystallized channel layer and method of manufacturing the same
TWI345671B (en) * 2007-08-10 2011-07-21 Au Optronics Corp Thin film transistor, pixel structure and liquid crystal display panel
TW200913162A (en) * 2007-09-11 2009-03-16 Univ Nat Chiao Tung Nonvolatile memory device with nanowire channel and a method for fabricating the same
US20090085157A1 (en) * 2007-09-28 2009-04-02 Klaus Muemmler Manufacturing method for an integrated circuit, corresponding intermediate integrated circuit structure and corresponding integrated circuit
US8159791B2 (en) * 2008-02-06 2012-04-17 Hitachi Global Storage Technologies Netherlands B.V. Magnetoresistive sensor having quantum well structure and a trapping layer for preventing charge carrier migration
US7915659B2 (en) * 2008-03-06 2011-03-29 Micron Technology, Inc. Devices with cavity-defined gates and methods of making the same
US8022487B2 (en) * 2008-04-29 2011-09-20 Intel Corporation Increasing body dopant uniformity in multi-gate transistor devices
CN101582448B (en) * 2008-05-14 2012-09-19 清华大学 Thin film transistor
US8507840B2 (en) * 2010-12-21 2013-08-13 Zena Technologies, Inc. Vertically structured passive pixel arrays and methods for fabricating the same
JP4623179B2 (en) * 2008-09-18 2011-02-02 ソニー株式会社 Thin film transistor and manufacturing method thereof
EP2421030B1 (en) * 2008-09-19 2020-10-21 Semiconductor Energy Laboratory Co., Ltd. Display device
US7863136B2 (en) * 2008-09-30 2011-01-04 Qimonda Ag Method of manufacturing integrated circuits including a FET with a gate spacer and a fin
US8067803B2 (en) * 2008-10-16 2011-11-29 Micron Technology, Inc. Memory devices, transistor devices and related methods
US8741702B2 (en) * 2008-10-24 2014-06-03 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR100962898B1 (en) * 2008-11-14 2010-06-10 엘지이노텍 주식회사 Semiconductor light emitting device and fabrication method thereof
JP2010123758A (en) * 2008-11-19 2010-06-03 Nec Corp Thin film device and method of manufacturing the same
WO2010065517A1 (en) * 2008-12-01 2010-06-10 The Trustees Of Columbia University In The City Of New York Electromechanical devices and methods for fabrication of the same
KR20100075100A (en) * 2008-12-24 2010-07-02 서울대학교산학협력단 The manufacturing method of active channel region for organic field-effect transistors using inkjet printing and the organic field-effect transistors thereby
JP5590877B2 (en) 2008-12-26 2014-09-17 株式会社半導体エネルギー研究所 Semiconductor device
DE102008063429B4 (en) * 2008-12-31 2015-03-26 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Setting the configuration of a multi-gate transistor by controlling individual lands
US8120073B2 (en) * 2008-12-31 2012-02-21 Intel Corporation Trigate transistor having extended metal gate electrode
GB2467357B (en) * 2009-01-30 2011-09-21 Cambridge Display Tech Ltd Organic thin film transistors
US7893492B2 (en) * 2009-02-17 2011-02-22 International Business Machines Corporation Nanowire mesh device and method of fabricating same
US20100213458A1 (en) * 2009-02-23 2010-08-26 Micron Technology, Inc. Rigid semiconductor memory having amorphous metal oxide semiconductor channels
JP2010212619A (en) 2009-03-12 2010-09-24 Toshiba Corp Graphene manufacturing method, graphene, graphene manufacturing device, and semiconductor device
WO2010113518A1 (en) * 2009-04-01 2010-10-07 国立大学法人北海道大学 Field-effect transistor
US8187938B2 (en) * 2009-04-13 2012-05-29 Hynix Semiconductor Inc. Non-volatile memory device and method for fabricating the same
US8110467B2 (en) * 2009-04-21 2012-02-07 International Business Machines Corporation Multiple Vt field-effect transistor devices
US8124507B2 (en) * 2009-06-24 2012-02-28 Panasonic Corporation Semiconductor device and method for fabricating the same
JP2011014754A (en) * 2009-07-03 2011-01-20 Elpida Memory Inc Semiconductor integrated circuit device
JP5395542B2 (en) * 2009-07-13 2014-01-22 株式会社東芝 Semiconductor device
CN101997035B (en) * 2009-08-14 2012-08-29 清华大学 Thin film transistor
US9245805B2 (en) * 2009-09-24 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Germanium FinFETs with metal gates and stressors
KR101584113B1 (en) * 2009-09-29 2016-01-13 삼성전자주식회사 3 Three Dimensional Semiconductor Memory Device And Method Of Fabricating The Same
US8143121B2 (en) * 2009-10-01 2012-03-27 Nanya Technology Corp. DRAM cell with double-gate fin-FET, DRAM cell array and fabrication method thereof
KR101081193B1 (en) * 2009-10-15 2011-11-07 엘지이노텍 주식회사 Semiconductor light emitting device and fabrication method thereof
KR101603771B1 (en) * 2009-10-21 2016-03-16 삼성전자주식회사 Electronic device using 2D sheet material and fabrication method the same
US8653608B2 (en) * 2009-10-27 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. FinFET design with reduced current crowding
DE102009046246B4 (en) * 2009-10-30 2012-04-12 GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG Manufacturing method and semiconductor device with deformation technology in three-dimensional transistors based on globally deformed semiconductor base layers
JP5515660B2 (en) * 2009-11-13 2014-06-11 セイコーエプソン株式会社 Manufacturing method of substrate for semiconductor device
US20110127492A1 (en) * 2009-11-30 2011-06-02 International Business Machines Corporation Field Effect Transistor Having Nanostructure Channel
WO2011074987A1 (en) * 2009-12-17 2011-06-23 Universitetssenteret På Kjeller Field effect transistor structure
TWI492432B (en) * 2009-12-17 2015-07-11 Hitachi Ltd Semiconductor memory device and manufacturing method thereof
US8421164B2 (en) * 2010-01-05 2013-04-16 Micron Technology, Inc. Memory cell array with semiconductor selection device for multiple memory cells
US8242560B2 (en) * 2010-01-15 2012-08-14 International Business Machines Corporation FinFET with thin gate dielectric layer
US8310013B2 (en) * 2010-02-11 2012-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a FinFET device
CN101783366A (en) * 2010-02-11 2010-07-21 复旦大学 Preparation method of graphene MOS transistor
KR101129930B1 (en) * 2010-03-09 2012-03-27 주식회사 하이닉스반도체 Semiconductor device and method for forming the same
JP2011216647A (en) * 2010-03-31 2011-10-27 Dainippon Printing Co Ltd Method for manufacturing pattern-formed body, method for manufacturing functional element, and method for manufacturing semiconductor element
EP2393118A1 (en) * 2010-06-02 2011-12-07 Nanya Technology Corporation Single-gate FinFET and fabrication method thereof
US8716095B2 (en) * 2010-06-03 2014-05-06 Institute of Microelectronics, Chinese Academy of Sciences Manufacturing method of gate stack and semiconductor device
JP2012015436A (en) * 2010-07-05 2012-01-19 Sony Corp Thin film transistor and display device
US8642416B2 (en) * 2010-07-30 2014-02-04 Monolithic 3D Inc. Method of forming three dimensional integrated circuit devices using layer transfer technique
DE102010038742B4 (en) * 2010-07-30 2016-01-21 Globalfoundries Dresden Module One Llc & Co. Kg Method and semiconductor device based on a deformation technology in three-dimensional transistors based on a deformed channel semiconductor material
WO2012017533A1 (en) * 2010-08-05 2012-02-09 富士通株式会社 Method for manufacturing semiconductor device and method for growing graphene
US8796733B2 (en) * 2010-08-09 2014-08-05 University Of Notre Dame Du Lac Low voltage tunnel field-effect transistor (TFET) and method of making same
US8431486B2 (en) * 2010-08-10 2013-04-30 International Business Machines Corporation Interconnect structure for improved time dependent dielectric breakdown
US8207032B2 (en) * 2010-08-31 2012-06-26 Micron Technology, Inc. Methods of forming pluralities of vertical transistors, and methods of forming memory arrays
US8530273B2 (en) * 2010-09-29 2013-09-10 Guardian Industries Corp. Method of making oxide thin film transistor array
KR101723864B1 (en) * 2010-10-08 2017-04-07 삼성전자주식회사 Semiconductor Device With Vertical Channel Transistor And Method Of Fabricating The Same
EP2442374B1 (en) * 2010-10-12 2016-09-21 LG Innotek Co., Ltd. Light emitting device
KR101755635B1 (en) * 2010-10-14 2017-07-10 삼성전자주식회사 Semiconductor device and method of fabricating the same
KR101457833B1 (en) * 2010-12-03 2014-11-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
US20120168723A1 (en) * 2010-12-29 2012-07-05 Electronics And Telecommunications Research Institute Electronic devices including graphene and methods of forming the same
TWI487108B (en) * 2011-01-13 2015-06-01 Prime View Int Co Ltd Metal oxide semiconductor structure and manufacturing method thereof
US8617941B2 (en) * 2011-01-16 2013-12-31 International Business Machines Corporation High-speed graphene transistor and method of fabrication by patternable hard mask materials
TWI552345B (en) * 2011-01-26 2016-10-01 半導體能源研究所股份有限公司 Semiconductor device and manufacturing method thereof
US8957442B2 (en) * 2011-02-11 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Light-emitting device and display device
US9162885B2 (en) * 2011-02-17 2015-10-20 Rutgers, The State University Of New Jersey Graphene-encapsulated nanoparticle-based biosensor for the selective detection of biomarkers
TWI538215B (en) * 2011-03-25 2016-06-11 半導體能源研究所股份有限公司 Field-effect transistor, and memory and semiconductor circuit including the same
KR101813173B1 (en) * 2011-03-30 2017-12-29 삼성전자주식회사 Semiconductor device, method of manufacturing the same and electronic device including semiconductor device
US8642996B2 (en) * 2011-04-18 2014-02-04 International Business Machines Corporation Graphene nanoribbons and carbon nanotubes fabricated from SiC fins or nanowire templates
US9006803B2 (en) * 2011-04-22 2015-04-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing thereof
KR101244768B1 (en) * 2011-05-04 2013-03-19 한국과학기술원 Non-volatile memory device using graphene gate electrode
KR101850703B1 (en) * 2011-05-17 2018-04-23 삼성전자 주식회사 Semiconductor device and method for fabricating the device
EP2715778B1 (en) * 2011-05-23 2023-06-07 National University of Singapore Method of transferring thin films
KR101797961B1 (en) * 2011-06-09 2017-11-16 삼성전자주식회사 Method for fabricating semiconductor device
US8685850B2 (en) * 2011-06-13 2014-04-01 Stmicroelectronics, Inc. System and method of plating conductive gate contacts on metal gates for self-aligned contact interconnections
EP2535937B1 (en) * 2011-06-17 2015-03-11 Friedrich-Alexander-Universität Erlangen-Nürnberg Electronic device
US10177170B2 (en) * 2011-06-24 2019-01-08 Sharp Kabushiki Kaisha Display device and method for manufacturing same
US8673426B2 (en) * 2011-06-29 2014-03-18 Semiconductor Energy Laboratory Co., Ltd. Driver circuit, method of manufacturing the driver circuit, and display device including the driver circuit
US9553195B2 (en) * 2011-06-30 2017-01-24 Applied Materials, Inc. Method of IGZO and ZNO TFT fabrication with PECVD SiO2 passivation
US8514626B2 (en) * 2011-07-26 2013-08-20 Micron Technology, Inc. Memory cells and methods of storing information
US8394682B2 (en) * 2011-07-26 2013-03-12 Micron Technology, Inc. Methods of forming graphene-containing switches
US8969154B2 (en) 2011-08-23 2015-03-03 Micron Technology, Inc. Methods for fabricating semiconductor device structures and arrays of vertical transistor devices
US9177872B2 (en) * 2011-09-16 2015-11-03 Micron Technology, Inc. Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
US8803129B2 (en) * 2011-10-11 2014-08-12 International Business Machines Corporation Patterning contacts in carbon nanotube devices
US8735971B2 (en) * 2011-12-02 2014-05-27 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
KR101906406B1 (en) * 2011-12-30 2018-12-10 삼성전자주식회사 non-volatile memory device having vertical structure and fabrication method
KR101888003B1 (en) * 2012-04-09 2018-08-13 삼성전자주식회사 Semiconductor devices having transistors capable of adjusting threshold voltage through body bias effect and methods for fabricating the same
US20140004666A1 (en) * 2012-06-28 2014-01-02 International Business Machines Corporation Passivation of carbon nanotubes with molecular layers
US8815739B2 (en) * 2012-07-10 2014-08-26 Globalfoundries Inc. FinFET device with a graphene gate electrode and methods of forming same
US9093302B2 (en) * 2013-11-13 2015-07-28 Globalfoundries Inc. Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices
EP2884542A3 (en) * 2013-12-10 2015-09-02 IMEC vzw Integrated circuit device with power gating switch in back end of line
JP6585354B2 (en) * 2014-03-07 2019-10-02 株式会社半導体エネルギー研究所 Semiconductor device
US9614040B1 (en) * 2016-02-02 2017-04-04 International Business Machines Corporation Strained silicon germanium fin with block source/drain epitaxy and improved overlay capacitance
KR102476143B1 (en) * 2016-02-26 2022-12-12 삼성전자주식회사 Semiconductor device
US10008583B1 (en) * 2017-05-08 2018-06-26 Samsung Electronics Co., Ltd. Gate-all-around nanosheet field-effect transistors and methods of manufacturing the same
EP3676878A4 (en) * 2017-08-31 2020-11-04 Micron Technology, Inc. Semiconductor devices, hybrid transistors, and related methods
US10446664B1 (en) * 2018-03-20 2019-10-15 International Business Machines Corporation Inner spacer formation and contact resistance reduction in nanosheet transistors
WO2021041558A1 (en) * 2019-08-28 2021-03-04 Micron Technology, Inc. Memory device having 2-transistor vertical memory cell and shared channel region
US11527623B2 (en) * 2020-07-28 2022-12-13 Micron Technology, Inc. Integrated assemblies and methods of forming integrated assemblies
US11476254B2 (en) * 2021-01-29 2022-10-18 Micron Technology, Inc. Support pillars for vertical three-dimensional (3D) memory
US11631681B2 (en) * 2021-03-02 2023-04-18 Micron Technology, Inc. Vertical contacts for semiconductor devices
US11641732B2 (en) * 2021-04-22 2023-05-02 Micron Technology, Inc. Self-aligned etch back for vertical three dimensional (3D) memory

Patent Citations (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4903189A (en) 1988-04-27 1990-02-20 General Electric Company Low noise, high frequency synchronous rectifier
US5107321A (en) 1990-04-02 1992-04-21 National Semiconductor Corporation Interconnect method for semiconductor devices
US5578513A (en) * 1993-09-17 1996-11-26 Mitsubishi Denki Kabushiki Kaisha Method of making a semiconductor device having a gate all around type of thin film transistor
US5460988A (en) 1994-04-25 1995-10-24 United Microelectronics Corporation Process for high density flash EPROM cell
US6165826A (en) 1994-12-23 2000-12-26 Intel Corporation Transistor with low resistance tip and method of fabrication in a CMOS process
US5824577A (en) 1995-02-16 1998-10-20 National Semiconductor Corporation MOSFET with reduced leakage current
US6300198B1 (en) 1997-03-19 2001-10-09 Siemens Aktiengesellschaft Method for producing a vertical MOS-transistor
US5899735A (en) 1997-09-19 1999-05-04 Vanguard International Semiconductor Corporation Method for making low-resistance contacts between polysilicon and metal silicide on semiconductor integrated circuits
US6218276B1 (en) 1997-12-22 2001-04-17 Lsi Logic Corporation Silicide encapsulation of polysilicon gate and interconnect
US6406962B1 (en) * 2001-01-17 2002-06-18 International Business Machines Corporation Vertical trench-formed dual-gate FET device structure and method for creation
US6940113B2 (en) 2001-06-28 2005-09-06 Sharp Laboratories Of America, Inc. Trench isolated cross-point memory array
US6869581B2 (en) 2001-11-27 2005-03-22 Fuji Xerox Co., Ltd. Hollow graphene sheet structure, electrode structure, process for the production thereof, and device thus produced
US20030211695A1 (en) * 2002-05-13 2003-11-13 Ching-Yu Chang Methods of fabricating high density mask rom cells
US20040032553A1 (en) * 2002-08-16 2004-02-19 Lg.Philips Lcd Co., Ltd. Flat display device
US20040053431A1 (en) * 2002-09-13 2004-03-18 Industrial Technology Research Institute Method of forming a flexible thin film transistor display device with a metal foil substrate
US7071258B1 (en) 2002-10-21 2006-07-04 Nanotek Instruments, Inc. Nano-scaled graphene plates
US7015142B2 (en) 2003-06-12 2006-03-21 Georgia Tech Research Corporation Patterned thin film graphite devices and method for making same
US20060099750A1 (en) 2003-06-12 2006-05-11 Deheer Walt A Patterned thin film graphite devices and method for making same
US7432557B1 (en) * 2003-07-08 2008-10-07 Advanced Micro Devices, Inc. FinFET device with multiple channels
US20050019993A1 (en) * 2003-07-24 2005-01-27 Deok-Hyung Lee Methods for fabricating fin field effect transistors using a protective layer to reduce etching damage
WO2005079182A2 (en) 2004-01-22 2005-09-01 International Business Machines Corporation Vertical fin-fet mos devices
US7518182B2 (en) 2004-07-20 2009-04-14 Micron Technology, Inc. DRAM layout with vertical FETs and method of formation
US20100052027A1 (en) 2004-07-20 2010-03-04 Micron Technology, Inc. DRAM Layout with Vertical FETS and Method of Formation
US7767525B2 (en) 2004-08-26 2010-08-03 Micron Technology, Inc. Methods of forming vertical transistor structures
US7276416B2 (en) 2004-09-01 2007-10-02 Micron Technology, Inc. Method of forming a vertical transistor
US20060046395A1 (en) 2004-09-01 2006-03-02 Nirmal Ramaswamy Forming a vertical transistor
US20070023839A1 (en) * 2005-07-27 2007-02-01 International Business Machines Corporation Finfet gate formed of carbon nanotubes
US20110210395A1 (en) * 2005-12-16 2011-09-01 Freescale Semiconductor, Inc. Transistors with immersed contacts
US20140061650A1 (en) * 2006-01-09 2014-03-06 Technion Research And Development Foundation Ltd. Transistor structures and methods of fabrication thereof
US20080315282A1 (en) * 2006-02-09 2008-12-25 Samsung Electronics Co., Ltd. Semiconductor Devices Including Transistors Having Three Dimensional Channels
US20100184261A1 (en) * 2006-03-14 2010-07-22 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US8124465B2 (en) * 2006-03-14 2012-02-28 Kabushiki Kaisha Toshiba Method for manufacturing a semiconductor device having a source extension region and a drain extension region
US20070235819A1 (en) * 2006-03-14 2007-10-11 Atsushi Yagishita Semiconductor device and method for manufacturing the same
US20100237336A1 (en) 2006-06-29 2010-09-23 University Of Florida Research Foundation, Inc. Nanotube enabled, gate-voltage controlled light emitting diodes
US7745290B2 (en) * 2006-07-03 2010-06-29 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor device including fin-fet
US20080049486A1 (en) 2006-08-28 2008-02-28 Qimonda Ag Transistor, memory cell array and method for forming and operating a memory device
US20080099814A1 (en) 2006-10-30 2008-05-01 Qimonda Ag Integrated circuit and method for production
US20100102292A1 (en) 2007-03-02 2010-04-29 Nec Corporation Semiconductor device using graphene and method of manufacturing the same
US20100155843A1 (en) * 2007-06-21 2010-06-24 Commissariat A L'energie Atomique Field effect transistor with alternate electrical contacts
US20100200840A1 (en) 2007-07-16 2010-08-12 International Business Machines Corporation Graphene-based transistor
US7732859B2 (en) 2007-07-16 2010-06-08 International Business Machines Corporation Graphene-based transistor
US20090047749A1 (en) * 2007-08-13 2009-02-19 Au Optronics Corp. Methods of manufacturing thin film transistor and display device
US20110045202A1 (en) 2007-08-31 2011-02-24 Micron Technology, Inc. Formation of Carbon-Containing Material
US20090181502A1 (en) 2008-01-16 2009-07-16 Texas Instruments Incorporated Method for fabricating graphene transistors on a silicon or soi substrate
US20130005102A1 (en) * 2008-04-03 2013-01-03 Micron Technology, Inc. Data Cells with Drivers and Methods of Making and Operating the Same
US7952088B2 (en) * 2008-07-11 2011-05-31 International Business Machines Corporation Semiconducting device having graphene channel
US20100025660A1 (en) 2008-07-31 2010-02-04 University Of Connecticut Semiconductor devices, methods of manufacture thereof and articles comprising the same
US20110253983A1 (en) * 2008-08-29 2011-10-20 Advanced Micro Devices, Inc. Sidewall graphene devices for 3-d electronics
US8546198B2 (en) * 2008-12-22 2013-10-01 Electronics And Telecommunications Research Institute Method of manufacturing transparent transistor with multi-layered structures
US20100213435A1 (en) 2009-02-24 2010-08-26 Shosuke Fujii Switching device and nonvolatile memory device
US20100258787A1 (en) 2009-04-08 2010-10-14 Electronics And Telecommunications Research Institute Field effect transistor having graphene channel layer
US20100270512A1 (en) 2009-04-27 2010-10-28 Hitachi, Ltd. Electrically connected graphene-metal electrode device, and electronic device, electronic integrated circuit and electro-optical integrated circuit using same
US8274110B2 (en) * 2009-05-20 2012-09-25 Micron Technology, Inc. Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
US20100295120A1 (en) 2009-05-20 2010-11-25 Gurtej Sandhu Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
US20100295119A1 (en) 2009-05-20 2010-11-25 Gurtej Sandhu Vertically-oriented semiconductor selection device for cross-point array memory
WO2010135172A1 (en) 2009-05-20 2010-11-25 Micron Technology, Inc. Vertically-oriented selection transistor structure for cross-point memory array
US20110041980A1 (en) 2009-08-24 2011-02-24 Tae-Whan Kim Electronic device utilizing graphene electrodes and ogranic/inorganic hybrid composites and method of manufacturing the electronic device
US20120145998A1 (en) * 2009-09-21 2012-06-14 International Business Machines Corporation Local Bottom Gates for Graphene and Carbon Nanotube Devices
US20110114919A1 (en) * 2009-11-13 2011-05-19 International Business Machines Corporation Self-aligned graphene transistor
US20110123776A1 (en) 2009-11-13 2011-05-26 Samsung Electronics Co., Ltd. Graphene laminate and method of preparing the same
US8106383B2 (en) * 2009-11-13 2012-01-31 International Business Machines Corporation Self-aligned graphene transistor
US20130230958A1 (en) * 2009-12-02 2013-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-Gate Semiconductor Device and Method
US8101474B2 (en) * 2010-01-06 2012-01-24 International Business Machines Corporation Structure and method of forming buried-channel graphene field effect device
US20110206934A1 (en) * 2010-02-22 2011-08-25 International Business Machines Corporation Graphene formation utilizing solid phase carbon sources
US20110220865A1 (en) * 2010-03-11 2011-09-15 Kabushiki Kaisha Toshiba Transistor and manufacturing method thereof
US20110291196A1 (en) * 2010-05-31 2011-12-01 Globalfoundries Inc. Self-Aligned Multiple Gate Transistor Formed on a Bulk Substrate
US8344358B2 (en) * 2010-09-07 2013-01-01 International Business Machines Corporation Graphene transistor with a self-aligned gate
US20130122668A1 (en) * 2010-09-07 2013-05-16 International Business Machines Corporation Method for forming and structure of a recessed source/drain strap for a mugfet
US20120074387A1 (en) * 2010-09-23 2012-03-29 Sean King Microelectronic transistor having an epitaxial graphene channel layer
US20120205719A1 (en) * 2010-11-19 2012-08-16 Micron Technology, Inc. Double gated 4f2 dram chc cell and methods of fabricating the same
US20120220102A1 (en) * 2010-11-22 2012-08-30 Zvi Or-Bach Semiconductor device and structure
US20140225068A1 (en) * 2010-12-17 2014-08-14 Samsung Electronics Co., Ltd. Graphene electronic device and method of fabricating the same
US20120264272A1 (en) * 2010-12-27 2012-10-18 Micron Technology, Inc. Methods Of Forming A Nonvolatile Memory Cell And Methods Of Forming An Array Of Nonvolatile Memory Cells Array Of Nonvolatile Memory Cells
US20120258587A1 (en) * 2011-04-07 2012-10-11 The Government Of The United States Of America, As Represented By The Secretary Of The Navy Method of Forming Graphene on a Surface
US20120313170A1 (en) * 2011-06-10 2012-12-13 International Business Machines Corporation Fin-Last Replacement Metal Gate FinFET
US20140124729A1 (en) * 2011-06-10 2014-05-08 Seoul National University R&Db Foundation 3-dimensional (3d) non-volatile memory device and method of fabricating the same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
International Search Report of the ISA/KR, International Application No. PCT/US2012/051711, mailed Mar. 29, 2013, three (3) pages.
Written Opinion of the ISA/KR, International Application No. PCT/US2012/051711, mailed Mar. 29, 2013, five (5) pages.

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11011647B2 (en) 2011-08-23 2021-05-18 Micron Technology, Inc. Semiconductor devices comprising channel materials
US10446692B2 (en) 2011-08-23 2019-10-15 Micron Technology, Inc. Semiconductor devices and structures
US10002935B2 (en) 2011-08-23 2018-06-19 Micron Technology, Inc. Semiconductor devices and structures and methods of formation
US11652173B2 (en) 2011-08-23 2023-05-16 Micron Technology, Inc. Methods of forming a semiconductor device comprising a channel material
US20140231751A1 (en) * 2013-02-15 2014-08-21 Kabushiki Kaisha Toshiba Semiconductor device
US9117738B2 (en) * 2013-02-15 2015-08-25 Kabushiki Kaisha Toshiba Interconnection of semiconductor device with graphene wire
US9755071B1 (en) 2016-06-30 2017-09-05 International Business Machines Corporation Merged gate for vertical transistors
US11856799B2 (en) 2017-08-31 2023-12-26 Micron Technology, Inc. Semiconductor devices, hybrid transistors, and related methods
US11335788B2 (en) 2017-08-31 2022-05-17 Micron Technology, Inc. Semiconductor devices, transistors, and related methods for contacting metal oxide semiconductor devices
US10943953B2 (en) 2017-08-31 2021-03-09 Micron Technology, Inc. Semiconductor devices, hybrid transistors, and related methods
US11908913B2 (en) 2017-08-31 2024-02-20 Micron Technology, Inc. Semiconductor devices, transistors, and related methods for contacting metal oxide semiconductor devices
US12015089B2 (en) * 2018-08-27 2024-06-18 Micron Technology, Inc. Transistors comprising two-dimensional materials and related memory cells and electronic devices
US11121258B2 (en) * 2018-08-27 2021-09-14 Micron Technology, Inc. Transistors comprising two-dimensional materials and related semiconductor devices, systems, and methods
US20200066917A1 (en) * 2018-08-27 2020-02-27 Micron Technology, Inc. Transistors comprising two-dimensional materials and related semiconductor devices, systems, and methods
US20210408297A1 (en) * 2018-08-27 2021-12-30 Micron Technology, Inc. Transistors comprising two-dimensional materials and related memory cells and semiconductor devices
US11282833B2 (en) 2018-11-16 2022-03-22 Samsung Electronics Co., Ltd. Semiconductor device
US11189588B2 (en) 2018-12-31 2021-11-30 Micron Technology, Inc. Anisotropic conductive film with carbon-based conductive regions and related semiconductor assemblies, systems, and methods
US11881468B2 (en) 2018-12-31 2024-01-23 Micron Technology, Inc. Anisotropic conductive film with carbon-based conductive regions and related semiconductor device assemblies and methods
US11749608B2 (en) 2018-12-31 2023-09-05 Micron Technology, Inc. Device packages including redistribution layers with carbon-based conductive elements, and methods of fabrication
US10854549B2 (en) 2018-12-31 2020-12-01 Micron Technology, Inc. Redistribution layers with carbon-based conductive elements, methods of fabrication and related semiconductor device packages and systems

Also Published As

Publication number Publication date
EP2748856A2 (en) 2014-07-02
WO2013028685A3 (en) 2013-05-16
KR20140036320A (en) 2014-03-25
US20210273111A1 (en) 2021-09-02
EP2748856A4 (en) 2015-07-29
WO2013028685A2 (en) 2013-02-28
JP5883508B2 (en) 2016-03-15
US11011647B2 (en) 2021-05-18
US10002935B2 (en) 2018-06-19
US20160276454A1 (en) 2016-09-22
US20200027990A1 (en) 2020-01-23
US11652173B2 (en) 2023-05-16
US9356155B2 (en) 2016-05-31
US10446692B2 (en) 2019-10-15
CN103765595A (en) 2014-04-30
US20130049120A1 (en) 2013-02-28
JP2014524672A (en) 2014-09-22
KR101570945B1 (en) 2015-11-20
US20150236164A1 (en) 2015-08-20
US20180301539A1 (en) 2018-10-18
CN103765595B (en) 2017-02-15
EP2748856B1 (en) 2020-12-02

Similar Documents

Publication Publication Date Title
US11652173B2 (en) Methods of forming a semiconductor device comprising a channel material
TWI651850B (en) Vertical-transport finfet device with variable fin pitch
CN105793968B (en) Semiconductor devices including source/drain and gate channels
US20160343708A1 (en) Semiconductor devices and methods of manufacturing the same
CN110678986B (en) Embedded bottom metal contact formed by vertical transistor self-aligned contact process
CN106169439A (en) Wire structures, the method forming wire structures and semiconductor device
US11677026B2 (en) Transistor having wrap-around source/drain contacts
US11024746B2 (en) Gate all-around device
KR20160100210A (en) Vertical gate all around (vgaa) devices and methods of manufacturing the same
US11935890B2 (en) Method for forming integrated semiconductor device with 2D material layer
US11342339B2 (en) Method of making six transistor SRAM cell using connections between 3D transistor stacks
US10615277B2 (en) VFET CMOS dual epitaxy integration
CN115332171A (en) Method for forming integrated circuit
US10453940B1 (en) Vertical field effect transistor with strained channel region extension
US20240105725A1 (en) Cfet with asymmetric source/drain features
US11335599B2 (en) Self-aligned contacts for 3D logic and memory
US20230068854A1 (en) Method of making a plurality of 3d semiconductor devices with enhanced mobility and conductivity
KR20240034102A (en) Integrated circuit devices including a back side power distribution network structure and methods of forming the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SANDHU, GURTEJ S.;REEL/FRAME:026793/0902

Effective date: 20110822

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

CC Certificate of correction
AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001

Effective date: 20160426

AS Assignment

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT, MARYLAND

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL

Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001

Effective date: 20160426

AS Assignment

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT, CALIFORNIA

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:043079/0001

Effective date: 20160426

AS Assignment

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, ILLINOIS

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

Owner name: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT, IL

Free format text: SECURITY INTEREST;ASSIGNORS:MICRON TECHNOLOGY, INC.;MICRON SEMICONDUCTOR PRODUCTS, INC.;REEL/FRAME:047540/0001

Effective date: 20180703

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:047243/0001

Effective date: 20180629

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4

AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT;REEL/FRAME:050937/0001

Effective date: 20190731

AS Assignment

Owner name: MICRON SEMICONDUCTOR PRODUCTS, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT;REEL/FRAME:051028/0001

Effective date: 20190731

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 8