CN101783366A - Preparation method of graphene MOS transistor - Google Patents
Preparation method of graphene MOS transistor Download PDFInfo
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- CN101783366A CN101783366A CN201010111271A CN201010111271A CN101783366A CN 101783366 A CN101783366 A CN 101783366A CN 201010111271 A CN201010111271 A CN 201010111271A CN 201010111271 A CN201010111271 A CN 201010111271A CN 101783366 A CN101783366 A CN 101783366A
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Abstract
The invention belongs to the technical field of semiconductor devices and particularly discloses a preparation method of a graphene MOS transistor, which is as follows: firstly intrinsic grapheme is processed through hydrogen plasma to obtain hydrogenated graphene, and then the large pi bonds of the graphene are destructed through the method of atomic layer metallic oxide deposition. In this way, the forbidden gap of the graphene can be effectively expanded and the gate leakage current in the graphene MOS transistor can be reduced. Meanwhile, the graphene with no metallic oxide deposition can maintain the semimetal property to be used as the source electrode and the drain electrode of the graphene MOS transistor, thus reducing the contact resistance between the source electrode and the channel. The preparation method is compatible with the existing CMOS technique and makes large grapheme-based integrated circuits possible.
Description
Technical field
The invention belongs to technical field of semiconductor device, be specifically related to a kind of MOS transistor and preparation method thereof, particularly a kind of method of using Graphene to prepare the high speed nanometer MOS transistor of source electrode and drain electrode belongs to field of semiconductor devices.
Background technology
Graphene (Graphene) is a kind of monolayer carbon atom film that separates from graphite material, each carbon atom is connected mutually with the sp2 hybridized orbit on two dimensional surface, just form three σ keys between three of each carbon atom and arest neighbors carbon atoms, a remaining p electron orbit is perpendicular to the Graphene plane, with the π of atom formation on every side key, surround orthohexagonal plane honeycombed structure between carbon atom mutually, on same atomic plane, have only two kinds of atoms that the locus is different like this, as Fig. 1.Graphene has zero forbidden band characteristic, even at room temperature mean free path and the coherence length of charge carrier in Graphene also can reach micron order, simultaneously, Graphene also has more than the high carrier mobility of silicon, so it is a kind of semi-conducting material of excellent performance, and because its unique two-dimensional structure, compare the easier realization large-area planar of CNT (carbon nano-tube) Graphene device, thereby obtained the extensive concern of scientific circles, be considered to be expected to continue in the integrated circuit of future generation the important materials of Moore's Law.
As novel semi-conducting material, Graphene has been applied in MOS (Metal-Oxide-Semiconductor, the Metal-oxide-semicondutor) transistor.The transistor technology of employing standard at first carves raceway groove with electron beam on the mono-layer graphite film, the core that is called as " island " then remaining is enclosed electronics, forms quantum dot.The structure of Graphene transistor gate part is the dielectric that the quantum dot of nanometer more than 10 clips several nanometers.This quantum dot often is called as " charge-islands ".Because understand the conductivity that changes this quantum dot after applying voltage, so quantum dot can be remembered transistorized logic state as the field-effect transistor that is same as standard.
Yet because the energy gap of Graphene is little, exists with the semimetal form under the free situation, thereby in graphene MOS transistor, exist the excessive problem of cut-off current, limited its further development.The mode in traditional broadening forbidden band comprises Graphene cut into fine strip shape, perhaps is modified into zigzag by the edge or armchair shape is realized.But these modes have quite high requirement to the accuracy of manufacture, have limited the integrated on a large scale of graphene MOS transistor.
Summary of the invention
The objective of the invention is to propose a kind of novel graphene MOS transistor, this graphene MOS transistor can improve the excessive problem of cut-off current that exists in the conventional graphite alkene MOS transistor.
For reaching above-mentioned purpose of the present invention, the present invention proposes a kind of graphene MOS transistor, comprises grid region, source region, drain region and channel region.Described grid region and channel region are between described source region and drain region, and described grid region is positioned on the described channel region, has one deck gate medium between described grid region and the channel region.The material that constitutes described gate medium is Al
2O
3, SiO
2Etc. the insulated by oxide medium.The material that constitutes described grid region is TiN, RuO
2, Ru or other metal.The material that constitutes described source region and drain region is the intrinsic Graphene.The material that constitutes described channel region is the hydrogenation Graphene contacted with described gate medium.
Further, the present invention proposes the manufacture method of above-mentioned graphene MOS transistor, comprise the steps:
Under low pressure, utilize H
2/ Ar mixed gas plasma hydrogenation treatment intrinsic Graphene surface obtains the hydrogenation Graphene;
Resulting hydrogenation Graphene is distributed in semiconductor substrate surface;
Utilize the method for atomic layer deposition, the gate medium of growing selectively on the surface of hydrogenation Graphene;
Growth layer of metal grid material constitutes the grid region of device on described gate medium;
Utilize annealing technology, the hydrogenation Graphene that does not contact with described gate medium is returned intrinsic Graphene state.
Described H
2H in the/Ar mist
2Volumetric concentration be 10%-30%, the hydrogenation treatment time is greater than 2 hours, as 2-3 hour.Described Semiconductor substrate is the substrate of monocrystalline silicon, polysilicon, silicon-on-insulator (SOI) or other material, also can comprise other prepared thin layer thereon, such as SiO
2Dielectric layer.Described gate dielectric material is Al
2O
3, SiO
2Etc. the insulated by oxide medium.Described metal gate material is TiN, RuO
2, Ru or other material metal.The intrinsic Graphene of described annealing back reduction constitutes the source region and the drain region of device.
Can effectively expand the energy gap of Graphene by method of the present invention, thereby can reduce the grid leakage current in the graphene MOS transistor, in addition, as source region in the MOS transistor and drain region, can reduce the contact resistance of source leakage and raceway groove with the intrinsic Graphene.Way of the present invention and existing CMOS process compatible can be used for following extensive graphene-based integrated circuit simultaneously.
Description of drawings
Fig. 1 is the atomic structure schematic diagram of intrinsic Graphene.
Fig. 2 to Fig. 6 is the forming process schematic diagram of a kind of graphene MOS transistor embodiment provided by the invention.
Fig. 3 b, Fig. 4 b, Fig. 5 b and Fig. 6 b are respectively the sectional views of structure shown in Fig. 3 a, Fig. 4 a, Fig. 5 a and Fig. 6 a.
Fig. 2 b is the atomic structure schematic diagram that is formed the hydrogenation Graphene by the intrinsic Graphene.
Fig. 4 c and Fig. 4 d are respectively and SiO
2And Al
2O
3The energy band diagram of the hydrogenation Graphene after the contact.
Embodiment
Below with reference to accompanying drawings an exemplary embodiment of the present invention is elaborated.In the drawings, for convenience of description, amplify or dwindled the thickness in layer and zone, shown in size do not represent actual size.Although the actual size that reflects device that these figure can not entirely accurate, their zones that still has been complete reflection and form mutual alignment between the structure, particularly form between the structure up and down and neighbouring relations.Reference diagram is the schematic diagram of idealized embodiment of the present invention, and embodiment shown in the present should not be considered to only limit to the given shape in zone shown in the figure, but comprises resulting shape, the deviation that causes such as manufacturing.For example the curve that obtains of etching has crooked or mellow and full characteristics usually, but in embodiments of the present invention, all represents with rectangle, and the expression among the figure is schematically, but this should not be considered to limit the scope of the invention.
At first, under the air pressure of about 100 handkerchiefs, utilize H
2Volumetric concentration is the H of 10%-30%
2/ Ar mixed gas plasma is handled intrinsic Graphene surface, makes that in greater than 2 hours time the hydrogenation of intrinsic Graphene is saturated, obtains the hydrogenation Graphene, as Fig. 2 a, shown in 201 be the intrinsic Graphene, shown in 202 be the hydrogenation Graphene.At this moment, the carbon atom in the intrinsic Graphene changes sp3 hydridization into from sp2 hydridization, atomic diagram such as Fig. 2 b, shown in 21,22 and 23 be carbon atom, shown in 24 be hydrogen atom.
Next, the hydrogenation Graphene that obtains is distributed on Semiconductor substrate 200 surfaces, and as Fig. 3 a, semi-simple body substrate 200 is the substrate of monocrystalline silicon, polysilicon, silicon-on-insulator (SOI) or other material, also can comprise other prepared thin layer thereon, such as SiO
2Dielectric layer.
Next, utilize the method for atomic layer deposition (ALD), one deck gate medium 203 of growing selectively on the surface of hydrogenation Graphene 202, gate medium 203 is such as being Al
2O
3Perhaps SiO
2, as Fig. 3 a, Fig. 3 b is the sectional view of structure shown in Fig. 3 a.By the growing principle of atomic layer deposition as can be known, the hydrogenation Graphene part that contacts with gate medium 203 can slough a hydrogen ion and with oxygen atom Cheng Jian.According to analog result, shown in Fig. 3 c and 3d, with SiO
2And Al
2O
3Being with of hydrogenation Graphene after the contact is broadened respectively to 0.9eV and 1.8eV.
Again next, growth layer of metal grid material 204 on gate medium 203, metal gate material 304 can be TiN, RuO
2, Ru or other metal.
At last, under 450 ℃, use Ar annealing 24 hours, make the hydrogenation Graphene that does not contact with gate medium 203 revert to the intrinsic state, the intrinsic Graphene of metalline can be used as the source region 205 and the drain region 206 of MOS transistor.
Such graphene MOS transistor structure has just formed.
As mentioned above, under the situation that does not depart from spirit and scope of the invention, can also constitute many very embodiment of big difference that have.Should be appreciated that except as defined by the appended claims, the invention is not restricted at the instantiation described in the specification.
Claims (10)
1. graphene MOS transistor, comprise grid region, source region, drain region and channel region, it is characterized in that described grid region and channel region are between described source region and drain region, described grid region is positioned on the described channel region, has one deck gate medium between described grid region and the channel region.
2. graphene MOS transistor according to claim 1 is characterized in that, the material that constitutes described gate medium is Al
2O
3Or SiO
2
3. graphene MOS transistor according to claim 1 is characterized in that, the material that constitutes described grid region is TiN, RuO
2Or Ru.
4. graphene MOS transistor according to claim 1 is characterized in that, the material that constitutes described source region and drain region is the intrinsic Graphene.
5. graphene MOS transistor according to claim 1 is characterized in that the material that constitutes described channel region is the hydrogenation Graphene contacted with described gate medium.
6. the manufacture method of a graphene MOS transistor is characterized in that, comprises the steps:
Under low pressure, utilize H
2/ Ar mixed gas plasma hydrogenation treatment intrinsic Graphene surface obtains the hydrogenation Graphene;
Resulting hydrogenation Graphene is distributed in semiconductor substrate surface;
Utilize the method for atomic layer deposition, the gate medium of growing selectively on the surface of hydrogenation Graphene;
Growth layer of metal grid material constitutes the grid region of device on described gate medium;
Utilize annealing technology, the hydrogenation Graphene that does not contact with described gate medium is returned intrinsic Graphene state; This Graphene constitutes source region and drain region.
7. manufacture method according to claim 6 is characterized in that, described H
2H in the/Ar mist
2Volumetric concentration be 10%-30%, the hydrogenation treatment time was greater than 2 hours.
8. manufacture method according to claim 6 is characterized in that, described Semiconductor substrate is monocrystalline silicon, polysilicon or silicon-on-insulator.
9. manufacture method according to claim 6 is characterized in that, described gate dielectric material is Al
2O
3Or SiO
2
10. manufacture method according to claim 6 is characterized in that, described metal gate material is TiN, RuO
2Or Ru.
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| CN201010111271A CN101783366A (en) | 2010-02-11 | 2010-02-11 | Preparation method of graphene MOS transistor |
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| CN201010111271A CN101783366A (en) | 2010-02-11 | 2010-02-11 | Preparation method of graphene MOS transistor |
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| CN101941696A (en) * | 2010-09-15 | 2011-01-12 | 复旦大学 | Nanolithographic method applied to manufacture of graphene-based field effect tube |
| CN102054869A (en) * | 2010-09-17 | 2011-05-11 | 中国科学院微电子研究所 | Graphene device and manufacturing method thereof |
| CN102097297A (en) * | 2010-11-16 | 2011-06-15 | 复旦大学 | Method for depositing high k gate dielectrics on atomic layer on graphene surface by adopting electric field induction |
| CN102184849A (en) * | 2011-04-27 | 2011-09-14 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing graphene-based field effect transistor |
| CN102184858A (en) * | 2011-04-07 | 2011-09-14 | 复旦大学 | Preparation method of graphene field effect transistor |
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