US8951848B2 - Circuit substrate for mounting chip, method for manufacturing same and chip package having same - Google Patents
Circuit substrate for mounting chip, method for manufacturing same and chip package having same Download PDFInfo
- Publication number
- US8951848B2 US8951848B2 US13/771,320 US201313771320A US8951848B2 US 8951848 B2 US8951848 B2 US 8951848B2 US 201313771320 A US201313771320 A US 201313771320A US 8951848 B2 US8951848 B2 US 8951848B2
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- US
- United States
- Prior art keywords
- layer
- chip
- conductive pads
- circuit board
- electrically conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 title claims description 33
- 239000000758 substrate Substances 0.000 title description 13
- 229910000679 solder Inorganic materials 0.000 claims abstract description 56
- 238000009413 insulation Methods 0.000 claims abstract description 30
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 36
- 238000007747 plating Methods 0.000 claims description 29
- 239000011889 copper foil Substances 0.000 claims description 17
- 239000003351 stiffener Substances 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 5
- 239000010931 gold Substances 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 150000001875 compounds Chemical class 0.000 claims description 4
- 238000000465 moulding Methods 0.000 claims description 4
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 2
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 111
- 238000000576 coating method Methods 0.000 description 13
- 239000011248 coating agent Substances 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- -1 Polyethylene Terephthalate Polymers 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000011112 polyethylene naphthalate Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12042—LASER
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15182—Fan-in arrangement of the internal vias
- H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present disclosure relates to a circuit substrate for mounting a microchip, a method for manufacturing the circuit substrate, and a chip package structure having the circuit substrate.
- chip packages may include a circuit substrate and a chip.
- the PCB is configured to form a connecting pad.
- Most of the circuit substrates include a plurality of patterned electrically conductive layers, which make the circuit substrate thick.
- FIG. 1 is a cross-sectional view of a flexible single-sided copper clad laminate in accordance with a first exemplary embodiment, comprising an insulation layer and a copper foil formed on the insulation layer.
- FIG. 2 shows through holes defined in the insulation layer of the flexible single-sided copper clad laminate of FIG. 1 .
- FIG. 3 shows two etch-resistant coatings formed on opposite sides of the flexible single-sided copper clad laminate of FIG. 2 .
- FIG. 4 shows the copper foil of FIG. 3 converted into a patterned electrically conductive layer and the two etch-resistant coatings removed.
- FIG. 5 shows a solder mask layer formed on the patterned electrically conductive layer of FIG. 4 , and a plurality of openings defined in the solder mask layer for exposing part of the patterned electrically conductive layer, thereby forming a plurality of conductive pads.
- FIG. 6 shows a seed layer formed on a surface of the insulation layer of FIG. 5 facing away from the patterned electrically conductive layer, an inner surface of the through hole and a surface of the patterned electrically conductive layer in the through hole using a sputtering process.
- FIG. 7 shows a stiffener stacked on the seed layer of FIG. 6 .
- FIG. 8 shows a surface plating layer formed on each of the conductive pads of FIG. 7 , thereby obtaining a circuit substrate.
- FIG. 9 shows a chip mounted on the circuit substrate of FIG. 8 through a wire-bonding method.
- FIG. 11 shows the stiffer of FIG. 10 removed.
- FIG. 12 shows the seed layer of FIG. 11 removed.
- FIG. 13 shows a solder bump in each of the through holes of FIG. 12 and electrically connected to the patterned electrically conductive layer in the through hole, and the solder bumps projected out of the through hole, thereby obtaining a chip package.
- FIG. 14 is a cross-sectional view of a chip package in accordance with a second exemplary embodiment.
- FIGS. 1-13 show a method for manufacturing a chip package in accordance with a first exemplary embodiment. The method includes the following steps.
- FIGS. 1-4 show a flexible single-sided circuit board 10 .
- the flexible single-sided circuit board 10 includes an insulation layer 11 and an patterned electrically conductive layer 12 formed on the insulation layer 11 .
- the insulation layer 11 has a first surface 111 , an opposite second surface 112 , and a plurality of through holes 13 passing through the first surface 111 and the second surface 112 .
- the patterned electrically conductive layer 12 is formed on the first surface 111 of the insulation layer 11 , and covers the through holes 13 .
- a flexible single-sided copper clad laminate (CCL) 10 a is provided.
- the flexible single-sided CCL 10 a includes the insulation layer 11 and a copper foil 14 .
- the copper foil 14 is formed on the first surface 111 of the insulation layer 11 .
- a material of the insulation layer 11 can be selected from the group consisting of Polyimide (PI), Polyethylene Terephthalate (PET) and Polyethylene Naphthalate (PEN).
- a thickness of the insulation layer 11 can be in the range from 15 ⁇ m to 250 ⁇ m, and preferably from 25 ⁇ m to 50 ⁇ m.
- a thickness of the copper foil 14 can be in the range from 12 ⁇ m to 35 ⁇ m.
- FIG. 2 shows that the through holes 13 are formed using a laser bombarding method or a drilling method.
- the through holes 13 pass through the first surface 111 and the second surface 112 , and terminate at the copper foil 14 , thus the copper foil 14 is exposed to the through holes 13 .
- each through hole 13 has a round cross section.
- FIGS. 3-4 show that the copper foil 14 is partly removed.
- the removing of the copper foil 14 forms the patterned electrically conductive layer 12 .
- the patterned electrically conductive layer 12 covers the through holes 13 .
- the patterned electrically conductive layer 12 has a plurality of portions exposed in the through holes 13 to sever as a plurality of first conductive pads 121 .
- the patterned electrically conductive layer 12 can be formed by using exposure, developing, and etching methods. An example of a method for forming the patterned electrically conductive layer 12 is described in detail as follows:
- a first etch-resistant coating 113 is formed on the copper foil 14
- a second etch-resistant coating 114 is formed on the second surface 112 of the insulation layer 11 .
- the first etch-resistant coating 113 covers the entire surface of the copper foil 14
- the second etch-resistant coating 114 covers the entire second surface 112 and openings of the through holes 13 .
- the first and second etch-resistant coatings 113 and 114 are a dry-film type.
- the second etch-resistant coating 114 prevents the copper foil 14 in the through holes 13 from being etched by etchant applied in a following step.
- the second etch-resistant coating 114 covers the openings of all through holes 13 and part of the second surface 112 .
- the first and second etch-resistant coatings 113 and 114 can also be a wet-film type.
- the first etch-resistant coating 113 is patterned by being partly exposed to a UV light and then being developed, thus part of the copper foil 14 is exposed. Furthermore, the exposed copper foil 14 is removed by an etching method. Finally, the remaining first etch-resistant coating 113 and the second etch-resistant coating 114 are removed by a stripping process, thereby obtaining the flexible single-sided circuit board 10 .
- FIG. 5 shows that a solder mask layer 15 is formed on the patterned electrically conductive layer 12 and the first surface 111 not covered by the patterned electrically conductive layer 12 .
- the solder mask layer 15 defines a plurality of openings 162 for exposing part of the patterned electrically conductive layer 12 .
- the patterned electrically conductive layer 12 exposed to the openings 162 serves as a plurality of second conductive pads 16 .
- the second conductive pads 16 are respectively electrically connected to the first conductive pads 121 .
- a material of the solder mask layer 15 can be liquid photoimageable solder resist ink or thermosetting solder resist ink.
- steps ( 1 )-( 2 ) can be a roll-to-roll process.
- FIGS. 6-8 shows that a seed layer 18 is formed on the second surface 112 , the inner surface of the through hole 13 and surfaces of the first conductive pads 121 in the through hole 13 .
- a stiffener 115 is arranged on the seed layer 18 formed on the second surface 112 .
- the stiffener 115 covers the second surface 112 and openings of the through holes 13 at the second surface 112 .
- a surface plating layer 161 is formed on each of the second conductive pads 16 , thereby obtaining a circuit substrate 20 .
- FIG. 6 shows that the seed layer 18 is formed on the second surface 112 , the inner surface of the through hole 13 and surfaces of the first conductive pads 121 in the through hole 13 using a sputtering process.
- the seed layer 18 is electrically connected to the patterned electrically conductive layer 12 .
- an electroless copper plating method can also form the seed layer 18 .
- a thickness of the seed layer 18 can be in the range from 5 ⁇ m to 15 ⁇ m.
- FIG. 7 shows that the stiffener 115 is attached to the second surface 112 .
- the stiffener 115 can be attached to the second surface 112 by an adhesive sheet.
- the stiffener 115 reinforces the rigidity of flexible single-sided circuit board 10 in the sequent process.
- the stiffener 115 also prevents the seed layer 18 from being plated gold in a following plating step.
- the stiffener 18 can be a stiffening board comprising a material selected from the group consisting of epoxy resin, phenolic resin, metal and any combination thereof.
- FIG. 8 shows that the surface plating layer 161 is formed by gold plating, thereby protecting the second conductive pads 16 from oxidation and is beneficial for linking golden wires when mounting a chip using a wire-bonding method.
- the surface plating layer 161 can also be formed by nickel gold plating, nickel palladium gold plating, or tin plating. Certainly, the surface plating layer 161 can also be omitted.
- the circuit board 20 includes an insulation layer 11 , an patterned electrically conductive layer 12 formed the first surface 111 of the insulation layer 11 , and a solder mask layer 15 .
- the insulation layer 11 defines a plurality of through holes 13 passing through the second surface 112 and the first surface 111 of the insulation layer 11 .
- the patterned electrically conductive layer 12 covers the through holes 13 at the first surface 111 .
- the patterned electrically conductive layer 12 in the through hole forms a plurality of first conductive pads 121 .
- a seed layer 18 is formed over the second surface 112 , inner surfaces of the through holes 13 and the first conductive pads 121 exposed in the through holes 13 .
- a stiffener 115 is attached to on the seed layer 18 on the second surface 112 , and covers the through holes 13 at the second surface 112 .
- the solder mask layer 15 is formed on the patterned electrically conductive layer 12 and the first surface 111 not covered by the patterned electrically conductive layer 12 .
- the solder mask layer 15 defines a plurality of openings 162 for exposing part of the patterned electrically conductive layer 12 .
- the patterned electrically conductive layer 12 is exposed to the openings 162 forming a plurality of second conductive pads 16 .
- the second conductive pads 16 are respectively electrically connected to the first conductive pads 121 .
- a surface plating layer 161 is formed on each of the second conductive pads 16 .
- the golden wires 32 are electrically connected with the chip 30 , and correspond to the second conductive pads 16 .
- the chip 30 is fixed to a surface of the solder mask layer 15 through an adhesive layer 31 , and the golden wires 32 are welded to the surface plating layer 161 .
- the molding compound can be epoxy molding compound.
- the stiffener 115 can be removed using a stripping technology.
- the seed layer 18 can be removed using etching.
- the end portion of the solder ball 46 can also be cylindrical or ellipsoid-shaped.
- a material of the solder ball 46 can be comprised of tin.
- the solder balls 46 can be formed using screen printing or plating.
- the chip package 50 includes an insulation layer 11 , an patterned electrically conductive layer 12 formed the first surface 111 of the insulation layer 11 , a solder mask layer 15 , a chip 30 , an encapsulating layer 40 and a plurality of solder balls 46 .
- the insulation layer 11 defines a plurality of through holes 13 passing through the second surface 112 and the first surface 111 of the insulation layer 11 .
- the patterned electrically conductive layer 12 covers the through holes 13 at the first surface 111 .
- the patterned electrically conductive layer 12 in the through hole forms a plurality of first conductive pads 121 .
- the solder mask layer 15 is formed on the patterned electrically conductive layer 12 and the first surface 111 not covered by the patterned electrically conductive layer 12 .
- the solder mask layer 15 defines a plurality of openings 162 for exposing part of the patterned electrically conductive layer 12 .
- the patterned electrically conductive layer 12 exposed to the openings 162 forms a plurality of second conductive pads 16 .
- the second conductive pads 16 are respectively electrically connected to the first conductive pads 121 .
- a surface plating layer 161 is formed on each of the second conductive pads 16 .
- the solder balls 46 are respectively formed in the through holes 13 and protrude from the second surface 112 .
- the solder balls 46 are respectively electrically connected to the first conductive pads 121 .
- the chip 30 is fixed on the solder mask layer 15 through an adhesive layer 31 .
- the chip 30 is electrically connected to the surface plating layers 161 on the second conductive pads 16 through a plurality of golden wires 32 .
- the golden wires 32 correspond to the second conductive pads 16 .
- the golden wires 32 , the chip 30 , the solder mask layer 15 , and the surface plating layer 161 are encapsulated in the encapsulating layer 40 .
- the circuit board 20 and the chip package 50 just include a single patterned electrically conductive layer 12 .
- the circuit board 20 and the chip package 50 are thinner, and the methods of manufacturing are easier.
- the chip 30 a is fixed to the circuit board 20 using a flip-chip method.
- the chip 30 a includes a plurality of contact bumps 32 a corresponding to the second conductive pads 16 .
- a plurality of solder bumps 161 a are formed on the surface plating layer 161 on the second conductive pads 16 .
- the chip 30 a is positioned on the circuit substrate 20 in a manner that the contact bumps 32 a contact the corresponding solder bumps 161 a . Then each of the contact bumps 32 a and the corresponding solder bumps 161 a are melted using a reflow soldering to form the solder bump 34 a having a single continuous body of material.
- the solder bumps 161 a can be formed using screen printing or plating.
- the solder bumps 161 a projects beyond the surface of the solder mask layer 15 .
- An end portion of each of the solder bumps 161 a can be cylindrical or ball-shaped.
- a material of the solder bump 161 a can be comprised of tin.
- the underfill layer 40 a firmly fixes the chip 30 a to the circuit board 20 .
- the underfill is filed through a capillary action of the gap between the bottom surface 42 a of the chip 30 a and the surface of the solder mask layer 15 when the underfill is arranged at the opening of the gap.
- the underfill layer 40 a can be comprised of an epoxy resin, such as Loctite 3536.
- a chip package 60 is obtained.
- the chip package 60 is similar to the chip package 50 of the first exemplary embodiment.
- the distinguishing features are that the chip package 60 includes a chip 30 a instead of the chip 30 in the first exemplary embodiment.
- the chip 30 a is electrically connected to the surface plating layers 161 on the second conductive pads 16 with a plurality of solder bumps 34 a .
- the gap between a bottom surface 42 a of the chip 30 a and the surface of the solder mask layer 15 is filled with the underfill layer 40 a , thereby firmly fixing the chip 30 a to the circuit board 20 .
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Structure Of Printed Boards (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
Claims (6)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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CN201210261162.1A CN103579128B (en) | 2012-07-26 | 2012-07-26 | Chip package base plate, chip-packaging structure and preparation method thereof |
CN2012102611621 | 2012-07-26 |
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US20140027893A1 US20140027893A1 (en) | 2014-01-30 |
US8951848B2 true US8951848B2 (en) | 2015-02-10 |
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US13/771,320 Active 2033-05-13 US8951848B2 (en) | 2012-07-26 | 2013-02-20 | Circuit substrate for mounting chip, method for manufacturing same and chip package having same |
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US (1) | US8951848B2 (en) |
CN (1) | CN103579128B (en) |
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TWI736093B (en) | 2019-12-31 | 2021-08-11 | 財團法人工業技術研究院 | Package structure |
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Also Published As
Publication number | Publication date |
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CN103579128A (en) | 2014-02-12 |
TWI483363B (en) | 2015-05-01 |
US20140027893A1 (en) | 2014-01-30 |
TW201405745A (en) | 2014-02-01 |
CN103579128B (en) | 2016-12-21 |
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