US8841205B2 - Manufacturing method and apparatus for semiconductor device - Google Patents

Manufacturing method and apparatus for semiconductor device Download PDF

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US8841205B2
US8841205B2 US13/217,736 US201113217736A US8841205B2 US 8841205 B2 US8841205 B2 US 8841205B2 US 201113217736 A US201113217736 A US 201113217736A US 8841205 B2 US8841205 B2 US 8841205B2
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processing
wafers
characteristic
measured value
lot
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US20120052600A1 (en
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Masaki Kamimura
Takashi Shimizu
Kunihiro Miyazaki
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Toshiba Corp
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Toshiba Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/418Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
    • G05B19/41875Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM] characterised by quality surveillance of production
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/30Nc systems
    • G05B2219/32Operator till task planning
    • G05B2219/32194Quality prediction
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/30Nc systems
    • G05B2219/32Operator till task planning
    • G05B2219/32198Feedforward inspection data for calibration, manufacturing next stage
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/30Nc systems
    • G05B2219/45Nc applications
    • G05B2219/45031Manufacturing semiconductor wafers
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • Embodiments described herein related generally to a manufacturing method and apparatus for a semiconductor device.
  • variations occur in wafer machining. Examples thereof include variations in film thickness in a film formation step and variations in machining size such as an opening diameter in an etching step.
  • FIG. 1 is a diagram showing a configuration of a manufacturing apparatus for a semiconductor device according to an embodiment
  • FIG. 2 is a flowchart showing a manufacturing process of a semiconductor device according to the embodiment
  • FIG. 3A is a diagram showing an example of a film thickness distribution according to the embodiment.
  • FIG. 3B is a diagram showing an example of a characteristic distribution according to the embodiment.
  • FIG. 4 is a diagram showing a correlation between a device characteristic and a film thickness according to the embodiment.
  • FIG. 5A is a diagram showing an example of a film thickness distribution according to the embodiment.
  • FIG. 5B is a diagram showing an example of a characteristic distribution according to the embodiment.
  • FIG. 6A is a diagram showing a conventional characteristic distribution
  • FIG. 6B is a diagram showing an example of a characteristic distribution according to the embodiment.
  • FIG. 7 is a diagram showing a configuration of a manufacturing apparatus for a semiconductor device according to an embodiment
  • FIG. 8 is a flowchart showing a manufacturing process of a semiconductor device according to the embodiment.
  • FIGS. 9A to 9C are diagrams each showing a film thickness distribution according to the embodiment.
  • FIG. 9D is a diagram showing a film thickness distribution according to a comparative example.
  • a manufacturing method for a semiconductor device includes: performing first processing on a plurality of wafers in a first processing order in a first processing apparatus; obtaining a processed amount with respect to each of the plurality of wafers in the first processing; obtaining a processed amount with respect to each of the plurality of wafers by second processing in a second processing apparatus after the first processing; deciding a second processing order, which is different from the first processing order, from the processed amount with respect to each of the plurality of wafers by the first processing and the processed amount with respect to each of the plurality of wafers by the second processing; and performing the second processing on the plurality of wafers in the second processing order in the second processing apparatus.
  • FIG. 1 shows a configuration of a manufacturing apparatus for a semiconductor device according to a present embodiment.
  • the manufacturing apparatus includes a batch film forming apparatus 11 A as a first processing apparatus which arranges 25 wafers w constituting one lot respectively in predetermined processed positions (processing order), to perform first processing, a wafer sorter 12 as a processing order changing mechanism which sorts the wafers w after completion of the first processing, and a batch film forming apparatus 11 B as a second processing apparatus which performs second processing on the plurality of wafers w in processed positions sorted by the wafer sorter 12 .
  • a batch film forming apparatus 11 A as a first processing apparatus which arranges 25 wafers w constituting one lot respectively in predetermined processed positions (processing order), to perform first processing
  • a wafer sorter 12 as a processing order changing mechanism which sorts the wafers w after completion of the first processing
  • a batch film forming apparatus 11 B as a second processing apparatus which performs second processing on the plurality of wafers
  • wafers are placed, for example, on quartz boats (not shown) arranged in a vertical direction with predetermined intervals.
  • the wafers w are transferred among the batch film forming apparatuses 11 A and 11 B, and wafer sorter 12 , for example, via an FOUP (Front Open Unified Pod) 13 provided with slots that house the respective wafers w.
  • FOUP Front Open Unified Pod
  • a film thickness measuring device 14 which measures a film thickness as a machined amount in each of the batch film forming apparatuses 11 A and 11 B, configured to obtain a film thickness distribution.
  • the film thickness measuring device 14 is connected with a storage device 15 .
  • the storage device 15 stores accumulated data on the film thickness distribution measured in the film thickness measuring device 14 in the past, film thickness data that is measured and updated, correlation data between the film thickness and a device characteristic (threshold voltage V th , etc.), lot information on the wafers w to be processed, and the like.
  • the lot information is made up of a wafer name, a product name, design information on a substrate to be produced, and the like, and stored in the form of database.
  • the storage device 15 is connected with a computing mechanism 16 that obtains a film thickness distribution as fluctuations in machined amount and a characteristic distribution based on the past accumulated data, the correlation data between the film thickness and the device characteristic, and the like.
  • the data obtained by the computing mechanism 16 is stored into the storage device 15 .
  • the storage device 15 is further connected with a control mechanism 17 .
  • a control mechanism 17 In the control mechanism 17 , optimal wafer processing conditions and processing order are obtained based on the data stored in the storage device 15 .
  • the optimal wafer processing conditions and processing order may also be obtained in the computing mechanism 16 .
  • the control device 17 controls the batch film forming apparatuses 11 A and 11 B, and the wafer sorter 12 which are connected to the control device 17 , based on the obtained processing conditions and processing order.
  • wafers in one lot are, for example, processed as in the following manner.
  • FIG. 2 shows a flowchart.
  • the wafers w in one lot machined in a previous step are arranged so as to be in the first processed positions, and introduced into the batch film forming apparatus 11 A by means of the FOUP 13 , while the processing conditions are optimized in the control mechanism 17 based on the lot information stored in the storage device 15 (Step 1 - 1 ).
  • the 25 wafers in one lot are respectively provided, for example, with ID numbers of 1 to 25 sequentially from the bottom of the first processed positions.
  • a first insulating film such as a TEOS (Tetra EthOxy Silane) film to be a first gate side wall is formed on a wafer with a gate electrode formed thereon as the first processing (Step 1 - 2 ).
  • a film thickness of the first insulating film as a machined amount of each wafer in the processed lot is sequentially measured in the film thickness measuring device 14 , and fluctuations in film thickness (film thickness distribution) inside the lot corresponding to the processed positions of the batch film forming apparatus 11 A are obtained.
  • the obtained film thickness distribution is transferred to the storage device 15 and stored into the storage device 15 .
  • FIG. 3A shows an example of the film thickness distribution of the first insulating film. It is found that the film thickness fluctuates in accordance with the processed positions, as shown in FIG. 3A .
  • the film thickness distribution may be predicted from a past measured value in the computing mechanism 16 as in later-mentioned prediction of a characteristic distribution in the batch film forming apparatus 11 B.
  • FIG. 3B shows an example of the characteristic distribution in a threshold voltage V th of an nMOS transistor as a typical characteristic. As shown in FIG. 3B , the distribution indicates a similar tendency to that of the film thickness distribution of the first insulating film shown in FIG. 3A .
  • a second insulating film such as a SiN film to be a second gate side wall is formed in the batch film forming apparatus 11 B as the second processing.
  • the film thickness fluctuates in accordance with the processed positions as shown in FIG. 5A .
  • a characteristic distribution is obtained based on correlation data between the threshold voltage V th of the nMOS transistor, as an obtained device characteristic and the second insulating film thickness, to result as in FIG. 5B .
  • FIG. 6A shows conventional fluctuations in V th (characteristic distribution) in combination of the first insulating film and the second insulating film as they are based on the above results. It is found that variations in V th are on the order of 30 mV. As thus described, the characteristic greatly fluctuates in accordance with the processed positions, thus increasing the variations.
  • the processing conditions are optimized in the control mechanism 17 based on the data in the storage device 15 , while the processed positions in the batch film forming apparatus 11 B are sorted, and the second processing is then performed.
  • control mechanism 17 for example as shown in Table 1, obtained fluctuation amounts V th (differences from an average value of V th ) in accordance with the processed positions in the batch film forming apparatus 11 A are arranged in a descending order.
  • the characteristic distribution obtained in the batch film forming apparatus 11 B is predicted (Step 1 - 4 ).
  • the processed positions in the batch film forming apparatus 11 B are sorted such that a large one and a small one from the respective fluctuation amounts of V th are combined with each other as shown in Table 3.
  • the processed positions in the batch film forming apparatus 11 B are optimized in the control mechanism 17 such that, from the characteristic distribution in the batch film forming apparatus 11 A and the predicted characteristic distribution in the batch film forming apparatus 11 B, fluctuations in these distributions are offset, to minimize the variations in characteristic (Step 1 - 5 ).
  • the wafers inside the lot are sorted by freely changing the slot positions inside the FOUP 13 in the wafer sorter 12 , so as to be in the optimized processed positions (Step 1 - 6 ).
  • the second insulating film is formed in accordance with the optimized processing conditions and processed positions (Step 1 - 7 ).
  • FIG. 6B shows fluctuations in (characteristic distribution of) V th in combination of the first insulating film and the second insulating film. It is found that the variations in V th are on the order of 10 mV, and can thus be on the order of a third of the conventional one.
  • the processing order in the latter step out of two steps is optimized so as to offset variations in characteristic obtained in machining by the two steps, whereby it is possible to suppress variations in characteristic, and thus improve a manufacturing yield.
  • the present embodiment is similar to the first embodiment in terms of the configuration of the manufacturing apparatus for a semiconductor device, but is different therefrom in that the first processing apparatus is a single-wafer film forming apparatus.
  • FIG. 7 shows a configuration of a manufacturing apparatus for a semiconductor device in the present embodiment.
  • the manufacturing apparatus includes a single-wafer film forming apparatus 71 A as a first processing apparatus which performs first processing on 25 wafers w constituting one lot respectively in a predetermined processing sequence (processing order), a wafer sorter 72 as a processing order changing mechanism which sorts the wafers w, as in the first embodiment, after completion of the first processing, and a batch film forming apparatus 7113 as a second processing apparatus which performs second processing on the plurality of wafers w in processed positions sorted by the wafer sorter 72 .
  • a single-wafer film forming apparatus 71 A as a first processing apparatus which performs first processing on 25 wafers w constituting one lot respectively in a predetermined processing sequence (processing order)
  • a wafer sorter 72 as a processing order changing mechanism which sorts the wafers w, as in the first embodiment, after completion of the first processing
  • the wafers w are transferred among the single-wafer film forming apparatus 71 A, the batch film forming apparatus 71 B and wafer sorter 72 , for example, via an FOUP 73 provided with slots that house the respective wafers w.
  • a film thickness measuring apparatus 74 is provided which measures a film thickness as a machined amount in each of the single-wafer film forming apparatus 71 A and the batch film forming apparatus 71 B, to obtain a film thickness distribution.
  • the film thickness measuring device 74 is connected with a storage device 75 .
  • the storage device 75 stores accumulated data on the film thickness distribution measured in the film thickness measuring device 74 in the past, film thickness data to be measured, correlation data between the film thickness and a device characteristic (threshold voltage V th , etc.), lot information on the wafers w to be processed, and the like.
  • the lot information is made up of a wafer name, a product name, design information on a substrate to be produced, and the like, and stored in the form of database. Further, it is connected, as needed, to the single-wafer film forming apparatus 71 A to store data on standby time and correlation data between the standby time and the film thickness distribution of the single-wafer film forming apparatus 71 A.
  • the storage device 75 is connected with a computing mechanism 76 that obtains a film thickness distribution as fluctuations in machined amount and a characteristic distribution based on the past accumulated data, the correlation data between the film thickness and the device characteristic, and the like.
  • the data obtained by the computing mechanism 76 is stored into the storage device 75 .
  • the storage device 75 is further connected with the control mechanism 77 .
  • the control mechanism 77 In the control mechanism 77 , optimal wafer processing conditions and processing order can be obtained based on the data stored in the storage device 75 .
  • the control mechanism 77 is further connected with the single-wafer film forming apparatus 71 A, the batch film forming apparatus 71 B and the wafer sorter 72 , and controls the single-wafer film forming apparatus 71 A, the batch film forming apparatus 71 B and the wafer sorter 72 based on the obtained processing conditions and processing order.
  • wafers in one lot are, for example, processed as in the following manner.
  • FIG. 8 shows a flowchart.
  • the wafers w in one lot machined in a previous step are loaded into the single-wafer film forming apparatus 71 A by means of a FOUP 73 in the first processing sequence.
  • Data on standby time is acquired by the single-wafer film forming apparatus 71 A (Step 2 - 1 ), which is then transferred to the storage device 75 and stored into the storage device 75 .
  • processing conditions are optimized based on the lot information stored in the storage device 75 (Step 2 - 2 ).
  • the 25 wafers in one lot are respectively provided with, for example, ID numbers of 1 to 25 in the first processing sequence.
  • a first insulating film such as a TEOS film to be a first gate side wall is formed on a wafer with a gate electrode formed thereon as the first processing (Step 2 - 3 ).
  • the wafers w are sequentially processed in a predetermined processing sequence in the single-wafer film forming apparatus 71 A.
  • the film thickness of the first insulating film as a machined amount of each wafer in the processed lot is sequentially measured in the film thickness measuring device 74 , and fluctuations in film thickness (film thickness distribution) inside the lot corresponding to the processing sequence of the batch film forming apparatus 71 A are acquired (Step 2 - 4 ).
  • the obtained film thickness distribution is transferred to the storage device 75 and stored into the storage device 75 .
  • FIG. 9A shows an example of the film thickness distribution of the first insulating film.
  • FIG. 9A shows a case where the time after processing on one wafer until processing on a next wafer by the single-wafer film forming apparatus 71 A (hereinafter referred to as standby time) is long (e.g. about one hour), along with the case of the standby time being short (e.g. about three seconds) due to successive processing or the like, and following FIGS. 9B to 9E also show those cases.
  • standby time the time after processing on one wafer until processing on a next wafer by the single-wafer film forming apparatus 71 A
  • the standby time being short due to successive processing or the like
  • FIGS. 9B to 9E also show those cases.
  • the film thickness distribution fluctuates in accordance with the standby time of the single-wafer film forming apparatus 71 A.
  • the one with the short standby time has small variations in film thickness in accordance with the processing sequence
  • the film thickness distribution varies in accordance with the standby time of the single-wafer film forming apparatus 71 A. This significantly appears on a first wafer in a processed lot as characteristic fluctuations, and the tendency of the fluctuations is specific to each device. Therefore, it is also possible to previously store correlation data between the standby time and the film thickness distribution into the storage device 75 , and predict the film thickness distribution from the standby time data based on the correlation data.
  • processing such as etchback is performed to form the first gate side wall, and thereafter, a second insulating film such as a SiN film to be a second gate side wall is formed in the batch film forming apparatus 71 B as the second processing.
  • a film thickness distribution in accordance with the processing positions of the second insulating film formed by the batch film forming apparatus 71 B is predicted in the computing mechanism 76 (Step 2 - 5 ).
  • the processed positions in the batch film forming apparatus 71 B are optimized in the control mechanism 77 in the first embodiment such that fluctuations in film thicknesses of the first insulating film and the second insulating film are offset, to minimize the variations (Step 2 - 6 ).
  • a processing temperature, processing time and the like at the time of changing the processed positions and forming the second insulating film may be simultaneously controlled, to perform the optimization.
  • the wafers inside the lot are sorted by freely changing the slot positions inside the FOUP 73 in the wafer sorter 72 , so as to be in the optimized processed positions (Step 2 - 7 ).
  • the second insulating film is formed in accordance with the optimized processing conditions and processed positions (Step 2 - 8 ).
  • FIG. 9C shows fluctuations in laminated film thickness of the first insulating film and the second insulating film (laminated film thickness distribution). It is found that as compared with a case shown in FIG. 9D where the sorting is not performed, variations in laminated film thickness distribution are suppressed. Since the laminated film thickness has a correlation with the obtained electric characteristic such as V th in the semiconductor device, the variations in characteristic can be suppressed by suppression of the variations in laminated film thickness distribution.
  • the single-wafer film forming apparatus and the batch film forming apparatus are combined in the present embodiment, a similar effect can be obtained even by combination of the single-wafer film forming apparatuses.
  • the processing sequence is sorted in place of the processed positions of wafers inside a lot.
  • the processing order in the latter step out of two steps is optimized so as to offset variations in machined amount as an amount machined by the two steps, whereby it is possible to suppress variations in characteristic which causes the variations in machined amount, and thus improve a manufacturing yield.
  • V th has been cited as the obtained characteristic of the semiconductor device and the value has been used which is obtained from the correlation with the film thickness measured by the film thickness measuring device in these embodiments
  • a value measured by a prober that measures an electric characteristic with respect to each chip inside the wafer may also be used.
  • another electric characteristic such as an on-current I on , a figuration characteristic such as a wiring width, a width of the gate electrode, a width of the gate side wall, or the like can also be employed.
  • a value obtained from the correlation with the film thickness as with V th or a value measured by the prober as a characteristic measuring device can be used.
  • a value measured by the prober as a characteristic measuring device can be used.
  • a value measured, for example, by a CD-SEM (Current Density Scanning Electron Microscope), a scatterometry or the like can be used. Any one or more of these characteristic measuring devices may be provided.
  • the embodiments can also be applicable to other processing steps such as a lithography step, an etching step and an ion implantation step.
  • machined amounts or the variations in characteristic in the two steps in the film formation step have been offset in these embodiments, for example, machined amounts or variations in characteristic in different steps, such as the film formation step and the lithography step, can also be offset so long as each of these steps has an effect on the same characteristic of the semiconductor device and is a step where variations occur in accordance with the processing order.
  • the number of steps may be two or larger, and machined amounts or variations in characteristic in three or four steps, such as a formation step for a gate side wall made up of three or more layers may be offset.
  • a single process such as film formation, etching and the like can be divided into two or more steps, and the wafers w can be sorted between those steps, to offset machined amounts or variations in characteristic in the single process.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Quality & Reliability (AREA)
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  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Chemical Vapour Deposition (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
US13/217,736 2010-08-27 2011-08-25 Manufacturing method and apparatus for semiconductor device Expired - Fee Related US8841205B2 (en)

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JP2010190948A JP5296025B2 (ja) 2010-08-27 2010-08-27 半導体装置の製造方法及び製造装置

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JP5853382B2 (ja) * 2011-03-11 2016-02-09 ソニー株式会社 半導体装置の製造方法、及び電子機器の製造方法
JP6144924B2 (ja) * 2012-03-21 2017-06-07 株式会社日立国際電気 基板処理装置、メンテナンス方法及びプログラム
US10901401B2 (en) 2016-01-15 2021-01-26 Mitsubishi Electric Corporation Plan generation apparatus, method and computer readable medium for multi-process production of intermediate product
JP7224254B2 (ja) * 2019-07-17 2023-02-17 東京エレクトロン株式会社 基板処理装置、情報処理装置、及び基板処理方法
WO2021024911A1 (ja) * 2019-08-02 2021-02-11 株式会社カネカ 太陽電池の製膜方法および太陽電池の製膜システム

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030164354A1 (en) * 1999-12-28 2003-09-04 Applied Materials, Inc. System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
US6946304B2 (en) 2001-08-31 2005-09-20 Kabushiki Kaisha Toshiba Apparatus for and method of manufacturing a semiconductor device, and cleaning method for use in the apparatus for manufacturing a semiconductor device
JP2005332894A (ja) 2004-05-18 2005-12-02 Sony Corp ウェーハプロセス装置及び半導体製造ライン
US20070202614A1 (en) * 2006-02-10 2007-08-30 Chiang Tony P Method and apparatus for combinatorially varying materials, unit process and process sequence
US20080006650A1 (en) * 2006-06-27 2008-01-10 Applied Materials, Inc. Method and apparatus for multi-chamber exhaust control
US20080077269A1 (en) 2006-09-22 2008-03-27 Lee Nam-Young Method and system for managing wafer processing
JP2009076863A (ja) 2007-08-27 2009-04-09 Renesas Technology Corp 半導体装置の製造方法
JP2010073921A (ja) 2008-09-19 2010-04-02 Seiko Epson Corp 加工装置、加工方法及び半導体装置の製造方法

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030164354A1 (en) * 1999-12-28 2003-09-04 Applied Materials, Inc. System level in-situ integrated dielectric etch process particularly useful for copper dual damascene
US6946304B2 (en) 2001-08-31 2005-09-20 Kabushiki Kaisha Toshiba Apparatus for and method of manufacturing a semiconductor device, and cleaning method for use in the apparatus for manufacturing a semiconductor device
US7195930B2 (en) 2001-08-31 2007-03-27 Kabushiki Kaisha Toshiba Cleaning method for use in an apparatus for manufacturing a semiconductor device
US20070137567A1 (en) 2001-08-31 2007-06-21 Kabushiki Kaisha Toshiba Apparatus for manufacturing a semiconductor device
JP2005332894A (ja) 2004-05-18 2005-12-02 Sony Corp ウェーハプロセス装置及び半導体製造ライン
US20070202614A1 (en) * 2006-02-10 2007-08-30 Chiang Tony P Method and apparatus for combinatorially varying materials, unit process and process sequence
US20080006650A1 (en) * 2006-06-27 2008-01-10 Applied Materials, Inc. Method and apparatus for multi-chamber exhaust control
US20080077269A1 (en) 2006-09-22 2008-03-27 Lee Nam-Young Method and system for managing wafer processing
JP2008077665A (ja) 2006-09-22 2008-04-03 Samsung Electronics Co Ltd 工程管理方法およびその方法を利用したシステム
US7801636B2 (en) 2006-09-22 2010-09-21 Samsung Electronics Co., Ltd. Method and system for managing wafer processing
JP2009076863A (ja) 2007-08-27 2009-04-09 Renesas Technology Corp 半導体装置の製造方法
JP2010073921A (ja) 2008-09-19 2010-04-02 Seiko Epson Corp 加工装置、加工方法及び半導体装置の製造方法

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Japanese Office Action for Japanese Application No. 2010-190948 mailed on Feb. 5, 2013.
Koukado Kenji, Sony Corp, Dec. 2, 2005, 1-12. *
Shishikura Isao, Seiko Epson Corp, Apr. 2, 2010, 1-31. *
Taiwanese Office Action issued on Feb. 20, 2014 in corresponding Taiwanese patent application No. 100129558, along with English translation.

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JP5296025B2 (ja) 2013-09-25
TWI472030B (zh) 2015-02-01

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