US8785942B2 - Nitride semiconductor substrate and method of manufacturing the same - Google Patents

Nitride semiconductor substrate and method of manufacturing the same Download PDF

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US8785942B2
US8785942B2 US13/352,987 US201213352987A US8785942B2 US 8785942 B2 US8785942 B2 US 8785942B2 US 201213352987 A US201213352987 A US 201213352987A US 8785942 B2 US8785942 B2 US 8785942B2
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nitride semiconductor
semiconductor substrate
buffer layer
substrate
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US20120211763A1 (en
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Akira Yoshida
Jun Komiyama
Yoshihisa Abe
Hiroshi Oishi
Kenichi Eriguchi
Shunichi Suzuki
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Coorstek Gk
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02458—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/0254—Nitrides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

  • the present invention relates to a nitride semiconductor substrate for a nitride semiconductor suitable as a high speed and high breakdown-voltage electron device.
  • Nitride semiconductors such as gallium nitride (GaN), aluminum nitride (AlN), etc., have outstanding properties, such as high electron mobility, high heat resistance, etc., and therefore can suitably be applied to a high electron mobility transistor (HEMT: High Electron Mobility Transistor), a heterojunction field effect transistor (HFET: Heterojunction Field Effect Transistor), for example.
  • HEMT High Electron Mobility Transistor
  • HFET Heterojunction Field Effect Transistor
  • Japanese Patent Application Publication No. 2001-196575 discloses a technology in which, in order to reduce a leak current component caused by conduction of the remaining carrier in a buffer layer of GaN and to raise a pinch off property of a transistor in a GaN field-effect transistor, an AlGaN layer is provided in the GaN buffer layer of a heterostructure in which the GaN buffer layer, a channel layer of GaN or a combination of InGaN and GaN, and an AlGaN layer are formed one by one on a sapphire substrate or a SiC substrate, and an AlN content in the AlGaN layer is smaller than an AM content in the AlGaN layer at the surface.
  • Japanese Patent Application Publication No. 2008-010803 discloses a nitride semiconductor field-effect transistor technology in which, an Al x Ga 1-x N layer, a GaN layer, and a Al y Ga 1-y N layer are stacked in this order in the +c direction of crystal orientation for the purpose of obtaining enhancement type operation capable of controlling the threshold voltage, and a gate portion has a channel of a double heterostructure, where depletion takes place when x ⁇ y.
  • Japanese Patent Application Publication No. 2010-123899 discloses a HEMT structure in which a first nitride semiconductor layer consisting of a first nitride semiconductor and a second nitride semiconductor layer which is formed on the first nitride semiconductor layer and consists of a second nitride semiconductor having a larger band gap than the first nitride semiconductor are provided, and the first nitride semiconductor layer has an area whose penetration dislocation density increases in the stacking direction.
  • JP-A No. 2001-196575 is effective in improvement in a pinch off property, but it is not necessarily sufficient in respect of improvement in the threshold voltage and current collapse.
  • JP-A No. 2008-010803 discloses that the technology can control the threshold voltage, it still does not sufficiently correspond to a need for obtaining a higher threshold voltage.
  • JP-A No. 2010-123899 can control the current collapse, but it is not sufficient in respect of the improvement in the threshold voltage.
  • the present invention arises in view of such technical problems and aims at providing a nitride semiconductor substrate which allows both a higher threshold voltage and current collapse improvement and is suitable for a normally-off type high breakdown voltage device, and a method of manufacturing the substrate.
  • the nitride semiconductor substrate in accordance with the present invention is a nitride semiconductor substrate having a substrate, a buffer layer formed on one principal plane of the above-mentioned substrate, an intermediate layer formed on the above-mentioned buffer layer, an electron transport layer formed on the above-mentioned intermediate layer, and an electron supply layer formed on the above-mentioned electron transport layer, wherein the above-mentioned intermediate layer has a thickness of 200 nm to 1500 nm and a carbon concentration of 5 ⁇ 10 16 atoms/cm 3 to 1 ⁇ 10 18 atoms/cm 3 and is of Al x Ga 1-x N (0.05 ⁇ x ⁇ 0.24), and the above-mentioned electron transport layer has a thickness of 5 nm to 200 nm and is of Al y Ga 1-y N (0 ⁇ y ⁇ 0.04).
  • Such a structure provides a nitride semiconductor substrate which allows both the higher threshold voltage and current collapse improvement and is suitable for a normally-off type high breakdown voltage device.
  • AlN spacer layers are respectively interposed between the above-mentioned intermediate layer and the above-mentioned electron transport layer and between the above-mentioned electron transport layer and the above-mentioned electron supply layer.
  • the above-mentioned buffer layer consists of an initial buffer layer and repeatedly deposited layers formed on the above-mentioned initial buffer layer
  • the above-mentioned initial buffer layer is such that an AlN layer and an Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer are stacked in this order
  • the above-mentioned repeatedly deposited layers are such that GaN layers and AlN layers are repeatedly stacked in this order a plurality of times
  • another GaN layer is further formed to have one set of composite layers, and a plurality of sets are stacked.
  • the preferred method of manufacturing the nitride semiconductor substrate in accordance with the present invention is a method of manufacturing a nitride semiconductor substrate using a vapor deposition process, wherein a temperature at the time of forming the above-mentioned intermediate layer on the above-mentioned buffer layer is 970° C. to 1250° C.
  • FIG. 1 is a schematic section of a nitride semiconductor substrate in accordance with a preferred embodiment of the present invention.
  • FIG. 2 is a schematic section of a nitride semiconductor substrate in accordance with another preferred embodiment of the present invention.
  • FIG. 3 is a schematic section of a nitride semiconductor substrate in accordance with another preferred embodiment of the present invention.
  • FIG. 4 is a table showing fabrication conditions and the evaluation results of Samples 1-32.
  • FIG. 5 is a table showing fabrication conditions and the evaluation results of Samples 1, 2 and 33-38.
  • the substrate 1 as a base substrate for forming the nitride semiconductor.
  • the materials there may be mentioned silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), and gallium nitride (GaN).
  • the substrate 1 is advantageous, since a Si single crystal substrate can be obtained easily.
  • a single crystal manufactured by the Czochralski process (CZ process) or a floating zone process (FZ process) or a substrate produced by various processes, such as a vapor deposition process, a lamination process, etc. may be applied.
  • CZ process Czochralski process
  • FZ process floating zone process
  • a substrate produced by various processes such as a vapor deposition process, a lamination process, etc.
  • it may be used after controlling suitably a thickness of the Si single crystal substrate, a surface state, concentration and distribution of dopants, such as oxygen, nitrogen, carbon, phosphorus, boron, etc., contained in the substrate, and various crystal defects.
  • the buffer layer 2 is formed on the one principal plane of the substrate 1 .
  • lattice constants and thermal expansion coefficients of Si and the nitride semiconductor are different, to thereby cause crystal defects, such as considerable curvature, a crack, a slip, etc. in the nitride semiconductor substrate 10 .
  • the buffer layer 2 is formed between the substrate 1 and the nitride semiconductor layer which form a device.
  • the optimal structure and material may suitably be chosen based on the use and required specification of the nitride semiconductor substrate 10 to be produced.
  • various types of nitride semiconductors may be used, for example.
  • a stack structure of the nitride semiconductor having at least one layer of nitride semiconductors containing Al may be used, since a high substrate property can be obtained readily.
  • FIG. 3 shows a schematic section of the nitride semiconductor substrate having a preferable embodiment of buffer layer.
  • the structure of the buffer layer 2 has an initial buffer layer 21 in which an AlN layer 211 and an Al z Ga 1-z N (0 ⁇ z ⁇ 1) layer 212 are stacked in this order, and repeatedly deposited layers 22 formed on the above-mentioned initial buffer layer 21 .
  • the above-mentioned repeatedly deposited layers 22 are such that the GaN layers 221 and the AlN layers 222 are repeatedly stacked in this order a plurality of times, another GaN layer 223 is further formed to have one set of composite layers 220 , and a plurality of sets are stacked.
  • the intermediate layer which serves to improve a property is formed on the buffer layer 2 , and the electron transport layer 4 is formed on this intermediate layer 3 . Furthermore, the electron supply layer 5 is formed thereon.
  • This structure is similar to substrate structures of a well-known HEMT etc. In this way, the nitride semiconductor substrate 10 in accordance with one embodiment of the present invention is formed.
  • the intermediate layer 3 has a thickness of 200 nm to 1500 nm and a carbon concentration of 5 ⁇ 10 16 atoms/cm 3 to 1 ⁇ 10 18 atoms/cm 3 , and is of Al x Ga 1-x N (0.05 ⁇ x ⁇ 0.24).
  • a method of raising a threshold voltage may be an increase in energy difference between a conduction band and the Fermi level in the intermediate layer 3 formed between the buffer layer 2 and the electron transport layer 4 .
  • it is necessary to reduce an electron density in the intermediate layer 3 .
  • a method of preventing generation of a defect in the intermediate layer 3 there may be mentioned.
  • Al x Ga 1-x N In the case where Al x Ga 1-x N is used for the intermediate layer 3 , a certain amount of film thickness is needed for realizing a normally-off state.
  • Al x Ga 1-x N itself is a material which tends to cause a defect when it is formed as a film by a vapor deposition process. For this reason, the electrons contained in the layer formed as a film increase and the Fermi level becomes high. Furthermore, as the film thickness is increased, an amount of electrons contained in the layer formed as a film increases in proportion to this thickness, so that improvement in the threshold voltage cannot be expected.
  • a thickness of the intermediate layer 3 is set to 200 nm to 1500 nm in the present invention. Preferably, it is from 800 nm to 1200 nm.
  • a film thickness of less than 200 nm is so insufficient as to provide an amount of electrons allowing the effect of the present invention, this is not preferred. On the other hand, if it exceeds 1500 nm, a breakdown voltage falls; this is not preferred, either.
  • a carbon concentration in the intermediate layer 3 is preferably from 5 ⁇ 10 16 atoms/cm 3 to 1 ⁇ 10 18 atoms/cm 3 . More preferably, it is from 1 ⁇ 10 17 atoms/cm 3 to 5 ⁇ 10 17 atoms/cm 3 .
  • the carbon concentrations are represented by averages measured in the thickness direction of the substrate by way of known concentration measuring methods, such as a spreading resistance (SR) measuring method and the secondary ion mass spectrometry (SIMS) method. Further, unless otherwise stated, it is represented by a value measured at one point in the center of the one principal plane of the substrate. However, it is possible to use values measured at multiple points in the one principal plane of the substrate if necessary.
  • concentration measuring methods such as a spreading resistance (SR) measuring method and the secondary ion mass spectrometry (SIMS) method.
  • Carbon included suitably in the intermediate layer 3 has the effects of preventing the rise of the Fermi level caused by a defect and of raising a conduction band of the electron transport layer 4 which is formed directly on the intermediate layer 3 .
  • a half-value width of an X-ray rocking curve of the intermediate layer 3 in accordance with the present invention is preferably 600 seconds or less at AlGaN (002) plane.
  • the half-value width of the X-ray rocking curve exceeds 600 seconds, there is concern that improvement in a threshold is inhibited since the crystallinity of the intermediate layer 3 is low.
  • x of Al x Ga 1-x N in the intermediate layer 3 is from 0.05 to 0.24. More preferably, it is from 0.15 to 0.23.
  • the intermediate layer 3 may be of not only a single layer having an Al x Ga 1-x N composition but also a multilayer structure consisting of a plurality of Al x Ga 1-x N layers where Al contents x are different. Furthermore, Al concentrations may be arranged to change (i.e. increase or decrease) uniformly in the thickness direction.
  • the electron transport layer 4 located directly on the intermediate layer 3 has a thickness of 5 nm to 200 nm and is of Al y Ga 1-y N (0 ⁇ y ⁇ 0.04).
  • a thickness of the electron transport layer 4 is from 5 nm to 200 nm. More preferably, it is from 10 nm to 150 nm.
  • a thickness of the electron transport layer 4 is less than 5 nm, it is so thin a film as to form a uniform film generally. Thus, there is concern that the property may be worsened because of uneven film thickness, this is not preferred. On the other hand, if the thickness exceeds 200 nm, the sufficient effect of raising the conduction band is not obtained, thus reducing the effect of improving the threshold voltage. This is not preferred, either.
  • the Al content of the electron transport layer 4 is of Al y Fa 1-y N
  • the carbon concentration of the electron transport layer 4 is not particularly limited, however, it is preferably from 5 ⁇ 10 16 atoms/cm 3 to 1 ⁇ 10 18 atoms/cm 3 . More preferably, it is from 1 ⁇ 10 17 atoms/cm 3 to 5 ⁇ 10 17 atoms/cm 3 .
  • the high carbon concentration prevents the rise of the Fermi level caused by a defect. As an example, it is effective in raising the conduction band of the GaN layer formed as the electron transport layer 4 .
  • a carbon concentration of less than 5 ⁇ 10 16 atoms/cm 3 does not allow the sufficient effects of preventing the rise of the Fermi level caused by a defect and of raising the conduction band of the GaN layer formed as the electron transport layer, this is not preferred.
  • a concentration of higher than 1 ⁇ 10 18 atoms/cm 3 there is concern that the high carbon concentration may worsen the collapse property. This is not preferred, either.
  • the electron supply layer 5 is formed on the electron transport layer 4 .
  • the electron supply layer 5 may be formed using a layer which has a normally-off type HEMT structure and is of various types of materials and compositions.
  • a nitride semiconductor is preferred.
  • AlGaN which has an arbitrary Al content may be applied.
  • the nitride semiconductor substrate 10 in accordance with one preferred embodiment of the present invention consists of the optimal combination of the film thickness and carbon concentration of the intermediate layer 3 and the film thickness and composition of the electron transport layer 4 which is in contact with the intermediate layer 3 , to thereby attain the high threshold voltage which is not conventional.
  • FIG. 2 shows a schematic section of the nitride semiconductor substrate in accordance with another preferred embodiment of the present invention.
  • AlN spacer layers 6 may further be interposed respectively between the intermediate layer 3 and the electron transport layer 4 and between the electron transport layer 4 and the electron supply layer 5 .
  • the AlN spacer layer 6 mainly provides the effect of increasing the shift of the threshold voltage.
  • the AlN spacer layers 6 exist to sandwich the electron transport layer 4 , thus exerting the effect of increasing the shift of the threshold voltage further.
  • a film thickness of the AlN spacer layer 6 is preferably from 0.2 nm to 2 nm.
  • a film thickness of less than 0.2 nm worsens film thickness controllability, and this is not preferred. If it exceeds 2 nm, there is concern that the electron mobility may be worsened. This is not preferred, either.
  • the AlN spacer layers 6 are respectively interposed between the intermediate layer 3 and the electron transport layer 4 and between the electron transport layer 4 and the electron supply layer 5 . This is because there is a possibility that only one of them may not provide the sufficient effect of increasing the shift of the threshold voltage.
  • a suitable method of manufacturing the nitride semiconductor substrate 10 in accordance with the present invention includes the steps of forming the buffer layer 2 on the one principal plane of the substrate 1 using a vapor deposition process, forming the intermediate layer 3 on the buffer layer 2 , forming the electron transport layer 4 on the intermediate layer 3 , and forming the electron supply layer 5 on the electron transport layer 4 , and a temperature at the time of forming the above-mentioned intermediate layer 3 is from 970° C. to 1250° C.
  • the buffer layer 2 , the intermediate layer 3 , the electron transport layer 4 , and the electron supply layer 5 are formed one by one by a vapor deposition process on the one principal plane, such as a Si substrate etc.
  • a metalorganic chemical vapor deposition (MOCVD) method is used preferably.
  • the intermediate layer 3 by optimizing its crystallinity and film thickness as well as the carbon concentration, it is possible to improve the threshold remarkably.
  • the precise control may be carried out with its film forming temperature, when a vapor deposition process is applied.
  • a source of carbon is included in the materials used for the MOCVD method, so that the carbon concentration can also be adjusted by controlling precisely the growth temperature, a material supply flow rate, growth time, etc., for the purpose of optimization.
  • a film forming temperature of the intermediate layer 3 is less than 970° C., necessary crystallinity cannot be obtained, this is not preferred. On the other hand, if it exceeds 1250° C., a uniform growth rate cannot be obtained and it degrades film thickness homogeneity or worsens Al concentration controllability, this is not preferred, either. Preferably, it is from 980° C. to 1030° C.
  • a growth temperature for each layer, except for the intermediate layer 3 is not necessarily limited but it may be suitably adjusted according to the required properties of the nitride semiconductor substrate.
  • the substrate 1 , the buffer layer 2 , the intermediate layer 3 , the electron transport layer 4 , and the electron supply layer 5 are essential components.
  • One or more layers suitably consisting of various types of nitride semiconductors may be added between the substrate 1 and the buffer layer 2 or onto the electron supply layer 5 as required or in order to add various types of properties.
  • the present invention can provide a nitride semiconductor substrate which allows both a higher threshold voltage and current collapse improvement and is suitable for a normally-off type high breakdown-voltage device, and a suitable method of manufacturing the substrate.
  • the nitride semiconductor substrate 10 in accordance with the present invention is advantageous in that the effect of improving the threshold voltage can be obtained by combining the structure having a smaller number of layers than before and the growth temperature control technique which allows simple and precise control.
  • a nitride semiconductor substrate 10 having a layer structure as shown in FIG. 1 was fabricated according to the following processes.
  • the substrate 1 made of a Si single crystal with a diameter of 3 inches, an n dopant type, a thickness of 625 ⁇ m, and a plane direction (100) was placed in an MOCVD apparatus.
  • materials for the nitride semiconductor trimethyl gallium (TMG), trimethyl aluminum (TMA), ammonia (NH 3 ), and methane (CH 4 ) were used. According to the layer to, be formed, these materials were used selectively and suitably, and a vapor deposition temperature was raised to 1000° C. to form each layer.
  • composition and adjustment of a thickness of each layer were achieved by selection of the materials and adjustment of a flow rate, pressure, and supply time.
  • An AlN single crystal layer was formed on the substrate 1 to have a carbon concentration of 5 ⁇ 10 19 atoms/cm 3 and a thickness of 20 nm. Subsequently, an Al 0.2 Ga 0.8 N single crystal layer was stacked to have a carbon concentration of 5 ⁇ 10 19 atoms/cm 3 and a thickness of 80 nm. These operations were repeated alternately by way of the similar process to form the buffer layers 2 in which a total of 20 layers including ten layers for each were stacked.
  • the electron transport layer 4 of a GaN single crystal layer was formed to have a thickness of 100 nm and a carbon concentration of 1 ⁇ 10 17 atoms/cm 3 .
  • the electron supply layer 5 of an Al 0.25 Ga 0.75 N single crystal was formed to have a thickness of 30 nm and a carbon concentration of 5 ⁇ 10 17 atoms/cm 3 .
  • the nitride semiconductor substrate 10 of Sample 1 was obtained.
  • Threshold voltages and current collapse of the nitride semiconductor substrates 10 in Samples 1 and 2 were each measured and evaluated for comparison. Fabrication conditions and evaluation results are shown in the following table 1.
  • Measurements of the threshold voltages were carried out such that Schottky electrodes (Ni/Au) of recess gates and ohmic electrodes (Ti/Al) as sources and drains were formed on the electron supply layers 5 of the respectively formed nitride semiconductor substrates 10 , element separation was carried out, and I-V measurement was performed by a curve tracer at room temperature after forming devices of electric field effect type transistors.
  • the collapse measurement by current measurement before and after applying stress voltage between electrodes was used. Further, by way the SIMS method, the carbon concentration was measured at one point in the center of the principal plane of the substrate.
  • the Al content, the film thickness, and the carbon concentration of the intermediate layer 3 and the film thickness and the carbon concentration of the electron transport layer 4 were changed. Except for these, the nitride semiconductor substrate 10 was fabricated similarly to Sample 1 and evaluated.
  • the breakdown voltages were evaluated using the curve tracer. One that was 150V per micrometer or more was judged to be “good” on the basis of the breakdown voltage value in Sample 1, and one that was less than it was judged to be “reduced”.
  • the current collapse compared with Sample 1, in the case where the current value after applying the stress voltage was equal to or greater than one half of the current value before applying it, the current collapse was judged to be “good”. In the case where it was less than one half, the current collapse was judged to be “reduced.
  • the buffer layer 2 was arranged to have a structure as set forth below. Except this, the nitride semiconductor substrate 10 was fabricated similarly to Sample 1 to obtain Sample 30.
  • the buffer layer 2 in Sample 30 was provided with an initial buffer layer and repeatedly deposited layers.
  • an AlN single crystal layer was stacked to have a thickness of 100 nm, and an Al 0.1 Ga 0.9 N single crystal layer was stacked to have a thickness of 200 nm.
  • a GaN single crystal layer was formed to have a thickness of 25 nm; subsequently an AlN single crystal layer was stacked to have a thickness of 5 nm.
  • another GaN layer was formed to have a thickness of 220 nm. Assuming these to be one set of composite layers, six sets were repeatedly stacked.
  • Sample 30 the plane direction (100) of the substrate 1 made of a Si single crystal was changed into (111). Except this, similarly to Sample 30, the nitride semiconductor substrate 10 was fabricated to obtain Sample 31.
  • the structure of the buffer layer 2 was arranged to be similar to that in Sample 30. Except this, similarly to Sample 2, the nitride semiconductor substrate 10 was fabricated to obtain Sample 32.
  • Sample 24 allowed each of the above-mentioned properties to be good, but resistance of the device increased.
  • the film forming temperature for the intermediate layer 3 was changed. Except this, similarly to Sample 1, the nitride semiconductor substrate 10 was fabricated and evaluated. Fabrication conditions and the evaluation results are shown in Table 2 ( FIG. 4 ).
  • the AlN spacer layer 6 with a thickness of 1 nm was interposed between the positions shown in FIG. 2 .
  • AlN was continuously deposited as a film in the manufacture process in Sample 1, and a growth temperature was set to 1000° C.
  • the nitride semiconductor substrate in accordance with the present invention is suitable as a nitride semiconductor substrate used for a nitride semiconductor suitable for an inverter for controlling large current, and a high speed and high breakdown-voltage electron device.

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JP2011-117552 2011-05-26
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JP6925117B2 (ja) 2016-11-18 2021-08-25 エア・ウォーター株式会社 化合物半導体基板の製造方法および化合物半導体基板
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