US8509003B2 - Read architecture for MRAM - Google Patents

Read architecture for MRAM Download PDF

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US8509003B2
US8509003B2 US13/237,282 US201113237282A US8509003B2 US 8509003 B2 US8509003 B2 US 8509003B2 US 201113237282 A US201113237282 A US 201113237282A US 8509003 B2 US8509003 B2 US 8509003B2
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sense
cell
read
resistance state
outputs
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US20130070519A1 (en
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Kai-Chun Lin
Hung-Chang Yu
Yue-Der Chih
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Priority to KR1020120022853A priority patent/KR101334424B1/ko
Priority to TW101117180A priority patent/TWI475560B/zh
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5607—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using magnetic storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0057—Read done in two steps, e.g. wherein the cell is read twice and one of the two read values serving as a reference value

Definitions

  • the present disclosure relates to read architectures for memory devices, and more specifically to reach architectures for magnetoresistive random access memory (MRAM).
  • MRAM magnetoresistive random access memory
  • Magnetoresistive random access memory is a non-volatile memory where data is stored in magnetic storage elements.
  • each cell has two ferromagnetic plates, each of which can hold a magnetic field, separated by a thin insulating layer.
  • One of the plates is a permanent magnet set to a selected polarity and the other plate's field can be changed to match that of an external field to store a bit.
  • the cell is either in the low (RL) resistive state, which may represent a logic “1”, or the high (RH) resistive state, which may represent a logic “0”.
  • FIG. 1 is a graph illustrating the distribution or count of high resistance (RH) and low resistance (RL) value across an array of MRAM cells.
  • RH high resistance
  • RL low resistance
  • Process variations can result in an overlap in the resistance values for the high (RH) and low (RL) states, which can lead to read errors. This overlap is defined between RHmin and RLmax.
  • Conventional sense amplifiers cannot account for these process variations.
  • FIG. 1 is a graph illustrating the high and low resistance distribution for MRAM cells in an array due to process variations.
  • FIG. 2 is another graph illustration resistance distribution for MRAM cells in an array.
  • FIG. 3 is a flow diagram illustrating on exemplary method of reading a MRAM cell.
  • FIG. 4 illustrates the method of FIG. 3 in connection with a resistance distribution graph.
  • FIG. 5 illustrates an embodiment of a read architecture for a MRAM cell.
  • FIG. 6 illustrates an embodiment of a multi-level sense amplifier for use in the read architecture of FIG. 5 .
  • FIG. 6A illustrate an alternative embodiment of the multi-level sense amplifier for use in the read architecture of FIG. 5 .
  • FIG. 7 illustrates an embodiment of the read architecture of FIG. 5 .
  • FIG. 8 illustrates an embodiment of a decision logic for use in the read architecture of FIG. 7 .
  • FIG. 9 is illustrates a MRAM cell in circuit illustration.
  • FIG. 10 is a so-called house curve illustrating MRAM magnetic tunneling junction (MTJ) resistance changes with changes in sensing current.
  • MTJ magnetic tunneling junction
  • FIG. 11 illustrates another house curve.
  • FIGS. 12-12D illustrate an embodiment of a non-destructive read architecture for reading a MRAM cell.
  • FIG. 13 illustrates an alternative embodiment of a non-destructive read methodology.
  • FIG. 14 is a flow diagram describing the alternative embodiment of a non-destructive read method of FIG. 13 .
  • Embodiments of a multi-level current sense amplifier are described herein for determining if a MRAM cell being read is programmed to a RH or RL value.
  • the MRAM cell is a Spin-Transfer-Torque (STT) MRAM.
  • STT MRAM uses spin-aligned or polarized electron flow to turn the free magnetic layer with respect to the pinned magnetic layer. When the polarizations of the layers are parallel, the result is the low (RL) resistive state, which may represent a logic “1”. When the polarizations of the layers are anti-parallel, the result is the high (RH) resistive state, which may represent a logic “0”.
  • the STT MRAM requires much less write current than conventional or toggle MRAM.
  • FIG. 2 is a graphical illustration showing some concepts underlying certain embodiments of a multi-level sense amplifier described herein.
  • FIG. 2 shows cell bit counts against resistance values.
  • RHmin which is the lowest expected value for RH for a MRAM cell in an array of cells
  • RLmax which is the highest expected value for RL for a MRAM cell in the array of cells.
  • the value delta ( ⁇ ) illustrated in the bottom half of FIG. 2 represents the difference between RH and RL for a given cell. It turns out that this value is consistent across different cells (as illustrated in FIG.
  • the multi-level sense amplifier uses sense amplifiers having different sense ratios (i.e., reference points) (illustrated as ratios A through E in FIG. 2 ) defining different resistance decision points (or thresholds) where the ratios are spaced in increments of less than ⁇ /2.
  • the outputs of the group of sense amplifiers can be analyzed to determine whether an individual cell is programmed with a resistance of RH or RL (i.e., programmed with a logic low (0) or logic high (1), respectively).
  • the multi-level sense amplifier should utilize at least four ratios, including two ratios at points higher than the value of RLmax and two ratios lower than the value of RHmin.
  • FIG. 3 is a flow diagram illustrating a method of reading a cell using a multi-level sense amplifier. This method involves a destructive read of the cell, and therefore, in certain situations, data must be rewritten into the cell.
  • the multi-level sense amplifier has “n” number of sense amplifiers.
  • the cell is read with each sense amplifier from the multi-level sense amplifier and the sense output results A[n:0], where n is greater than 3, is saved.
  • the low resistance (RL) state is written into the MRAM cell.
  • step 14 the cell is read again and the sensing output result B[n:0] is saved.
  • the saved outputs A and B are compared to determine if the cell was originally programmed at RH or RL. If there are two or more changes between the saved outputs A[n:0] and B[n:0], then it is determined that the resistance of the read cell was RH (step 20 ). Otherwise, it is determined that the resistance of the read cell was RL (step 18 ).
  • step 22 if it was determined at step 20 that the read value was RH, then RH is rewritten into the cell because the cell written low at step 12 . There is no need to rewrite data to the cell if the determination at step 18 was that the cell was programmed at RL.
  • FIG. 4 shows four possible data scenarios 30 to 60 to further illustrate the reading method described above.
  • a first scenario 30 that the coil is programmed at a resistance value of H 1 that is greater than the threshold set by all of the sense ratios A to E.
  • the output of each sense amplifier is going to indicate a high value, since H 1 is greater than the sense point of each sense amplifier.
  • a low value is written to the cell. This value is offset from the value H 1 by ⁇ . Assume this value is L 1 and falls somewhere between the threshold of ratio C and D.
  • step 14 the cell is read again, which results in three high outputs (from the sense amplifiers at ratios A, B and C) and two low outputs (from the sense amplifiers at ratios D and E). Because there are at least two changes in the read data (i.e., from the outputs of the sense amplifiers corresponding to ratios D and E), the decision is made at step 16 that the cell was programmed at RH. Note that the cell will need to be reprogrammed due to the low write of step 12 .
  • the approach guarantees that even if the cell is programmed at RHmax then the reprogramming, of that cell to its corresponding RL value crosses at least those two ratios that falls exclusively within the RH distribution. It should be noted also that the spacing of the ratios is less than ⁇ /2, meaning the move from RH to RL, which is a move of ⁇ , crosses at least two sense ratios.
  • the cell is programmed at a resistance value of H 2 that falls somewhere between ratios D and E.
  • the outputs of the first four sense amplifiers are going to indicate a high value, since H 2 is greater than the sense point of each of those sense amplifiers, but the output of the last sense amplifier is going to indicate a low value, since H 2 is less than the sense point of the last sense amplifier.
  • a low value is written to the cell. This value is offset from the value H 2 by ⁇ , so the resistance value moves across at least two sense ratio points (i.e., because the spacing must be less than ⁇ /2). Assume this value is L 2 and falls below the threshold of ratio A.
  • step 14 the cell is read again, which results in five low outputs. Because there are at least two changes in the read data, the decision is made at step 16 that the cell was programmed at RH. Note that the cell will need to be reprogrammed due to the low write of step 12 .
  • the cell is programmed at a resistance value of L 3 that falls right along ratio C.
  • Conventional sense amplifiers would not provide a definitive data output in this situation because it falls in the RH/RL overlap region and because it falls along a sense ratio.
  • the outputs of the first two sense amplifiers are going to indicate a high value, since L 3 is greater than the sense point of each of those sense amplifiers.
  • the third sense amplifier may read a value of H since the output is indeterminable, having fallen too close to the actual ratio.
  • the fourth and fifth sense amplifiers will read low values, since L 3 is less than the sense point of the last two sense amplifiers. At step 12 a low value is written to the cell.
  • step 14 the cell is read again, which results in only one data change corresponding to the output of the third sense amplifier. That it, this time the sense amplifier read the output as low. Because there is only one change in the read data, the decision is made at step 16 that the cell was programmed at RL. Note that the cell will not need to be reprogrammed since its data state was not changed by the low write of step 12 . Also note that it does not matter what value is read by the third sense amplifier in the first and second read operations. At most, there can be only one change in data and sometimes when the resistance values falls on top of the sense point there may be no change of data.
  • the cell is programmed at a resistance value of H 4 falling at or near the RHmin value and somewhere between ratios B and C.
  • Conventional sense amplifiers would not provide a definitive data output in this situation because it falls in the RH/RL overlap region.
  • the outputs of the first two sense amplifiers are going to indicate a high value, since H 4 is greater than the sense point of each of those sense amplifiers, but the outputs of the last three sense amplifiers are going to indicate a low value, since H 4 is less than their respective sense thresholds.
  • a low value is written to the cell.
  • This value is offset from the value H 4 by ⁇ , so the resistance value moves across at least two sense ratio points (i.e., because the spacing must be less than ⁇ /2). Assume this value is L 4 and falls below the threshold of ratio A.
  • the cell is read again, which results in five low outputs. Because there are at least two changes in the read data, the decision is made at step 16 that the cell was programmed at RH. Note that the cell will need to be reprogrammed due to the low write of step 12 .
  • the multi-level sense amplifier is configured to reflect at least two data changes when a cell programmed at RH is read, programmed at a level RL and then reread. At least two data changes occur because the increments between the sense thresholds is set to be less than ⁇ /2 and it is known that reprogramming the cell from RH to RL will change the resistance of the cell by the value of ⁇ . As such, the reprogramming operation is guaranteed to move the resistance value lower across at least two threshold points if the original programming is RH. Therefore, the multi-level sense amplifier is capable of reading even cells that fall within the grey overlap region between RHmin and RLmax.
  • the multi-level sense amplifier regarding at least two ratios higher than RLmax and at least two ratios lower than RHmin.
  • This approach accounts for the two worst case scenarios.
  • a cell is programmed at RH and when it is reprogrammed to the low value RL this value RL falls at RLmax. Setting at least two ratios higher than RLmax guarantees that at least the outputs of those two amplifiers will change.
  • the cell is programmed at RHmin. Having at least two ratios lower than RHmin ensures that if the cell is programmed at RH, then there will be at least two data state changes after programming that cell to RL because the spacing between ratios is set at less than ⁇ /2.
  • FIG. 5 illustrates an embodiment of a read architecture 100 utilizing a multi-level sense amplifier for implementing the read technique described above.
  • the architecture includes MRAM cell 104 programmed either to Rh or RH.
  • a reference current source 106 is provided, which could be a MRAM cell or a current source.
  • the cell 104 and reference 106 are coupled to a bank 102 of sense amplifiers each configured at a different ratio.
  • sense amplifier 102 A is configured at ratio A
  • sense amplifier 102 B is configured at ratio B
  • sense amplifier 102 C is configured at ratio C
  • sense amplifier 102 D is configured at ratio D
  • sense amplifier 102 E is configured at ratio E.
  • Each sense amplifier 102 has a respective output coupled to a circuit module 108 for storing the sense output of each amplifier.
  • the architecture also includes a decision module 110 for checking the sense amplifier outputs and determining if an RH or RL condition has been read from the cell based on the changes (if any) in the sense amplifier outputs from the first read to the second read. For example, if the module 110 determines that a high resistance has been read, then the sense output SO is set to logical 0, and if the module 110 determines that a low resistance has been read, then the sense output SO is set to logical 1. It should be understood that while the architecture 100 illustrated in FIG. 5 shows only one cell being read, the basic architecture would be adapted for reading multiple cells in an array of cells using conventional selection and multiplexing techniques used in the memory art.
  • control logic for implementing the reading technique providing any necessary control signals to the modules, as well as read and write control signals can be implemented in the memory controller of the MRAM array.
  • an additional integrated circuit controller for controlling the array may also be used.
  • Tunneling Magneto Resistance (TMR) ratio is one of the major performance criteria of STT-MRAM cells.
  • there is a delta current of 41.6 ⁇ mA ⁇ 25 ⁇ mA 16.6 ⁇ A.
  • Half of this delta current is 8.3 ⁇ A.
  • RHmin is 3800 ohms.
  • a cell at this RHmin will have an RL value that is 3800/1.66, i.e., 2289 ohms.
  • the current of the cell when at RHmin is 0.2V/3800 ohms, i.e., 52.6 ⁇ A
  • a reference resistance between RLmax (4800 ohms) and RHmin (3800 ohms) is selected.
  • a reference resistance of 4188 ohms is selected.
  • ratios are selected that keeps the increments between adjacent sense points at less than half delta (i.e., less than 17.4 ⁇ A).
  • the following ratios can be selected: X1.3, X1.2, X1, X0.8 and X0.7.
  • a simple calculation can confirm that these ratios meet the half delta requirement.
  • the reference (X1) was set at 4188 ohms.
  • Each ratio is spaced from an adjacent ratio by less than half delta (i.e., less than 17.4 ⁇ A): 62.1 ⁇ A; 57 ⁇ A; 47.775 ⁇ A; 38.4285 ⁇ A; and 33.4285 ⁇ A.
  • FIG. 6 illustrates a circuit diagram of a first embodiment of a multi-level sense amplifier 200 that may be used in the architecture of FIG. 5 .
  • the multi-level sense amplifier 200 includes a reference section 202 including a reference cell 206 programmed at a RL value and a reference cell 208 programmed at a RH value.
  • the reference section 202 includes NMOSs N 2 and N 4 tied to clamping voltage Vclamp and selection transistors N 1 and N 3 tied to control signal Ref mux.
  • the clamping voltage Vclamp is used to clamp the bitline voltage. For example, Vclamp may be set to 0.7V. If the threshold voltage is 0.5V, then the bit line voltage is 0.2V.
  • the reference section 202 generates reference current Iref equal to IrefH+IrefL.
  • the multi-level sense amplifier also includes five sense amplifiers for providing five sense outputs SOA, SOB, SOC, SOD, and SOE.
  • Transistor pairs P 1 /P 4 , P 1 /P 5 , P 1 /P 6 , P 1 /P 7 and P 1 /P 8 provide current mirrors for mirroring the reference current Iref to the five sense amplifiers.
  • Transistors P 4 , P 5 , P 6 , P 7 and P 8 are sized to provide the sensing ratios discussed above.
  • the PMOS are sized as follows: PMOS P 4 is sized to provide a current Iref A equal to the average or midpoint between IrefH and IrefL (i.e., Iref/2) times 1.3; PMOS P 5 is sized to provide a current IrefB equal to 1.2 ⁇ (Iref/2); PMOS P 6 is sized to provide a current IrefC equal to Iref/2; PMOS P 7 is sized to provide a current IrefD equal to 0.8 ⁇ (Iref/2); and PMOS P 8 is sized to provide a current IrefE equal to 0.7 ⁇ (Iref/2).
  • the cell current Icell is generated from the cell 204 in response to the bit line clamping voltage and at a level dependent on whether the cell is programmed to RH or RL.
  • the cell current Icell is mirrored via current mirror pair PMOS P 2 /P 3 and through NMOS mirror pairs N 7 /N 8 , N 7 /N 9 , N 7 /N 10 and N 7 /N 11 .
  • PMOS P 4 and NMOS N 8 are coupled together to inverter INV 1 , which provides output SOA.
  • PMOS P 6 and NMOS N 9 are coupled together to inverter INV 2 , which provides output SOB.
  • PMOS P 6 and NMOS N 10 are coupled together to inverter INV 3 , which provides output SOC.
  • PMOS P 7 and NMOS N 11 are coupled together to inverter INV 4 , which provides output SOD.
  • PMOS P 8 and NMOS N 12 are coupled together to inverter INV 5 , which provides output SOE.
  • This structure mirrors the reference current and the cell current to each branch of the multi-level sense amplifier.
  • the reference current is greater than the cell current, then the voltage between PMOS and NMOS transistors of the branch will be higher. If reference current is less than the cell current, then voltage between the PMOS and NMOS transistors of that branch will be lower.
  • An inverter such as is shown in FIG. 5 , or other structure (e.g., a simple voltage amplifier) can be used to map the higher voltage to a logic value of “1” and the lower voltage to a logic value of “0”.
  • FIG. 6A illustrates an alternative embodiment of a multi-level sense amplifier 200 A.
  • the sense amplifier 200 A of FIG. 6 is identical to that of the sense amplifier 200 of FIG. 6 only it uses a modified reference section 202 A.
  • the reference section 202 A generates a reference current Iref from a constant resistance 207 (e.g., polysilicon resistors, MOSFET biased in triode region, etc.).
  • a constant resistance 207 e.g., polysilicon resistors, MOSFET biased in triode region, etc.
  • FIG. 7 illustrates an embodiment of the storage and decisional logic 210 coupled to the sense outputs SOA to SOE of the multi-level sense amplifier 200 A of FIG. 6A .
  • the outputs SOA to SOE are coupled to a multiplexer bank 212 that includes multiplexers 212 A, 212 B, 212 C, 212 D and 212 D coupled to the sense outputs SOA to SOE, respectively.
  • the multiplexer includes two outputs coupled to a pair of data storage nodes of data storage module 214 .
  • each data storage module is formed from a pair of data latches L for holding data outputted from its corresponding connected multiplexer.
  • Latch pair 214 A is coupled to the output of multiplexer 212 A; latch pair 214 B is coupled to the output of multiplexer 212 B; latch pair 214 C is coupled to the output of multiplexer 212 C; latch pair 214 D is coupled to the output of multiplexer 212 D; and latch pair 214 E is coupled to the output of multiplexer 212 E.
  • a control signal is provided from the memory controller to the multiplexers to control whether the individual multiplexers pass the sensed output to either the first or second latch of the respective latch pair. That is, one of the latches of the latch pair receives the result of the first read operation (step 10 of FIG. 3 ) and the other latch receives the result of the second read operation (step 14 of FIG. 3 ).
  • a bank 216 of exclusive OR (XOR) gates is coupled to the data storage module 214 .
  • latch pair 214 A is coupled to the inputs of the XOR gate 216 A;
  • latch pair 214 B is coupled to the inputs of the XOR gate 216 B;
  • latch pair 214 C is coupled to the inputs of the XOR gate 216 C;
  • latch pair 214 D is coupled to the inputs of the XOR gate 216 D;
  • latch pair 214 E is coupled to the inputs of the XOR gate 216 E.
  • the XOR gate's logic function can be summarized as one or the other, but not both. So, if there is any difference between the data stored in the latches of a latch pair, the XOR gate will output a logic high (1).
  • the outputs of the XOR gates 216 A to 216 E are coupled to decision logic module 220 , which determines the number of read output changes (e.g., do the number of changes meet the minimum number of changes (i.e., 2) to determine the cell is programmed at RH) and outputs a sense output SO in accordance therewith.
  • decision logic module 220 determines the number of read output changes (e.g., do the number of changes meet the minimum number of changes (i.e., 2) to determine the cell is programmed at RH) and outputs a sense output SO in accordance therewith.
  • FIG. 8 illustrates an embodiment of the logic module 220 illustrated in FIG. 7 . It should be understood that there are numerous logic combinations that can be used to determine the number of read output changes and outputs sense output SO in accordance therewith and that FIG. 8 illustrates only one such embodiment. Also, analog approaches and combinations of analog and digital can also be utilized, e.g., a storage capacitor where the voltage level represents the number of data changes and an output inverter, etc.
  • a bank of inverters is used to invert outputs SOA′ to SOE′ from the XOR gates 216 to provided inverted outputs SOA′_B to SOA′_E, respectively.
  • a series of gates is also provided to implement the following logic: if none, or only one, of SOA′ to SOE′ are logical 1 (meaning there was one or less data changes between the first and second reads of the MRAM cell), then the output SO is logical “1” (i.e., the MRAM cell was programmed at a low resistance value); else, output logical “0” (i.e., MRAM cell was programmed at a high resistance value).
  • This logic is implemented in the illustrated embodiment via a first bank of NOR gates 222 , a first bank of NAND gates 224 coupled to the outputs of the NOR gates, a second bank of NAND gates 226 coupled to the output of the first bank of NAND gates 224 , a NOR gate 228 coupled to the outputs of the NAND gates 226 and an inverter coupled to the output of the NOR gate 228 .
  • FIGS. 9-12D described below illustrate an alternative embodiment of a MRAM cell read architecture and methods and the underlying concepts thereof.
  • This alternative embodiment is non-destructive in nature, meaning data does not have to be rewritten to the read cell after the read. This approach has advantages in read latency and power consumption.
  • FIG. 9 shows a one-transistor MTJ STT-MRAM cell structure.
  • One MTJ is connected to one NMOS transistors in series between the bit line (BL) and source line (SL).
  • the word line (WL) is connected to the gate of the NMOS selection transistor.
  • the MTJ can be modeled as a variable resistor.
  • the MTJ includes two ferromagnetic layers and one oxide barrier layer, e.g., MgO. If the magnetization directions of the two ferromagnetic layers are parallel, the MTJ is in the low resistance state (RL), and if the magnetization directions are anti-parallel, the MTJ is in the high-resistance state (RH).
  • MgO oxide barrier layer
  • FIG. 10 illustrates a R-I sweep curve of an magnetic tunneling junction (MTJ) of a MRAM cell.
  • MTJ magnetic tunneling junction
  • V REF reference voltage
  • VREF When the VREF is used across multiple STT-MRAM cells, VREF must be set between the maximum expected V BL,L and the minimum expected V BL,H , which is not always possible as discussed above because there can be overlap in the resistance values between RH and RL across the array due to large bit-to-bit variations in MTJ resistance (See FIG. 1 ).
  • a read architecture uses a multi-level sense amplifier (e.g., one using multiple read currents I RA to I RD ) to make a decision on whether the MRAM cell was programmed at RH (large slope) or RL (smaller slope).
  • the read approach involves taking an initial read of the cell and establishing a sense reference for use in further reads based on this initial read. The reference is offset from the initial read.
  • the offset is designed—recognizing the sharp difference in slopes between RH and RL illustrated in the house curves of FIGS. 10 and 11 —such that the outputs of the additional reads will show whether the MRAM cell was programmed at RH or RL. That is, if the resistance value of the cell falls sharply, it is determined that the MRAM cell was programmed at RH. If the resistance value falls less sharply than would be expected for a cell programmed at RH, then it is determined that the MRAM cell was programmed at RL.
  • This architecture and method of reading is illustrated in more detail in connection with FIGS. 12 to 12D and described below.
  • FIG. 12 illustrates an embodiment of a non-destructive read architecture 300 . Illustrated to the left of the architecture are MTJ RH and RL curves across a range of sensing currents. Specifically, two points are illustrated denoting the RH and RL resistance values at a first sense current IBLA.
  • the read architecture includes a MRAM cell 302 , illustrated as the combination of a selection transistor and a MTJ.
  • the MRAM cell 302 may be, for example, STT-MRAM cell or toggle mode MRAM, cell, both of which exhibit the resistance slope characteristics illustrated in FIGS. 9 , 11 and 12 .
  • the read architecture includes, by way of example only, four current sources 304 A, 304 B, 304 C and 304 D for providing current IBLA, IBLB, IBLC and IBLD, where IBLA ⁇ IBLB ⁇ IBLC ⁇ IBLD.
  • the source blocks 304 can be provided as a series of current mirrors.
  • the architecture also includes switches A, A 1 , B, C and D.
  • Storage Element & Reference Generator 306 (hereinafter, reference generator 306 ) is connected to a voltage offset source 308 .
  • Sense amplifier 310 which in the illustrated embodiment is a voltage senses amplifier, has a first input coupled to an out of the reference generator 306 .
  • the reference generator 306 provides a voltage reference (described below as VBLA-offset) to the first input of the sense amplifier 310 .
  • the second input of the sense amplifier 310 is selectively coupled to the cell 302 via switches B, C and D.
  • the output of the sense amplifier 310 provides outputs SAOB, SAOC, and SAOD through switches B, C and D, respectively, to a decision circuit 312 , which is also described in more detail below.
  • the sense amplifiers 310 could be a current sense amplifier. Modifications to the architecture would include, for example, providing sources 304 as current sources and providing the reference from reference generator 306 as a reference current.
  • the first operation performed by the read architecture is to generate the reference voltage.
  • switch A is on (closed) while the other switches in architecture 300 are off (open).
  • Current source 304 A provides sensing current IBLA through switch A to the MRAM cell 302 , which produces a bit line voltage VBLA.
  • the bit line voltage VBLA is either equal to IBLA ⁇ RH (IBLA) or to IBLA ⁇ RL (IBLA) depending upon whether the MRAM cell is programmed at RH or RL, where RH (IBLA) is the resistance value of the particular cell being read when programmed at RH and provided a sensing current IBLA and RL (IBLA) is the resistance value of that cell when programmed at RL and provided a sensing current IBLA.
  • Reference generator 306 stores a voltage value equal to VBLA minus some offset voltage as determined by the voltage offset element 308 . This value is referred to herein as VBLA-offset. Reference generator 306 outputs this voltage to sense amplifier 312 for use as a sensing threshold.
  • the VBLA-offset voltage can be thought of as setting a reference resistance Rref (labeled in FIG. 12A ) that is offset from the initial resistance value of the MRAM cell under low sense current IBLA. That is, depending on whether the MRAM cell is programmed at RH or RL, the value of Rref is either RH (IBLA) ⁇ , or RL (IBLA) ⁇ .
  • the value of delta ( ⁇ ) is selected so that RH (IBLA) >Rref>RH (IBLD) .
  • the value of delta ( ⁇ ) is also selected so that RL (IBLA) >RL (IBLD) >Rref.
  • delta must be selected so that when all of the sense outputs are considered, there is a clear distinction between the outputs to be expected from a MRAM cell programmed at RH and one programmed at RL. Silicon test data can be used to select or fine tune the delta value.
  • switches A and A 1 are off, switches B are now on, and switches C and D remain off.
  • This configuration connects current source 304 B to the memory cell 302 to provide sensing current IBLB.
  • This generates voltage VVLB, which is equal to either IBLB ⁇ RH (IBLB) or IBLB ⁇ RL (IBLB) .
  • IBLB is larger than IBLA and that the resistance of the MRAM cell goes down as the sensing current increases.
  • the memory cell is programmed at RH, the amount of drop off from RH (IBLA) to RH (IBLB) will be steeper than the amount of drop off from RL (IBLA) to RL (IBLB) .
  • sense amplifier 310 outputs a logical “1” for SAOB, which is stored by decision circuit 312 for later analysis.
  • FIG. 12C in a next operation switches A, A 1 and B are off, switches C are now on, and switches D remain off.
  • This configuration connects current source 304 C to the memory cell 302 to provide sensing current IBLC.
  • This generates voltage VBLC, which is equal to either IBLC ⁇ RH (IBLC) or IBLC ⁇ RL (IBLC) .
  • IBLC is larger than IBLB and that the resistance of the MRAM cell goes down as the sensing current increases.
  • the drop off from RH (IBLB) to RH (IBLC) will be steeper than the drop off from RL (IBLB) to RH (IBLC) .
  • the resistance value of the cell is actually lower than Rref at this point if the cell is programmed at RH but still above Rref if programmed at RL.
  • VBLC is lower than VBLA-offset if the MRAM cell is programmed at RH, and VBLC is higher than VBLA-offset if the MRAM cell is programmed at RL. Therefore, sense amplifier 310 outputs a logical “0” for SAOB if the cell is at RH and a logical “1” if the cell is at RL.
  • FIG. 12D in a next operation switches A, A 1 , B and C are off and switches D are now on.
  • This configuration connects current source 304 D to the memory cell 302 to provide sensing current IBLD.
  • This generates voltage VBLD, which is equal to either IBLD ⁇ RH (IBLD) or IBLD ⁇ RL (IBLD) .
  • IBLD is larger than IBLC and that the resistance of the MRAM cell goes down as the sensing current increases.
  • the drop off from RH (IBLC) to RH (IBLD) will be larger than the drop off from RL (IBLC) to RL (IBLD) .
  • the resistance value of the cell is again lower than Rref at this point if the cell is programmed at RH and notably still above Rref if programmed at RL.
  • VBLD is lower than VBLA-offset if the MRAM cell is programmed at RH, and VBLD is higher than VBLA-offset if the MRAM cell is programmed at RL. Therefore, sense amplifier 310 outputs a logical “0” for SAOB if the cell is at RH and a logical “1” if the cell is at RL.
  • the value of the offset ⁇ and the number of sensing currents (and thus the number of data points) and their spacing can be selected to provide data from which the programmed state of the memory cell can be definitively determined.
  • at least four sensing currents are used, which is sufficient for generating the reference voltage and three data points SAOB, SAOC and SAOD, and the values are selected such that there will be at least two data points that would differ between a cell programmed at RH and one programmed at RL. At least two differences are deemed preferable to avoid instances when the RH value may fall at or near Rref.
  • RH may be represented by outputs [1 0 0] and RL by outputs [1 1 1].
  • the decision circuit 312 is configured to analyze the outputs SAOB, SAOC, SAOD, etc. and output a sense output SO that is either logical high (“1”) or logical low (“0”) dependent on the data.
  • the circuit can be configured in any number of ways to make this determination. For example, the circuit can be configured to check to see if there are enough SAO outputs that are low to make a determination that the cell is programmed at RH and output a logical “0” in such case (assuming of course that the convention is that RH corresponds to logical “0”). One may not expect the same output data pattern for each cell examined since process variations may affect the slope of RH an RL slightly.
  • the read architecture has been described above in connection with setting of a sense threshold voltage based on subtracting an offset voltage from VBLA, which is generated using low reference current IBLA, the system may in essence be flipped, meaning the sense threshold voltage is based on adding an offset voltage from VBLD, which is generated using higher reference current IBLD. Voltages VBLA, VBLB and VBLC would then be compared to this VBLD-offset voltage threshold instead of VBLA-offset.
  • the current sources 304 can be replaced with voltage sources.
  • the read architecture fundamentally operates in the same way but uses current sense amplifier (rather than a voltage sense amplifier) and current reference (rather than voltage reference VBLA-offset).
  • the reference generator described above can be configured as a simple capacitor for storing a voltage value VBLA-offset, which is generated by connecting the voltage VBLA to the offset 308 .
  • conventional charge sharing techniques using switching capacitors may be employed.
  • the VBLA voltage is stored at a first capacitor and then the first capacitor is connected to a second, smaller capacitor for charge sharing with the second capacitor. A smaller voltage is therefore generated by the smaller charge in the second capacitor.
  • the value of delta can be easily controlled through the sizing of the capacitors.
  • FIGS. 13 and 14 illustrate an alternative embodiment of the read architecture and method described above in connection with FIGS. 12-12D .
  • the offset ( ⁇ ) is moved up and down for the sequential read.
  • FIG. 13 shows four cycles using reference currents IBLA, IBLB, IBLC and IBLD. These four cycles are described above in connection with FIGS. 12-12D .
  • the value of reference Rref threshold is lowered to RrefB.
  • the value of the reference Rref threshold is raised above the original Rref value to Rref C.
  • the value of the Rref threshold is lowered to Rref D, which is below the original Rref value.
  • the difference reference values can be generated in any number of ways. For example, a voltage divider or current mirror may be used to provide different delta values for use in providing the different reference thresholds.
  • Cycle B moving the offset as described above enlarges the difference between RH/RL and Rref, increasing the read margin for both read RH and read RL.
  • Cycle C reducing the offset to raise the threshold point enlarges the sense amplifier margin for a read RH but reduces the margin for a read RL.
  • the change in the delta value can depend on the feature of the sense amplifier. For example, it may be easier for some sense amplifiers to read RL or RH, so the offset can be tuned for different purposes. For example, some sense amplifiers (or sensing architectures) might prefer to read RL but not to read RH, in which case more margin should be preserved for RH.
  • the offset voltage (or current as the case may be) is generated.
  • the first sense current I_blA (or voltage) is forced on the MRAM cell.
  • the resultant bit line voltage (or current) plus the generated offset are stored as the reference threshold.
  • the next sense current (or voltage) is forced on the cell and the sense results are stored.
  • the sense ratio of the sense amplifier is changed, such as by changing the offset voltage (or current). Step 406 is then repeated with the next sense current. Steps 406 and 408 can be repeated until all sense currents are used.
  • step 410 the stored sense outputs are examined to see how many outputs are low (or high depending on the selected approach). If the result of step 410 is negative, then at step 412 is determined that the cell was programmed at RL. Otherwise, at step 414 it is determined that the cell was programmed at RH.
  • the architecture includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier.
  • the storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell.
  • the architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison.
  • a method of reading a magnetoresistive random access memory (RAM) cell includes the steps of: performing a first read of the RAM cell at each of a plurality of different sense thresholds to provide a first set of sense outputs; writing the RAM cell to the low resistance state; performing a second read of the RAM cell at each of the plurality of different sense thresholds to provide a second set of sense outputs; comparing the first set of sense outputs and second set of sense outputs; and providing a data output for the RAM cell based on the comparing step.
  • a non-destructive method of reading a magnetoresistive random access memory (MRAM) cell includes the steps of: providing a first stimulus to the MRAM cell to produce a first bit line electric quantity; deriving a reference quantity from the first bit line electric quantity; providing a plurality of additional stimuli to the MRAM cell in sequence to produce a corresponding plurality of bit line electric quantities; comparing the reference quantity with the plurality of bit line electric quantities in sequence to produce a corresponding plurality of output values representing a result of the comparison; and examining the plurality of output values and outputting a sense output representing a determination of a programmed state of the MRAM cell.

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