US8483630B2 - Method and system for generating a pulse signal of the ultra wide band type - Google Patents

Method and system for generating a pulse signal of the ultra wide band type Download PDF

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US8483630B2
US8483630B2 US13/122,889 US200913122889A US8483630B2 US 8483630 B2 US8483630 B2 US 8483630B2 US 200913122889 A US200913122889 A US 200913122889A US 8483630 B2 US8483630 B2 US 8483630B2
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amplitude
phase
frequency
phases
signal
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US20110260757A1 (en
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Andrea Cathelin
Stéphane Thuries
Sylvain Godet
Eric Tournier
Jacques Graffeuil
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Centre National de la Recherche Scientifique CNRS
STMicroelectronics SA
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STMicroelectronics SA
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/69—Spread spectrum techniques
    • H04B1/7163—Spread spectrum techniques using impulse radio
    • H04B1/717—Pulse-related aspects
    • H04B1/7174—Pulse generation

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  • the invention relates to signals of the Ultra Wide Band type, or UWB signals, and, more particularly, to pulse signals of the ultra wide band type.
  • a conventional scheme for generating UWB pulses uses direct generation on the basis of fast phenomena such as for example the crossover from a forward bias to a reverse bias of an SRD diode (“Step Recovery Diode”), according to an acronym well known to the person skilled in the art.
  • Step Recovery Diode an SRD diode
  • Another conventional solution uses the indirect generation of pulses using, for example, modulation of a carrier by a Gaussian function in a mixing stage.
  • a method and a system for generating UWB pulses are proposed which allows a controlled adjustment of the bandwidth and/or of the central frequency of the UWB pulses.
  • a direct digital synthesis of pulses of ultra wide band type (UWB pulses) is thus proposed. More particularly, the phase accumulator of a direct digital frequency synthesis device with a phase increment having a chosen value is controlled so as to generate an output signal of the digital frequency synthesis device exhibiting an amplitude modulation whose envelope exhibits zero crossings.
  • the digital frequency synthesis device is moreover advantageously devised in such a way that the generated-signal part situated between two zero crossings of the envelope forms a pulse of the ultra wide band type (UWB pulse).
  • the digital frequency synthesis device thus devised is then controlled for example so as to isolate one or more pulses of UWB type.
  • a pulse is said to be of the ultra wide band type when, from the frequency point of view, it exhibits characteristics approaching those, generally accepted in this field, of an ultra wide band (UWB) pulse and when from the temporal point of view, its form approaches or is equal to that of an ideal UWB pulse.
  • UWB ultra wide band
  • a system for generating a pulse signal of the ultra wide band type comprising:
  • the digital frequency synthesis device comprises a phase accumulator able to deliver, at a first frequency, phases coded on i bits mutually spaced apart by a phase increment that is different from a power of two, greater than 2 i /3 and less than 2 i /3+2 i /2.
  • the digital frequency synthesis device moreover comprises processing means able to receive the said phases and designed to deliver an amplitude-modulated output signal whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude.
  • Each amplitude-modulated signal part situated in one of the said regions forms a pulse of the ultra wide band type whose central frequency is equal to the said first frequency and whose width depends on the value of the phase increment.
  • the control means are able to control the operation of the digital frequency synthesis device so as selectively to deliver one or more pulses of the ultra wide band type.
  • the inventors have in effect observed that the output signal generated by the digital frequency synthesis device was amplitude modulated as soon as the phase increment was different from a power of two. Furthermore, the fact that this phase increment is moreover greater than 2 i /3, that is to say in fact than a third of the maximum number of possible phases that can be delivered by the phase accumulator, and less than 2 i /3+2 i /2 made it possible to have an envelope of this amplitude modulation which exhibits zero crossings with moreover a signal portion between the zero crossings which is exploitable, that is to say with a relatively significant number of values.
  • the processing means of the digital frequency synthesis device have been devised in such a way that, between two zero crossings of the envelope, the latter exhibits a form substantially approaching the envelope of a UWB pulse.
  • the processing means can comprise a phase/amplitude converter, for example a memory, coupled to the output of the phase accumulator, and containing digital samples of a waveform corresponding to the envelope of the pulse of the ultra wide band type.
  • this waveform can be a portion of a sinusoid or else a Gaussian.
  • the processing means can comprise conversion means for generating a triangular analogue signal in response to the output signal delivered by the phase accumulator, and a differential pair of transistors, for example bipolar transistors, coupled to the output of the conversion means and able to generate the said pulse or pulses of ultra wide band type.
  • a differential pair of transistors for example bipolar transistors
  • the waveform to be generated comprising in general an axial symmetry, it is possible to choose the value of the phase increment in the span ]2 i /3;2 i /2[ or else in the span ]2 i /2;2 i /2+2 i /3[.
  • the control means are able to activate the phase accumulator from a first phase value which corresponds to a value of the signal generated at the output of the digital frequency synthesis device and which is situated within or in the vicinity of a first zone of zero amplitude of the said modulation envelope, up to a second phase value which corresponds to a value of the signal generated at the output of the digital frequency synthesis device and which is situated within or in the vicinity of a second zone of zero amplitude of the said modulation envelope, the said first zone and the said second zone being consecutive.
  • the system furthermore comprises control means able to adjust the value of the said first frequency and/or that of the phase increment so as to adjust in a controlled manner the central frequency and/or the bandwidth of each pulse of ultra wide band type.
  • the system can advantageously be embodied in the form of an integrated circuit, for example in CMOS or BiCMOS technology.
  • the method comprises several deliveries of the said phases of the phase accumulator respectively performed sequentially on command between the said pair of phases so as sequentially to generate several pulses of ultra wide band type.
  • digital samples representative of a waveform having a form analogous to that of the said envelope of the amplitude modulation are stored in the direct digital frequency synthesis device.
  • the direct digital frequency synthesis device comprises a differential pair of transistors, and during each delivery of phases by the phase accumulator a triangular analogue signal is delivered to the said differential pair of transistors on the basis of the values of the phases delivered.
  • the method furthermore comprises a controlled adjustment of the value of the said first frequency and/or of that of the phase increment so as to adjust in a controlled manner the central frequency and/or the bandwidth of each pulse of ultra wide band type.
  • FIG. 1 illustrates an exemplary embodiment of a system for generating a pulse signal according to the invention
  • FIG. 2 schematically illustrates a mode of implementation of a method according to the invention
  • FIG. 3 schematically illustrates an example of an output signal generated by a system according to the invention
  • FIG. 4 illustrates a variant of implementation of a method according to the invention
  • FIGS. 5 and 6 illustrate another exemplary embodiment of a system for generating a pulse signal of the UWB type according to the invention
  • FIG. 7 illustrates another mode of implementation of a method according to the invention
  • FIG. 8 illustrates an example of a pulse of UWB type generated by a system of the type of that illustrated in FIG. 5 ;
  • FIG. 9 illustrates a mode of control of a system for generating a pulse signal of the UWB type according to the invention.
  • the reference SYS designates in a general manner a system for generating a pulse signal of the ultra wide band type.
  • This system mainly comprises a direct digital frequency synthesis device DDS and control means MC able to control the operation of the digital synthesis device.
  • a direct digital frequency synthesis device DDS (“Direct Digital Synthesizer”) is a device generally known by the person skilled in the art for directly generating a periodic signal, generally sinusoidal, for example on the basis of certain samples stored in a memory.
  • the output signal is provided by a digital analogue converter and is optionally filtered.
  • the digital information provided to the digital analogue converter represents the instantaneous amplitude of the signal.
  • the successive samples of the signal may arise for example from a read-only memory.
  • the address applied to the input of the read-only memory represents the signal phase.
  • the latter is generated in general by a counter called a phase accumulator. The latter delivers the successive phases at the tempo of a first frequency and on the basis of a phase increment.
  • the phases are digital words which can be coded on i bits.
  • the maximum possible number of phases of different values capable of being delivered by the phase accumulator is then equal to 2 i .
  • the value of the phase increment will be chosen specifically, and the processing means MT of the DDS device, that is to say the means coupled at the output of the phase accumulator, will be designed to deliver an amplitude-modulated output signal whose envelope exhibits a succession of regions respectively delimited by zones of zero amplitude, each amplitude-modulated signal part situated in one of the said regions, forming a pulse of the ultra wide band type.
  • the phases PH are delivered at the frequency of a clock signal Clk 1 , this frequency being designated hereinafter by “first frequency”.
  • the processing means MT of the DDS device, coupled at the output of the phase accumulator ACCP, comprise in this example a phase-amplitude converter CVPA which gives the form of the signal.
  • the phase-amplitude converter can be a read-only memory, which contains the samples k of the waveform to be generated. These samples can be coded on n bits, n possibly being different from i.
  • the addresses of the memory forming the converter CVPA can also be coded on i bits.
  • the delivery of the phases of the phase accumulator is then equivalent to a linear scan of the memory, which is faster or slower depending on the phase increment ⁇ p.
  • phase-amplitude converter is also controlled by another clock signal Clk 2 .
  • this other clock signal may at a certain moment be identical in phase and in frequency to the clock signal Clk 1 .
  • the samples, or amplitudes, k, delivered by the phase-amplitude converter are delivered to a digital analogue converter DAC which converts the digital signal into an analogue signal SG, the latter optionally being filtered in a filter FLT so as to deliver the output signal SGF to the output terminal BS of the system SYS.
  • a filter FLT In the case where the filter FLT is not present, the output signal is then directly the signal SG.
  • UWB pulse Although there is no universal definition of an ideal UWB pulse, it is generally accepted, as regards its spectrum, that a UWB pulse exhibits a bandwidth of greater than 500 MHz or is greater than 20% of its central frequency. These definitions relate only to the frequency aspect. As regards the temporal aspect, there is no particular definition, but it may be accepted that the general form of a UWB pulse is the product of an envelope and a sinusoidal carrier of frequency equal to the central frequency of the UWB pulse. As regards the envelope, a Gaussian envelope most closely approaches the envelope of an ideal UWB pulse.
  • the phase accumulator ACCP delivers the successive phases mutually spaced apart by the increment ⁇ p at the first frequency F clk (step 21 ).
  • the signal SG is obtained at the output of the digital/analogue converter DAC.
  • this signal SG is an amplitude-modulated signal whose envelope ENV exhibits a succession of regions RG j ⁇ 1 , RG j , RG j+1 . . . . These regions are respectively delimited by zones of zero amplitude ZA, ZB.
  • the control means MC will activate the phase accumulator ACCP from a first phase value PHA ( FIG. 2 ) which corresponds to a value of the signal SG generated at the output of the digital frequency synthesis device DDS, and which is situated within or in the vicinity of a first zone of zero amplitude ZA of the modulation envelope ENV, up to a second phase value PHB which corresponds to a value of the signal SG and which is situated within or in the vicinity of a second zone ZB of zero amplitude of the modulation envelope ENV.
  • the first zone ZA and the second zone ZB are consecutive.
  • the inventors have observed that the frequency inscribed inside the envelope ENV is equal to the first frequency F clk . It is therefore independent of ⁇ p.
  • the signal inscribed in the envelope is a square signal, and is so whatever the waveform stored in the phase-amplitude converter. That said, other architectures are possible for the converter DAC leading to behaviours of blockers of order greater than zero.
  • phase increment ⁇ p controls only the period of the envelope ENV, that is to say the width of the UWB pulse.
  • the output frequency of the signal SG is then fixed and equal to the first frequency F clk . It is the central frequency of the UWB pulse.
  • a Gaussian pulse will be stored if one wishes to obtain a Gaussian envelope.
  • an ideal UWB pulse exhibits a Gaussian envelope and a sinusoidal carrier.
  • the spectrum of a Gaussian envelope is also a Gaussian while the fact of having a sinusoidal carrier makes it possible to transpose the spectrum of the envelope about a single frequency which is the central frequency of the UWB pulse.
  • the carrier is not sinusoidal, but for example square
  • the spectrum is transposed about the fundamental (central frequency) and also about its harmonics.
  • it will preferably be possible to minimize these harmonics, for example by using the filter FLT.
  • a digital/analogue conversion 221 is performed, optionally before a filtering 222 .
  • the processing means of the DDS device do not comprise any phase/amplitude converter (ROM memory for example), but comprise conversion means, for generating a triangular analogue signal in response to the output signal delivered by the phase accumulator ACCP, and a differential pair of transistors PDT coupled to the output of the conversion means and able to generate the said pulse or pulses of ultra wide band type.
  • ROM memory for example
  • conversion means for generating a triangular analogue signal in response to the output signal delivered by the phase accumulator ACCP, and a differential pair of transistors PDT coupled to the output of the conversion means and able to generate the said pulse or pulses of ultra wide band type.
  • the conversion means here comprise a controlled inverter IVC coupled to the phase accumulator, and an analogue digital conversion stage DAC coupled to the output of the controlled inverter.
  • the inverter IVC is controlled by the high-order bit MSB of the phase i delivered by the phase accumulator ACCP.
  • a register RG controlled by the clock signal Clk 2 , is connected between the output of the controlled inverter IVC and the digital analogue converter DAC.
  • the differential pair of transistors for example bipolar transistors, referenced PDT, is a differential pair of conventional structure.
  • the collectors of the two transistors form the outputs VSN 1 and VSN 2 of the differential pair.
  • Each collector is moreover linked to the supply voltage Vdd by way of a resistor R.
  • the processing 22 of the signal performed downstream of the phase accumulator therefore comprises here a controlled inversion 224 the effect of which is to transform the phase ramps into a digital triangular signal.
  • This digital triangular signal is converted into an analogue triangular signal by a digital/analogue conversion 225 before being delivered to the differential pair PDT.
  • the transfer function of the differential pair PDT makes it possible to transform the analogue triangular signal into a waveform comprising exponential portions, and which is closer to the Gaussian than the sinusoid. Therefore, in addition to the reduction in consumption and in integration area, resulting from the omission of the memory of the phase/amplitude converter, the use of a differential pair of transistors makes it possible to obtain a waveform whose envelope more nearly approaches the envelope of an ideal UWB pulse.
  • the signal SG delivered at the output of the DDS device provides, during continuous operation of the phase accumulator, a train of pulses.
  • One of these pulses IMP is illustrated in FIG. 8 . It is seen once again that it is possible to isolate such a pulse by operating the phase accumulator ACCP between two phases corresponding to the two crossings A, B of the envelope of the signal generated through or in the vicinity of the zones of zero amplitude ZA and ZB of the envelope of the signal.
  • FIG. 5 An exemplary embodiment and manner of operation of the control means MC of the system is illustrated in FIG. 5 and in FIG. 9 .
  • control means which may readily be embodied in the form of logic circuits on the basis of logic synthesis tools, or else in a software manner within a processor, comprise an input for receiving the first frequency or input frequency F clk . They also comprise another input for receiving a starting “start” pulse.
  • the control means MC also receive two phase values PHA and PHB corresponding respectively to the limits A and B of the useful sequence making it possible to isolate a pulse in the output signal SG.
  • the control means also receive the value R 1 of the register of the phase accumulator ACCP and deliver the two clock signals Clk 1 and Clk 2 , respectively to the register of the phase accumulator ACCP and to the register RG connected downstream of the controlled inverter.
  • the register R 1 has the value PHA and the clock signals Clk 1 and Clk 2 are inactive (zero value).
  • the signals Clk 1 and Clk 2 have the same phase and both take the frequency F clk . Stated otherwise the two signals are then identical.
  • the value R 1 of the register of the phase accumulator ACCP is then incremented with the phase increment ⁇ p at the tempo of the frequency F clk (step 93 ).
  • step 94 the clock signal Clk 2 is deactivated (step 95 ), while the clock signal Clk 1 continues to be active with the frequency F clk .
  • the effect of this is therefore to deliver a zero signal as output from the DDS device, this having made it possible to deliver between the points A and B a pulse IMP of the ultra wide band type.
  • the value R 1 of the register of the phase accumulator ACCP continues to be incremented (step 96 ), until it again attains the value PHA (step 97 ), thereby resetting the register to its quiescent state.
  • control means MCTL which will make it possible to deliver in a controlled manner the values of the frequencies F clk and of that of the increment ⁇ p.
  • control means can be embodied in logic circuit form or else realized in a software manner.
  • control means MCTL can also be present in the architecture illustrated in FIG. 5 .
  • control means MC which were described with reference to FIG. 5 can be used with the architecture of FIG. 1 .
  • Such a device can be readily embodied in BiCMOS or CMOS technology in an integrated manner.
  • the estimated consumption of a system SYS is of the order of 1.8 mW for a simple accumulator structure based on 9 bits with a frequency F clk of 1.7 GHz.
  • the phase/amplitude converter can for example be a digital algorithm making it possible to calculate the output sample on the basis of the input phase. This converter can even be omitted and its effect integrated into the digital/analogue converter which then becomes non-linear.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
US13/122,889 2008-10-07 2009-10-06 Method and system for generating a pulse signal of the ultra wide band type Active 2029-12-31 US8483630B2 (en)

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FR0856778A FR2936918B1 (fr) 2008-10-07 2008-10-07 Procede et systeme de generation d'un signal impulsionnel du type a bande ultra large
FR0856778 2008-10-07
PCT/EP2009/062962 WO2010040740A1 (fr) 2008-10-07 2009-10-06 Procede et systeme de generation d'un signal impulsionnel du type à bande ultra large

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US20090174440A1 (en) * 2008-01-04 2009-07-09 The Hong Kong University Of Science And Technology Frequency-hopping pulse-width modulator for switching regulators
DE102014019178B4 (de) * 2014-01-24 2016-08-18 Olympus Scientific Solutions Americas Inc. Paketbasierter direkter digitaler Synthesizer zur Minimierung von mathematischem Rauschen und Rauschen eines Digital-Analog-Konverters
US20170180000A1 (en) * 2014-07-25 2017-06-22 Allen-Vanguard Corporation System and method for ultra wideband radio frequency scanning and signal generation
US11277711B2 (en) 2019-06-19 2022-03-15 Samsung Electronics Co., Ltd. Electronic device for determining location information of external device

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DE102013208080A1 (de) * 2013-05-02 2014-11-06 Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik Empfänger, Anordnung und Verfahren für die Ultrabreitband-Übertragung
FR3068190B1 (fr) * 2017-06-27 2022-11-25 Uwinloc Procede et dispositif d’emission de messages uwb, procede et systeme d’estimation de position a partir de messages uwb
US11726790B2 (en) * 2019-12-12 2023-08-15 Intel Corporation Processor and instruction set for flexible qubit control with low memory overhead

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Cited By (6)

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Publication number Priority date Publication date Assignee Title
US20090174440A1 (en) * 2008-01-04 2009-07-09 The Hong Kong University Of Science And Technology Frequency-hopping pulse-width modulator for switching regulators
US8760141B2 (en) * 2008-01-04 2014-06-24 The Hong Kong University Of Science And Technology Frequency-hopping pulse-width modulator for switching regulators
DE102014019178B4 (de) * 2014-01-24 2016-08-18 Olympus Scientific Solutions Americas Inc. Paketbasierter direkter digitaler Synthesizer zur Minimierung von mathematischem Rauschen und Rauschen eines Digital-Analog-Konverters
US20170180000A1 (en) * 2014-07-25 2017-06-22 Allen-Vanguard Corporation System and method for ultra wideband radio frequency scanning and signal generation
US10122407B2 (en) * 2014-07-25 2018-11-06 Allen-Vanguard Corporation System and method for ultra wideband radio frequency scanning and signal generation
US11277711B2 (en) 2019-06-19 2022-03-15 Samsung Electronics Co., Ltd. Electronic device for determining location information of external device

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FR2936918B1 (fr) 2010-10-22
WO2010040740A1 (fr) 2010-04-15
FR2936918A1 (fr) 2010-04-09
US20110260757A1 (en) 2011-10-27

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