US8242844B2 - LNA circuit for use in a low-cost receiver circuit - Google Patents

LNA circuit for use in a low-cost receiver circuit Download PDF

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US8242844B2
US8242844B2 US12/824,927 US82492710A US8242844B2 US 8242844 B2 US8242844 B2 US 8242844B2 US 82492710 A US82492710 A US 82492710A US 8242844 B2 US8242844 B2 US 8242844B2
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transistor
lna
signal
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US20110316631A1 (en
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Aslamali A. Rafi
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Silicon Laboratories Inc
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Priority to CN201110190751.0A priority patent/CN102386856B/zh
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/534—Transformer coupled at the input of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/72—Indexing scheme relating to amplifiers the amplifier stage being a common gate configuration MOSFET
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45306—Indexing scheme relating to differential amplifiers the common gate stage implemented as dif amp eventually for cascode dif amp
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45621—Indexing scheme relating to differential amplifiers the IC comprising a transformer for phase splitting the input signal

Definitions

  • the present disclosure is generally related to amplifiers, and more particularly, to low noise amplifiers (LNAs).
  • LNAs low noise amplifiers
  • tuner circuitry capable of processing analog terrestrial, digital terrestrial, and cable broadcasts with low cost and small size.
  • Such tuner circuitry may be configured to handle signals with broadband input frequencies ranging from 54 MHz to 880 MHz, and thus require a wideband LNA with sufficiently high linearity and a low noise figure well below 3 dB in order to obtain high sensitivity.
  • Narrow-band receivers such as Code-Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), short-range wireless receivers, and terrestrial digital multimedia broadcasting (T-DMB) receivers, are typically configured to tune to channels where the ratio of maximum frequency to minimum frequency is less than two.
  • CDMA Code-Division Multiple Access
  • GSM Global System for Mobile Communications
  • T-DMB terrestrial digital multimedia broadcasting
  • the IIP2 and IIP3 of the LNA are important because, in the frequency band of reception (54 MHz to 880 MHz), there can be an interfering channel with a frequency that is half or a third of the desired frequency channel, which interfering channel, through second order or third order distortion, respectively, can land at the frequency of interest and corrupt the picture quality.
  • Such second or third order distortion products are called HD2 (harmonic distortion 2) and HD3 (harmonic distortion 3), respectively.
  • NF Noise Figure
  • a single-ended-to-differential amplifier represents a good configuration for integration and can provide moderate IIP2 performance.
  • conventional single-ended-to-differential amplifiers typically have a relatively high NF.
  • the high NF degrades sensitivity of the tuner circuitry, making it difficult to use an LNA on the first stage in a wideband tuner.
  • FIG. 1 is a partial block and partial schematic diagram of a conventional, single-ended input, differential output, low-noise amplifier (LNA) with a balanced load.
  • LNA low-noise amplifier
  • FIG. 2 is a partial block and partial schematic diagram of a conventional, differential-input, differential output, LNA with a balanced load and a balun circuit.
  • FIG. 3 is a partial block and partial schematic diagram of a balunless LNA circuit configurable for use with a tuner circuit.
  • FIG. 4 is a block diagram of an embodiment of a device including the LNA circuit of FIG. 3 .
  • FIG. 5 is a diagram of another embodiment of a device including the LNA circuit of FIG. 3 coupled to a passive mixer.
  • FIG. 6 is a diagram of still another embodiment of a device including the LNA of FIG. 3 coupled to a mixer through a resistive load.
  • LNA low-noise amplifier
  • IIP2 second-order input-referred intercept point
  • Coupled is used to refer to components that are directly connected or are joined or linked by indirect connection. It should understood that the illustrated embodiments are for illustrative purposes only, and that direct connections illustrated within the drawings may include elements and/or intervening components that are not shown.
  • FIG. 1 is a partial block and partial schematic diagram of a conventional, single-input, differential-output low-noise amplifier (LNA) circuit 100 with a balanced load.
  • LNA circuit 100 includes a LNA 102 , which is coupled to a signal source 104 and to a load circuit 106 .
  • Load circuit 106 can be a tuner, switches of a mixer, or other circuitry.
  • Signal source 104 can be an antenna or other circuitry for receiving a broadband signal.
  • Signal source 104 models an antenna as a voltage source 108 that applies a signal to a resistance 110 , such as a 75 Ohm resistor.
  • the resistor 110 is coupled to a pin 112 of LNA 102 .
  • LNA 102 includes pin 112 and a second pin 114 , which is coupled to ground.
  • LNA 102 further includes resistors 116 and 118 , transistors 126 and 128 , and capacitors 120 and 122 .
  • Resistor 116 has a first terminal coupled to pin 112 and a second terminal coupled to a source of a transistor 126 , which is an n-channel metal oxide semiconductor field effect transistor (NMOSFET).
  • Transistor 126 includes a gate coupled to pin 114 through capacitor 114 , and a drain coupled to balanced load circuit 106 .
  • Resistor 118 includes a first terminal coupled to pin 114 and a second terminal coupled to a source of transistor 128 .
  • Transistor 128 further includes a gate coupled to pin 112 through capacitor 122 and a drain coupled to balanced load circuit 106 .
  • transistors 126 and 128 , capacitors 120 and 122 , and resistors 116 and 118 are substantially matched, providing a balanced circuit.
  • signal source 104 provides radio frequency (RF) signals to pin 112 , and pin 114 is coupled to ground.
  • the RF input at pin 112 is applied to transistor 126 and resistor 116 and is provided to the gate of transistor 128 .
  • Small signal (high frequency) current (i) flows from drain to source through transistor 126 and from source to drain through transistor 128 .
  • Vs voltage signal source
  • the current (i) is the same through both transistors 126 and 128 .
  • a differential output current is produced from a single ended voltage input.
  • radio frequency refers to a signal having a frequency within a range from approximately 3 kHz to hundreds of Gigahertz.
  • High frequency signals or small signals refer to AC components or RF components of the signal.
  • Equation 1 the variable (R) represents the resistance of each of the resistors 116 and 118 and the variable (gm) represents the transconductance of each of transistors 126 and 128 .
  • an optimized noise figure of LNA 102 is as high as 6 dB.
  • the noise figure of 6 dB is not acceptable for terrestrial applications.
  • the IIP2 was only 40 dBm (the power ratio referenced to one milliwatt), which is insufficient for cable applications for which 50 dBm is a typical threshold.
  • the common source stage represented by transistor 128 contributes significant noise to the signal, adversely affecting the noise figure (NF) and sensitivity of the system while giving insufficient IIP2 performance.
  • balun circuit such as an external transformer, is used to convert the single-ended input into a differential input through electromagnetic coupling.
  • An example of an LNA circuit that uses a balun circuit is described below with respect to FIG. 2 .
  • FIG. 2 is a partial block and partial schematic diagram of a conventional, dual-input LNA circuit 200 , including the LNA 102 of FIG. 1 and including a balun circuit 206 .
  • signal source 104 is replaced with a signal source 204 that includes balun circuit 206 (depicted as a simple transformer).
  • the voltage signal source (Vs) 108 depicted in FIG. 1 is divided into input sources 208 and 210 , each of which are approximately half of the voltage signal source (Vs), i.e., Vs/2.
  • Signal source 204 includes resistors 212 and 214 , each of which is approximately 37.5 ⁇ or half of the resistance of resistor 110 in FIG. 1 .
  • signal source 204 divides the balanced, single-ended input signal (which may be received from an antenna or other signal source) into an unbalanced signal using passive transformer 206 as a balun, and provides the resulting signals to LNA 102 at pins 112 and 114 .
  • the small signal voltages appear across transistor 126 and 128 , causing small signal current (i) to flow from drain to source through transistor 126 and from source to drain through transistor 128 , as shown.
  • Diagram 200 further includes an equivalent circuit 220 illustrating the effective impedance 222 of LNA circuit 202 .
  • the effective impedance of LNA 102 is determined from the resistance of resistors 116 and 128 plus one over the transconductance (gm) of transistors 126 and 128 , which is approximately 25 ⁇ .
  • the effective impedance is defined by Equation 2 below.
  • the small signal current (i) flowing in both networks is the same. Further, the voltage across the effective 25 ⁇ resistance is approximately the same as the voltage across the transconductor.
  • the noise figure is dominated by the 25 ⁇ impedance.
  • the fully differential LNA illustrated in FIG. 2 can provide excellent IIP2 performance over a wide frequency band
  • a drawback of circuit 200 is that the passive transformer 206 is required.
  • Such a passive transformer is typically too bulky to be integrated on the chip, and its insertion loss degrades the receiver's noise figure and its sensitivity. To avoid such degradation, low-loss and expensive external transformers are used, increasing both the size and expense of the circuitry.
  • FIG. 3 is a partial block and partial schematic diagram of an embodiment of a circuit 300 including a single-input, balunless LNA 302 configurable for use with a tuner circuit.
  • Circuit 300 includes a signal source, such as an antenna, a broadband connection, or other signal source.
  • the signal source is represented by voltage signal source (Vs) 108 , which provides RF signals to LNA 302 .
  • the voltage signal source (Vs) 108 is capacitively coupled to inputs 112 and 114 through capacitors 304 and 306 , respectively, which operate to block direct current and low frequency signals.
  • LNA 302 includes a direct current (DC) current source, represented by inductor 308 coupled to a regulated supply voltage (Vreg). Inductor 308 is coupled to pin 112 for injecting a DC current (I dc ) into the pin 112 .
  • LNA 302 further includes a resistor 310 having a first terminal coupled to pin 112 and a second terminal coupled to a source of transistor 312 , which includes a gate coupled to bias circuitry 311 , and a drain coupled to a source of transistor 314 .
  • Transistor 314 further includes a gate coupled to bias circuitry 311 and a drain coupled to an output node 321 .
  • the gates of transistors 312 and 314 appropriately biased by bias circuitry 311 to permit the DC current (I dc ) to flow through transistors 312 and 314 . From a RF signal point of view, the gates of transistors 312 and 314 can be thought of as being at ground.
  • LNA 302 further includes an NMOS transistor 316 including a drain coupled to output node 321 , a gate coupled to bias circuitry 311 , and a source coupled to a drain of NMOS transistor 318 , which also includes a gate coupled to bias circuitry 311 and a source coupled to pin 114 through resistor 320 .
  • a second current source, represented by inductor 302 couples pin 114 to a supply terminal, which may be a negative supply terminal or which may include other circuitry.
  • Capacitor 306 blocks DC current flow to voltage signal source (Vs) 108 , forcing the DC current (I dc ) into inductor 313 .
  • bias circuitry 311 details of bias circuitry 311 are omitted for the sake of simplicity.
  • any biasing circuitry including operational amplifiers, control circuits, voltage divider circuits, or other appropriate circuitry can be used to bias transistors 312 , 314 , 316 and 318 sufficiently to allow current flow through the transistors.
  • output node 321 is coupled to a mixer.
  • the inductor 322 and variable capacitor 324 form a tunable band-pass LC filter, also known as a tracking filter.
  • Fixed capacitor 328 and variable capacitor 326 form a capacitive attenuator network that is used to reduce the gain prior to the mixer in the presence of strong signals.
  • the LNA transconductor comprised of resistors 310 and 320 and transistors 312 , 314 , 316 , and 318 is shown coupled to a tracking filter and capacitive attenuator comprised of inductor 322 and capacitors 324 , 326 and 328 , other embodiments are also possible.
  • the LNA transcondutor could be coupled to switches of a passive mixer (as depicted in FIG. 5 ) or to a simple resistive load (as illustrated in FIG. 6 ).
  • the gates of PMOS transistors 312 and 314 and NMOS transistors 316 and 318 are biased to permit DC current (I dc ) to flow.
  • the gates of transistors 312 , 314 , 316 , and 318 receive no small signal currents.
  • the RF input signal (i in ) produced by voltage signal source (Vs) 108 flows through resistor 110 and divides substantially evenly to flow into pins 112 and 114 .
  • the inductors 313 and 308 operate as open circuits with respect to the small signal inputs (i in /2), forcing the small signal inputs (i in /2) to flow through PMOS transistors 312 and 314 and through NMOS transistors 316 and 318 to output node 321 , which carries the small signal output current (i out ).
  • the impedance (Zchip) of the LNA 302 (as seen looking into pins 112 and 114 ) is determined according to the following equation:
  • Equation 3 the resistance (2R) is twice the resistance (R) of the resistors 116 and 118 in circuits 100 and 200 in FIGS. 1 and 2 .
  • the variable (gm) represents the transconductance of transistors 312 and 316 . Equation 3 can be simplified as shown in Equation 4 below:
  • the equivalent circuit 330 depicts the input resistance 110 and voltage signal source (Vs) 108 and illustrates the input impedance (Zchip) of the LNA 302 , which is represented by resistor 332 .
  • the simplified circuit 302 has the same equivalent circuit as the differential circuit 200 in FIG. 2 .
  • the noise figure is better than the differential case.
  • the NF of the trasnconductor can be approximated according to Equation 5 below:
  • the NF is about 0.7 dB.
  • the off-chip balun can have a loss of about 1.3 dB, further degrading the total NF to about 2 dB.
  • the single ended transconductor of FIG. 3 has an NF that can be approximated according to the Equation 6 below:
  • the NF of LNA 302 is 1.25 dB. Since an off-chip balun is not used, the total NF is also 1.25 dB, which is better than the 2 dB NF of the differential case with the balun. Furthermore, for a given voltage signal source (Vs) 108 , the small signal current (i) flowing into the LNA remains the same as in the differential case, and hence gain is also the same.
  • Vs voltage signal source
  • LNA 302 is similar to the LNA 102 in FIG. 1 .
  • IIP3 input-referred intercept point
  • the IIP3 of LNA 302 is described below with respect to Equation 7.
  • the second-order input-referred intercept point is also improved, as compared to the single-end input LNA 102 in FIG. 1 .
  • the IIP2 is improved by using conventional push-pull complementary stages.
  • Second order distortion is characterized by asymmetric positive and negative half cycles. During the positive half cycle, NMOS transistors 316 and 318 have a small “on” voltage (Von), while PMOS has a larger “on” voltage (Von). During the negative half cycle, the opposite is true. If NMOS and PMOS transistors 312 and 318 match, then the second order distortion cancels. However, process variations that cause NMOS transistor 318 to be different from PMOS transistor 312 can cause the IIP2 to change.
  • the “on” voltages of PMOS and NMOS transistors 312 , 314 , 316 , and 318 are opposite, balancing out. Further, using source degeneration resistors 310 and 320 desensitizes the “effective” on voltage (voltage across resistors plus “on” voltage of transistors) variations across process corners.
  • LNA 302 has a satisfactory IIP2 across process corners, which exceeds 50 dBm.
  • Table 1 below depicts the IIP2 of one specific example of LNA 302 where the PMOS transistors 312 and 314 had width/length ratios that were 2.00 times that of NMOS transistors 316 and 318 .
  • PROCESS CORNER IIP2 (dBm) Typical-Typical (TT) 54 Slow NMOS Fast PMOS (SNFP) 61 Fast NMOS Slow PMOS (FNSP) 51 Fast NMOS Fast PMOS (FNFP) 56 Slow NMOS Slow PMOS (SNSP) 53
  • LNA 302 exceeds 50 dBm at all process corners. Further, trimming devices can be added, which change the ratio PMOS W/L to NMOS W/L, to fine tune performance. However, even at the 2.00 ⁇ difference between the PMOS and NMOS devices, performance falls within the acceptable range.
  • the DC current (I dc ) is approximately equal to one-fourth of a differential current (I differential ), representing a 4 ⁇ current savings over a conventional LNA.
  • each NMOS transistor 126 and 128 has a transconductance of gm and each single-ended brand drew a DC current of I diff /2.
  • the PMOS and NMOS transistors 312 , 314 , 316 , and 318 each transistor 312 , 314 , 316 , and 318 has a transconductance of gm/2 while sharing the same DC current. This implies that the current drawn is one-quarter of the differential current (I diff ) as follows:
  • LNA 302 has noise figure, IIP2, IIP3, and gain parameters that satisfy terrestrial TV signal processing requirements, while using less DC current.
  • Table 2 represents a simulation performance summary and comparison of LNA 302 with LNA 102 in FIG. 2 , for example, with a corresponding 440 Ohm load, transconductance of NMOS and PMOS being 40 mS each and resistors 310 , 320 in FIG. 3 each being 25 ohms, the following performance is obtained.
  • the CMOS LNA 302 without the balun substantially matches performance of the LNA 102 with the balun.
  • the NF of LNA 302 is better than that of LNA 102 , while IIP2, IIP3 and Gain numbers are comparable between the two.
  • DC current drawn by LNA 302 is 75% less than that drawn by LNA 102 .
  • Performance of the LNA 302 across process corners can be adjusted for a particular implementation. In particular, at design time, the width/length (W/L) ratio of PMOS 312 and the W/L of NMOS 318 can be designed to optimize the IIP2 performance across process corners.
  • FIG. 4 is a block diagram of a device 400 including the LNA 302 of FIG. 3 .
  • Device 400 further includes an antenna 402 , connector 404 , pin 405 , and capacitive filter and capacitive attenuator 406 , which includes an output coupled to a single input to differential output converter 408 , which is coupled to a double balanced harmonic rejection mixer (HRM) 410 .
  • HRM double balanced harmonic rejection mixer
  • the CMOS LNA 302 obtains a noise figure of 2.6 dB, a gain of 18 dB, and IIP2 of 50 dBm, an IIP3 of 25 dBm, and a DC current of approximately 10 mA.
  • the single-ended capacitive filter and capacitive attenuator 406 provides a single-ended transfer function that provides the same load as a differential load.
  • the single input to differential output converter 408 obtains a noise figure of 9 dB, a gain of 0 dB, an IIP3 of 15 dBm, and a DC current of approximately 15 mA.
  • HRM 410 obtains a noise figure of 12 dB, a gain of 19 dB, and an IIP3 of 12 dBm.
  • the 30 mA current saved by using LNA 302 as compared to LNA 102 can be used to provide power to other circuitry.
  • part of the saved 30 mA can be used in the single ended to differential output converter 408 to supply the 15 mA.
  • FIGS. 1-4 are illustrative only.
  • the gains, decibel levels, and currents were provided for illustrative purposes. Such values may be appropriate for particular implementations and/or may vary across different circuit implementations.
  • FIG. 5 is a diagram of another embodiment of a device 500 including the LNA circuit 302 of FIG. 3 coupled to a passive mixer 502 , which is configured to receive the output current (i out ) and to produce a multi-phase intermediate frequency (IF) output signal, which can be provided to other circuitry, such as a filter, an IF amplifier, a processor, and/or other circuitry configured to process the IF output signal.
  • a passive mixer 502 configured to receive the output current (i out ) and to produce a multi-phase intermediate frequency (IF) output signal, which can be provided to other circuitry, such as a filter, an IF amplifier, a processor, and/or other circuitry configured to process the IF output signal.
  • IF intermediate frequency
  • While the LNA 302 of FIG. 3 is coupled to a mixer through an LC network and the LNA 302 of FIG. 5 is coupled to a passive mixer without intervening circuitry, other embodiments may include resistive loads or other circuitry between the LNA 302 and the mixer.
  • An example of an embodiment of a device is described below with respect to FIG. 6 that includes LNA 302 coupled to a resistive load and a mixer.
  • FIG. 6 is a diagram of still another embodiment of a device 600 including the LNA 302 of FIG. 3 coupled to a mixer through a resistive load 602 .
  • the resistive load includes a first terminal coupled to output node 321 and a second terminal coupled to a voltage source, such as a V MID (a buffered voltage at approximately a mid-point between a power supply rail and ground).
  • V MID a buffered voltage at approximately a mid-point between a power supply rail and ground.
  • LNA 302 may be used in a variety of devices to provide low-noise amplification with reduced power consumption (as compared to the differential LNA 102 of FIG. 1 ). Further, while LNA 302 has been depicted with input pins 112 and 114 for receiving the input signals from a signal source, such as antenna 402 , it should be understood that pins 112 and 114 may be eliminated and that a single pin or input terminal may be used to provide the input signal to capacitors 304 and 306 , which may be on-chip capacitors.
  • a highly linear single-ended, balunless LNA 302 is presented that achieves an IIP3 of 25 dBm, an IIP2 of 50 dBm (over process corners), and a noise figure of 2.6 dB while consuming only 10 mA of current.
  • the reflection loss achieved is about ⁇ 6 dB.
  • the LNA lowers costs by eliminating the balun while adding only one off-chip inductor and one capacitor to the bill of materials.
  • the current savings is approximately 30 mA, which current may be used to provide power to other circuitry, thereby conserving overall power consumption.

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US12/824,927 US8242844B2 (en) 2010-06-28 2010-06-28 LNA circuit for use in a low-cost receiver circuit
DE102011077566.8A DE102011077566B4 (de) 2010-06-28 2011-06-15 LNA-Schaltkreis zum Gebrauch in einem kostengünstigen Receiver-Schaltkreis
CN201110190751.0A CN102386856B (zh) 2010-06-28 2011-06-27 用于低成本接收机电路的lna电路
US13/564,592 US8629723B2 (en) 2010-06-28 2012-08-01 Low noise amplifier including a single-ended input

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US8629723B2 (en) 2014-01-14

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