US8134233B2 - Method and apparatus for providing electrically isolated closely spaced features on a printed circuit board - Google Patents

Method and apparatus for providing electrically isolated closely spaced features on a printed circuit board Download PDF

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Publication number
US8134233B2
US8134233B2 US11/830,348 US83034807A US8134233B2 US 8134233 B2 US8134233 B2 US 8134233B2 US 83034807 A US83034807 A US 83034807A US 8134233 B2 US8134233 B2 US 8134233B2
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Prior art keywords
entity
entities
fracture
stress
sub
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Expired - Fee Related, expires
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US11/830,348
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English (en)
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US20090034215A1 (en
Inventor
Jerzy Wielgus
Daniel R. Gamota
Tomasz L. Klosowiak
John B. Szczech
Kin P. Tsui
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Motorola Solutions Inc
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Motorola Solutions Inc
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Priority to US11/830,348 priority Critical patent/US8134233B2/en
Assigned to MOTOROLA, INC. reassignment MOTOROLA, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GAMOTA, DANIEL R., WIEGLUS, JERZY, KLOSOWIAK, TOMASZ L., SZCZECH, JOHN B., TSUI, KIN P.
Priority to PCT/US2008/069003 priority patent/WO2009017928A2/en
Priority to EP08772355A priority patent/EP2174534A2/de
Priority to CN200880101209.XA priority patent/CN101772993A/zh
Publication of US20090034215A1 publication Critical patent/US20090034215A1/en
Assigned to MOTOROLA SOLUTIONS, INC. reassignment MOTOROLA SOLUTIONS, INC. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: MOTOROLA, INC
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0293—Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/695—Organic materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105—Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/17—Post-manufacturing processes
    • H05K2203/175—Configurations of connections suitable for easy deletion, e.g. modifiable circuits or temporary conductors for electroplating; Processes for deleting connections
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing

Definitions

  • the present invention relates generally to fine features in metal circuitry on printed circuit boards, and more particularly, to a method for creating fine features using thermal and mechanical stressing.
  • FIG. 1 is a partial isometric view of a substrate having features formed thereon in accordance with some embodiments of the invention.
  • FIG. 2 is a partial isometric view of the substrate of FIG. 1 being exposed to a flash of light in accordance with some embodiments of the invention.
  • FIG. 3 is a partial cross sectional view of FIG. 2 through section 2 - 2 in accordance with some embodiments of the invention.
  • FIG. 4 is a partial cross sectional view of FIG. 3 after exposure to light in accordance with some embodiments of the invention.
  • FIG. 5 is a partial isometric view of FIG. 4 in accordance with some embodiments of the invention.
  • FIG. 6 is a partial cross sectional view of one embodiment of a transistor in accordance with the invention.
  • embodiments of the invention described herein may be comprised of conventional elements arranged in a non-conventional way, as described herein.
  • the embodiments may be used in various circuits, such as but not limited to, a radio receiver, a radio transmitter, signal drivers, clock circuits, power source circuits, and user input devices. Accordingly, methods and means for achieving these functions have been described herein. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such embodiments with minimal experimentation.
  • a method of forming controlled stress fractures in metal produces electrically isolated closely spaced circuit sub-entities for use on a printed wiring board is described herein.
  • a polymeric substrate has a layer of metal adhered to the surface, and the metal layer is formed into entities.
  • Each entity has a fracture initiating feature formed into it, which serves to initiate and/or direct a stress crack that is induced in the metal.
  • the entities are fractured in a controlled manner by subjecting the substrate and the entities to mechanical stress by a rapid thermal excursion, creating a stress fracture in the entity extending from the fracture initiating feature.
  • the stress fracture divides each entity into two or more sub-entities that are electrically isolated from each other by the stress fracture.
  • the resulting structure can be used to form circuitry requiring very fine spaces between conductors on, for instance, high density printed circuit boards.
  • a transistor structure is formed.
  • the rapid thermal stress may be induced by means of a high intensity arc lamp such as found in xenon strobe lighting.
  • an electrically insulating material serves as a substrate 10 to form printed circuitry thereon.
  • the substrate 10 is typically a polymer or blend of polymers such as polyesters, polyimides, polyamides, polyamide-imides, polyetherimides, polyacrylates, polyethylene terephthalate, polyethylene, polypropylene, polyvinylidene chloride, and polysiloxanes, polycarbonates, polyolefins, polymethyl methacrylate, fabrics, or paper.
  • the polymers may also contain various amounts of conventional fillers as is known in the art for enhanced physical and/or electrical performance, such as glass fibers, carbon fibers, carbon nanotubes, polyimide fibers, etc.
  • the metal layer 11 consists of one or more entities 12 that are typically lines or runners for carrying electrical signals, or they are pads or terminations for attachment of surface mounted components. Certain entities 12 contain one or more fracture initiating features 14 , 54 on a perimeter portion of the entity and/or in the interior portion of the entity.
  • the feature 14 can encompass a number of shapes, but generally a shape having a sharp point or portion is preferable. Since the coefficient of thermal expansion (CTE) of the substrate 10 is much greater than the CTE of the metal entity 12 , an increase in the temperature of the substrate and entity will mechanically stress the metal entity. Increasing the temperature will generally develop tension in the metal layer and low compression in the underlying substrate since the substrate is usually much thicker than the metal layer. Tensile stress in conjunction with the fracture initiating features will initiate and propagate a stress crack in the metal entity when the induced mechanical stress reaches a certain level. The amount of stress required to initiate a fracture will vary with each metal and metal/polymer combination.
  • CTE coefficient of thermal expansion
  • the fracture initiating feature 14 is essentially a “defect” that is intentionally formed in the entity, and serves as a stress concentration point in each entity to relieve the stress by initiating a fracture.
  • the stress fractures 45 extend away from the fracture initiating features, 14 into an interior portion of the affected entities, so as to form two or more sub-entities 42 from the entity.
  • Each sub-entity 42 is now electrically isolated from an adjacent sub-entity by the stress fracture.
  • a printed circuit board 5 now contains a number of sub-entities that are closely spaced, but electrically isolated from each other.
  • a layer of metal or conductive ink 11 Situated on and firmly adhered to a major surface of the substrate 10 is a layer of metal or conductive ink 11 , such as copper, aluminum, chromium, gold, iron, nickel, palladium, platinum, silver, titanium, tin, tungsten, zinc, or other conductive matrices containing these metals of alloys thereof.
  • the metal layer 11 consists of one or more entities 12 that are typically lines or runners for carrying electrical signals, or they are pads or terminations for attachment of surface mounted components.
  • Fracture initiating features 14 are formed on a perimeter portion of one or more of the entities and/or in the interior portion of the entity during the patterning process. Although depicted in the drawing figures as a portion of a triangle, the feature 14 can encompass a number of shapes, but generally a shape having a sharp point or portion is preferable.
  • CTE coefficient of thermal expansion
  • a suitable source 29 is a photonic curing system sold by NovaCentrix Company that uses a strobed xenon arc lamp (140-500 nanometers wavelength) which is driven by a 3000 Watt high voltage power supply.
  • a trigger circuit adjusts the strobe energy output between about 10 and about 1000 Joules, the pulse duration ranges from 20 to 500 micro-seconds, and the strobe rate can be adjusted from a single pulse-to-pulse rate of up to 2 kilohertz.
  • FIG. 3 a cross sectional view through section 2 - 2 of FIG.
  • the heat energy from source 29 that impinges upon the assembly causes the metal entity 12 to expand laterally as shown by arrows 38 , and causes the substrate 10 to also expand laterally, but at a much larger rate as shown by the large arrows 37 .
  • This mismatch in expansion creates a large amount of mechanical stress (tensile stress) in the metal entity, and causes it to fracture.
  • the amount of stress required to initiate fracture will vary with each metal and metal/polymer combination. Since the fracture-initiating feature 14 is essentially a “defect” that is intentionally formed in the entity, it serves to concentrate the stress at that point.
  • the stress fracture 45 has now caused the entity 12 to be separated into two sub-entities 42 that are electrically isolated by the narrow channel formed by the fracture 45 .
  • FIG. 5 it can be seen that the stress fractures originate from the apex of the fracture initiating feature 14 and extend into the interior of the entity 12 . If one were to locate a fracture initiating feature 54 in the interior portion of the entity instead of around the perimeter, then one could induce a number of fractures, each extending radially from the apexes of fracture initiating feature 54 .
  • the polymeric substrate prior to subjecting the entities to rapid thermal stress, is mechanically bent in a convex shape directed away from the major surface, such that an apex of the bend is preferably disposed directly below the fracture initiating feature.
  • This type of bend will develop close to unidirectional tensile stresses on the surface of the metal, which in turn creates a preferential direction for stress crack propagation parallel to the bend axis.
  • a fracture guiding feature 15 can also be formed on or in a major surface of the entity, rather than on the vertical wall of an exterior portion. The feature does not extend completely through the metal, and can be formed by scratching or milling the metal surface.
  • a very thin layer of aluminum was deposited on a polyethylene terephthalate substrate by sputtering.
  • the aluminum layer was then patterned into a series of entities that contained fracture initiating features.
  • the patterned assembly was subsequently subjected to a single 300 micro-second pulse from the NovaCentrix xenon strobe light at 1800 volts. After returning to ambient temperature, inspection revealed that a 3 micron channel was formed in the aluminum layer.
  • the fractured entities are used as elements in a transistor structure.
  • closely spaced entities 62 A and 62 B are formed using the methods described above.
  • a semiconductor element 67 is deposited in the gap formed by the stress fracture between adjacent entities 62 A, 62 B, and a dielectric material 68 is deposited over the semiconductor element.
  • a gate electrode 69 is then formed on the dielectric material 68 , to create a transistor, where entities 62 A, 62 B form the source and drain electrodes.
  • An alternate embodiment of the transistor finds a bottom gate structure wherein a portion of the metal layer acts as a gate electrode, a dielectric material is disposed over the gate electrode, source and drain electrodes are disposed over the dielectric material, and a semiconductor element is disposed on the dielectric between the source and drain electrodes or over the source and drain electrodes.
  • a method is disclosed to generate micron sized channels between circuit electrodes by inducing crack propagation via a thermal, chemical or mechanical process or combination there of.
  • a printed circuit board can now contain a number of sub-entities that are closely spaced, but electrically isolated from each other, using patterning or deposition techniques that are low to medium resolution.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
US11/830,348 2007-07-30 2007-07-30 Method and apparatus for providing electrically isolated closely spaced features on a printed circuit board Expired - Fee Related US8134233B2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US11/830,348 US8134233B2 (en) 2007-07-30 2007-07-30 Method and apparatus for providing electrically isolated closely spaced features on a printed circuit board
PCT/US2008/069003 WO2009017928A2 (en) 2007-07-30 2008-07-02 Method and apparatus for providing electrically isolated closely spaced features on a printed circuit board
EP08772355A EP2174534A2 (de) 2007-07-30 2008-07-02 Verfahren und vorrichtung zur bereitstellung von elektrisch isolierten dicht beabstandeten strukturelementen auf einer leiterplatte
CN200880101209.XA CN101772993A (zh) 2007-07-30 2008-07-02 在印刷电路板上提供电隔离的紧密间隔特征的方法和装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/830,348 US8134233B2 (en) 2007-07-30 2007-07-30 Method and apparatus for providing electrically isolated closely spaced features on a printed circuit board

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US20090034215A1 US20090034215A1 (en) 2009-02-05
US8134233B2 true US8134233B2 (en) 2012-03-13

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US (1) US8134233B2 (de)
EP (1) EP2174534A2 (de)
CN (1) CN101772993A (de)
WO (1) WO2009017928A2 (de)

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US8158510B2 (en) * 2009-11-19 2012-04-17 Stats Chippac, Ltd. Semiconductor device and method of forming IPD on molded substrate
US8111903B2 (en) * 2008-09-26 2012-02-07 International Business Machines Corporation Inline low-damage automated failure analysis
JP2013191690A (ja) * 2012-03-13 2013-09-26 Shin Etsu Chem Co Ltd 半導体装置及びその製造方法
DE102012214440B3 (de) * 2012-08-14 2013-10-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Planaroptisches Element, Sensorelement und Verfahren zu deren Herstellung
US10656137B2 (en) * 2015-09-21 2020-05-19 Ethan Pfeiffer Method for producing a nano-gap in a brittle film assisted by a stabilizing substrate

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Ki Wan Kim, "PCT International Search Report and Written Opinion," WIPO, ISA/KR, Korean intellectual Property Office, Daejeon, Republic of Korea, Mar. 13, 2009, 10 pages.

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Publication number Publication date
WO2009017928A2 (en) 2009-02-05
CN101772993A (zh) 2010-07-07
WO2009017928A3 (en) 2009-05-22
EP2174534A2 (de) 2010-04-14
US20090034215A1 (en) 2009-02-05

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