US8105878B2 - Manufacturing method of a semiconductor device having a package dicing - Google Patents

Manufacturing method of a semiconductor device having a package dicing Download PDF

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Publication number
US8105878B2
US8105878B2 US11/833,606 US83360607A US8105878B2 US 8105878 B2 US8105878 B2 US 8105878B2 US 83360607 A US83360607 A US 83360607A US 8105878 B2 US8105878 B2 US 8105878B2
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Prior art keywords
tape
pickup
dicing
csp
thermosetting
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US11/833,606
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US20080076210A1 (en
Inventor
Haruhiko Harada
Takao Matsuura
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of US20080076210A1 publication Critical patent/US20080076210A1/en
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the present invention relates to a semiconductor manufacturing technique and more particularly to a technique which can be effectively applied to a semiconductor device assembling method having a package dicing (dicing after resin molding) process.
  • FIG. 1 is a process flow chart showing an example of a procedure for assembling a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a manufacturing process flow chart showing an example of assembling steps up to resin molding in assembling the semiconductor device according to the embodiment
  • FIG. 3 is a manufacturing process flow chart showing an example of assembling steps after resin molding in assembling the semiconductor device according to the embodiment
  • FIG. 4 is a process flow chart showing an example of detailed processings in a chip pickup process according to the embodiment
  • FIG. 5 is a plan view showing a structural example of a dicer and that of a picker both used in assembling the semiconductor device according to the embodiment
  • FIG. 1 is a process flow chart showing an example of a procedure for assembling a semiconductor device according to an embodiment of the present invention
  • FIG. 2 is a manufacturing process flow chart showing an example of assembling steps up to resin molding in assembling the semiconductor device according to the embodiment
  • FIG. 3 is a manufacturing process flow chart showing an example of assembling steps after resin molding in assembling
  • thermosetting tape 19 can be done on the first pickup stage 26 while performing the pickup process on the second pickup stage 27 , whereby it is possible to shorten the heating time and improve the efficiency of the pickup process.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
US11/833,606 2006-09-22 2007-08-03 Manufacturing method of a semiconductor device having a package dicing Expired - Fee Related US8105878B2 (en)

Applications Claiming Priority (2)

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JP2006-257690 2006-09-22
JP2006257690A JP5054954B2 (ja) 2006-09-22 2006-09-22 半導体装置の製造方法

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US8105878B2 true US8105878B2 (en) 2012-01-31

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US20090311849A1 (en) * 2008-06-17 2009-12-17 International Business Machines Corporation Methods of separating integrated circuit chips fabricated on a wafer
JP2010092931A (ja) * 2008-10-03 2010-04-22 Toshiba Corp 半導体装置の製造方法及び半導体装置の製造装置
JP7345328B2 (ja) * 2019-09-13 2023-09-15 株式会社ディスコ 被加工物の加工方法
JP7612428B2 (ja) * 2020-03-23 2025-01-14 ファスフォードテクノロジ株式会社 ダイボンディング装置、剥離治具および半導体装置の製造方法
JP7558871B2 (ja) * 2021-03-30 2024-10-01 東レエンジニアリング株式会社 チップ搬送装置およびこれを用いた実装装置ならびに実装方法

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