US7829378B2 - Method of manufacturing electronic device, substrate and semiconductor device - Google Patents

Method of manufacturing electronic device, substrate and semiconductor device Download PDF

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US7829378B2
US7829378B2 US12/044,397 US4439708A US7829378B2 US 7829378 B2 US7829378 B2 US 7829378B2 US 4439708 A US4439708 A US 4439708A US 7829378 B2 US7829378 B2 US 7829378B2
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conductive pattern
bump
projection
insulating layer
substrate
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US20080230897A1 (en
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Yoshihiro Machida
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
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    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H—ELECTRICITY
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    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0231—Manufacturing methods of the redistribution layers
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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    • H01L2924/01029—Copper [Cu]
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Definitions

  • the present application claims priority from JP 2007-072706 filed on Mar. 20, 2007.
  • the present invention relates to a method of manufacturing an electronic device, and a substrate and a semiconductor device, and more particularly to a method of manufacturing an electronic device having a structure in which a substrate body and a conductive pattern formed thereon through an insulating layer are connected to each other by using a bump, and a substrate and a semiconductor device.
  • the chip size package has a structure in which a rewiring (a wiring for packaging) is formed through a passivation layer (a protecting layer) on a device forming surface of a semiconductor chip obtained by dicing a wafer to be a semiconductor substrate.
  • a plurality of electrodes is first formed on a semiconductor chip region of a semiconductor wafer and a bump is formed on each of the electrodes.
  • the bump is formed by a bonding wire using a bonding device.
  • a bonding wire extended from a capillary is first bonded to an electrode pad and the capillary is subsequently lifted while the bonding wire is reeled out, and the bonding wire thus reeled out is then cut to form a bump.
  • the bump formed by the bonding wire has a variation in a height from a surface (the electrode pad) on which the bump is formed and it is hard to form a rewiring to be connected to the bump in this state.
  • a processing for applying a load to each formed bump in a lump to substantially flatten an upper part of the bump.
  • a semiconductor wafer having the bump formed thereon is covered with a resin, and furthermore, the resin is polished to expose an upper surface of the bump from the resin. Then, a solder ball is formed on each bump exposed from the resin, and thereafter, the semiconductor wafer is subjected to a dividing processing (a dicing processing) every semiconductor chip region so that a chip size package is manufactured.
  • a dividing processing a dicing processing
  • an insulating layer is formed to cover the bump. Therefore, there is required a polishing step of polishing the insulating layer to expose the bump.
  • a processing (a so-called desmear processing) for roughening a surface of the insulating layer is required when a nonelectrolytic plating method is used, for example. For this reason, a processing for forming a plated layer is complicated. As a result, a manufacturing cost of a semiconductor device is increased.
  • a conductive layer by a sputtering method or a CVD method. Since the methods require an expensive film forming apparatus having a vacuum treating container, however, the manufacturing cost is increased. For this reason, they are not practical.
  • the invention features that the following means is taken.
  • an electronic device including:
  • the substrate body is a semiconductor substrate.
  • the machining executed at the fourth step is a grinding processing.
  • a cutting position of a grinding stone to be used in the grinding processing is set to be higher than a non-opposing position of the conductive layer to the projection and to be lower than an opposing position of the conductive layer to the projection.
  • the bump is formed by a bonding wire at the first step.
  • a substrate including:
  • a tip surface of the projection is on the level with an upper surface of the conductive layer.
  • a semiconductor device including:
  • a tip surface of the projection is on the level with an upper surface of the conductive layer.
  • the conductive layer is formed on the upper surface of the insulating layer and the upper part of the exposed portion of the projection, and the protruded portion opposed to the projection is removed by the machining to expose the projection from the conductive layer. Therefore, the height of each projection from the substrate body is uniform and is on the level with the upper surface of the conductive layer. Consequently, a leveling processing required conventionally is unnecessary and a polishing step of exposing the projection of the bump from the insulating layer is also unnecessary. Thus, a manufacturing process can be simplified and a manufacturing cost can be reduced.
  • FIG. 1A is a sectional view showing a semiconductor device according to an example of the invention.
  • FIG. 1B is a sectional view showing the enlarged vicinity of a bump in FIG. 1A ,
  • FIG. 2 is a sectional view showing a circuit board according to an example of the invention
  • FIG. 3A is a sectional view (No. 1) for explaining a method of manufacturing a semiconductor device according to an example of the invention
  • FIG. 3B is a sectional view (No. 2) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 3C is a sectional view (No. 3) for explaining the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 3D is a sectional view (No. 4) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 3E is a sectional view (No. 5) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 3F is a sectional view (No. 6) for explaining the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 3G is a sectional view (No. 7) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 3H is a sectional view (No. 8) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 3I is a sectional view (No. 9) for explaining the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 3J is a sectional view (No. 10) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 3K is a sectional view (No. 11) for explaining the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 3L is a sectional view (No. 12) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 3M is a sectional view (No. 13) for explaining the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 4A is a sectional view (No. 14) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 4B is a sectional view (No. 15) for explaining the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 4C is a sectional view (No. 16) for explaining the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 4D is a sectional view (No. 17) for explaining the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 4E is a sectional view (No. 18) for explaining the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 5 is a sectional view (No. 1) for explaining a variant of the method of manufacturing a semiconductor device according to the example of the invention.
  • FIG. 6 is a sectional view (No. 2) for explaining a variant of the method of manufacturing a semiconductor device according to the example of the invention
  • FIG. 1A is a sectional view showing a semiconductor device 100 according to an example of the invention.
  • the semiconductor device 100 according to the example has a schematic structure in which an insulating layer 105 and a conductive pattern 106 are provided on a protecting layer (a passivation layer) 102 of a semiconductor chip 101 on which an electrode pad 103 is formed.
  • a protecting layer a passivation layer
  • the conductive pattern 106 is referred to as a so-called rewiring in some cases, and is used in packaging for the semiconductor chip 101 .
  • the insulating layer 105 is constituted by an epoxy based resin, for example.
  • the conductive pattern 106 has such a structure that a first conductive pattern 107 and a second conductive pattern 108 which are formed of Cu are laminated, for example.
  • the conductive pattern 106 formed on the insulating layer 105 is connected to a projection (which will be described below) of a bump 104 formed of Au, for example, and provided on the electrode pad 103 . More specifically, the conductive pattern 106 is connected to an electronic circuit of the semiconductor chip 101 through the bump 104 .
  • the bump 104 is formed by a bonding wire using a wire bonding device, for example.
  • solder bump 110 is formed on the conductive pattern 106 . Furthermore, a solder resist layer (an insulating layer) 109 is formed to cover the insulating layer 105 and a part of the conductive pattern 106 around the solder bump 110 .
  • FIG. 1B shows an A portion (the vicinity of the bump 104 ) of the semiconductor device 100 which is enlarged.
  • the bump 104 is constituted by a bump body 104 A to be connected (bonded) to the electrode pad 103 and a projection 104 B which is protruded from the bump body 104 A.
  • the bump 104 is formed by a bonding wire constituted by Au, for example, using the wire bonding device.
  • the wire bonding device continuously bonds the bonding wire to the electrode pad 103 and cuts the bonding wire after the bonding, thereby forming the bump body 104 A to be bonded to the electrode pad 103 and the projection 104 B which is protruded from the bump body 104 A.
  • the projection 104 B is formed to include a flat tip portion 104 D formed on a tip of the projection 104 B and a connecting portion 104 C provided between the tip portion 104 D and the bump body 104 A.
  • the semiconductor device 100 according to the example has a structure in which the projection 104 B is inserted in the conductive pattern 106 and features that the tip portion 104 D of the projection 104 B which is inserted is on the level (the same plane) with an upper surface 107 B of the first conductive pattern 107 .
  • the first conductive pattern 107 and the second conductive pattern 108 formed on the tip portion 104 D can be a uniform and flat conductive layer having no step. Consequently, an electrical characteristic of the second conductive pattern 108 can be stabilized and a height of the solder bump 110 to be formed thereon can be made uniform. Moreover, the tip portion 104 D of the projection 104 B is on the level (the same surface) with the upper surface 107 B of the first conductive pattern 107 so that a fine wiring can be obtained.
  • FIG. 2 shows a circuit board 120 according to an example of the invention.
  • structures corresponding to the structures shown in FIGS. 1A and 1B have the same reference numerals and description thereof will be partially omitted.
  • the circuit board 120 has a schematic structure in which an insulating layer 105 and a conductive pattern 106 are laminated on a glass board 121 on which a surface electrode 122 is formed. Moreover, a bump 104 is formed in a predetermined position on the surface electrode 122 formed on an upper surface of the glass board 121 .
  • the insulating layer 105 is formed by an epoxy based resin, for example, and the conductive pattern 106 has such a structure that a first conductive pattern 107 formed of Cu and a second conductive pattern 108 are laminated.
  • the conductive pattern 106 formed on the insulating layer 105 is connected to a tip portion 104 D of the bump 104 formed on the surface electrode 122 . More specifically, the conductive pattern 106 is connected to the surface electrode 122 through the bump 104 . Moreover, a solder resist layer (an insulating layer) 109 is formed on a top of each of the insulating layer 105 and the conductive pattern 106 , and a predetermined part thereof is opened so that the conductive pattern 106 is exposed and an external electrode 123 is formed.
  • the tip portion 104 D of a projection 104 B and an upper surface 107 B of the first conductive pattern 107 are constituted to be on the level (the same surface) with each other.
  • the second conductive pattern 108 formed on the first conductive pattern 107 and the tip portion 104 D can be set to be a smooth pattern having no concavo-convex portion. Thus, an electrical characteristic can be stabilized.
  • first conductive pattern 107 and the second conductive pattern 108 are formed of Cu in each of the examples, it is also possible to constitute them by materials other than Cu. Moreover, the first conductive pattern 107 and the second conductive pattern 108 may be formed by different metallic materials (alloy materials) and the conductive pattern 106 may have a laminating structure of the different materials.
  • FIGS. 3A to 3M and FIGS. 4A to 4D Next, a method of manufacturing an electronic device according to an example of the invention will be described with reference to FIGS. 3A to 3M and FIGS. 4A to 4D .
  • FIG. 1A By taking, as an example of the electronic device, the semiconductor device 100 shown in FIG. 1A , description will be given to a method of manufacturing the semiconductor device 100 .
  • FIGS. 3A to 3M and FIGS. 4A to 4D to be used in the following description moreover, corresponding structures to the structures shown in FIGS. 1A , 1 B and 2 used in the description have the same reference numerals and a part of the description will be omitted.
  • a semiconductor substrate 101 A (which is a wafer and will be hereinafter referred to as a substrate 101 A) having a plurality of regions 101 a provided with an electronic circuit (like a grid, for example) is first manufactured by using a well-known method.
  • the region 101 a corresponds to a semiconductor chip 101 .
  • An electrode pad 103 is formed on a device forming surface 101 b on which an electronic circuit is formed in the region 101 a .
  • a protecting layer (a passivation layer) 102 formed of SiN (Si 3 N 4 ) is provided in a portion other than the electrode pad 103 in the device forming surface 101 b . Consequently, the device forming surface 101 b can be protected.
  • FIG. 3B shows the enlarged region 101 a of the substrate 101 A illustrated in FIG. 3A .
  • the enlarged region 101 a is shown for simplicity of the illustration and description.
  • the bump 104 is formed on the electrode pad 103 by using a wire bonding device, for example.
  • the bump 104 is formed by a bonding wire constituted by Au.
  • FIG. 4A shows a C portion (the bump 104 ) of FIG. 3C which is enlarged.
  • the wire bonding device continuously bonds the bonding wire to the electrode pad 103 and cuts the bonding wire thus bonded, thereby forming a bump body 104 A to be bonded to the electrode pad 103 and the projection 104 B which is protruded from the bump body 104 A.
  • the insulating layer 105 formed by an epoxy based resin material, for example, is provided on the substrate 101 A (the protecting layer 102 ).
  • the insulating layer 105 is formed by lamination (pasting) or application, for example.
  • the insulating layer 105 is formed in such a manner that the projection 104 B of the bump 104 is exposed from an upper surface of the insulating layer 105 .
  • the insulating layer 105 a soft resin material to which a hardness regulating material such as a filler referred to as NCF is rarely added.
  • NCF a hardness regulating material
  • a thickness of the insulating layer 105 is also selected in such a manner that the projection 104 B is reliably protruded from the upper surface of the insulating layer 105 in the formation of the insulating layer 105 .
  • the insulating layer 105 is not restricted to the material but can be formed by using various insulating materials (resin materials).
  • insulating materials resin materials
  • a conductive layer 107 A formed by a thin copper foil is stuck onto the insulating layer 105 , for example.
  • the conductive layer 107 A is stuck to the insulating layer 105 in a state in which a support layer 111 formed of Cu is laminated thereon, for example, (a state in which the conductive layer 107 A is supported by the support layer 111 ).
  • FIG. 4B shows an E portion (the vicinity of the bump 104 ) of FIG. 3E which is enlarged.
  • the conductive layer 107 A is pushed up by the bump 104 and is thus brought into a swelling state toward the support layer 111 side.
  • FIG. 3F shows a state in which the support layer 111 is removed.
  • FIG. 4C shows an F portion (the vicinity of the bump 104 ) of FIG. 3F which is enlarged.
  • a flat surface is provided in a position of the conductive layer 107 A which is not opposed to the bump 104 (a non-opposing position which is not projective), and the conductive layer 107 A is pushed up by the bump 104 and is thus swollen as described above in a position opposed to the bump 104 (an opposing position which is projective).
  • an arrow H 1 shown in FIG. 4C indicates a height from the upper surface of the substrate 101 A to the upper surface of the conductive layer 107 A in the non-opposing position.
  • an arrow H 2 shown in FIG. 4C indicates a height from the upper surface of the substrate 101 A to the tip portion 104 D of the bump 104 .
  • the heights H 1 and H 2 are set to be H 1 ⁇ H 2 .
  • FIG. 3F shows a state in which the substrate 101 A is attached to a grinding apparatus. In the attaching state, the substrate 101 A is sucked by an adsorbing table which is not shown and is thus fixed. Subsequently, a grinding roll 112 is used and is moved in a direction of an arrow in the drawing so that the grinding processing is carried out.
  • the grinding roll 112 is obtained by baking and hardening an abrasive grain. By rotating and moving the grinding roll 112 , it is possible to carry out the grinding processing over a surface of a workpiece.
  • a height (represented by H) from the upper surface of the substrate 101 A in a position in which the grinding operation of the grinding roll 112 is carried out (which is referred to as a grinding position) is set to be equal to or slightly greater than the height H 1 (which will be hereinafter referred to as an upper surface height H 1 ) from the upper surface of the substrate 101 A to the upper surface 107 B in the non-opposing position of the conductive layer 107 A and is set to be smaller than the height H 2 (which will be hereinafter referred to as a projection height H 2 ) from the upper surface of the substrate 101 A to the tip portion 104 D of the bump 104 (H 1 ⁇ H ⁇ H 2 ).
  • the grinding position of the grinding roll 112 is set and the grinding roll 112 is moved from a position shown in FIG. 3F to a position shown in FIG. 3G . Consequently, the portion of the conductive layer 107 A which is opposed to the bump 104 (the projection 104 B) and is thus swollen is ground by the grinding roll 112 .
  • the grinding position H is higher than the height H 1 of the upper surface and is lower than the height H 2 of the projection (H 1 ⁇ H ⁇ H 2 ) as described above. Therefore, the grinding processing is rarely carried out over the upper surface 107 B of the conductive layer 107 A.
  • the conductive layer 107 A and the projection 104 B are ground (removed) by the grinding roll 112 in the opposing position in which the conductive layer 107 A is swollen from the upper surface 107 B.
  • FIG. 3G shows a state in which the grinding processing of the grinding roll 112 is carried out as described above.
  • FIG. 4D shows a G portion (the vicinity of the bump 104 ) of FIG. 3G which is enlarged.
  • the grinding processing is carried out by the grinding roll 112 on the condition described above.
  • the conductive layer 107 A and the tip portion 104 D of the bump 104 in the opposing position are removed through the grinding processing. Consequently, the tip portion 104 D of the bump 104 is exposed from the conductive layer 107 A, and the exposed tip portion 104 D and the upper surface 107 B of the conductive layer 107 A have no concavo-convex portion and are on the level with each other.
  • a plurality of bumps 104 is formed on the substrate 101 A. All of the bumps 104 are subjected to the grinding processing by the grinding roll 112 having the grinding position H to be constant. Consequently, all of the projection heights H 2 of the tip portions 104 D of the respective bumps 104 (which are the heights from the upper surface of the substrate 101 A) are equal to each other. In the example, thus, it is possible to cause the projection heights H 2 of all of the bumps 104 to be equal to each other without executing a leveling processing which has conventionally been carried out.
  • the bump 104 formed by using a wire bonding method has a high productivity and a comparatively great variation in the height. Also in the bump 104 , it is possible to easily cause the projection heights H 2 of the bumps 104 to be equal to each other at a simple step by using the manufacturing method according to the example. Thus, it is possible to enhance the reliability of the semiconductor device 100 to be manufactured.
  • the conductive layer 107 A is used as a feeding layer (a seed layer) at an electrolytic plating step which will be described below.
  • the conductive pattern 106 to be connected to the bump 104 is formed through electrolytic plating using the conductive layer 107 A as the feeding layer (the seed layer).
  • a method of forming the conductive pattern 106 includes a so-called subtractive process and a so-called semiadditive process, for instance.
  • a so-called subtractive process and a so-called semiadditive process, for instance.
  • description will be given to an example in which the subtractive process is used.
  • a conductive layer 108 A formed of Cu is laminated on the conductive layer 107 A and the tip portion 104 D through the electrolytic plating using the conductive layer 107 A as the feeding layer.
  • the tip potion 104 D is on the level with the upper surface 107 B of the conductive layer 107 A. Therefore, the conductive layer 108 A thus formed is a flat and excellent layer having no concavo-convex portion.
  • FIG. 4E shows an H portion (the vicinity of the bump 104 ) of FIG. 3H which is enlarged.
  • a mask pattern R 1 having an opening portion Ra is formed on the conductive layer 108 A.
  • the mask pattern R 1 can be provided by forming a resist layer through application or sticking of a film and patterning the resist layer using a photolithography.
  • the conductive layers 107 A and 108 A are subjected to pattern etching using the mask pattern R 1 as a mask. Consequently, the first conductive pattern 107 and the second conductive pattern 108 are laminated and the conductive pattern 106 connected to the bump 104 is formed.
  • first conductive pattern 107 has a thickness of approximately 2 to 3 ⁇ m and the second conductive pattern 108 has a thickness of approximately 30 to 40 ⁇ m, for example, the numeric values are only illustrative and the invention is not restricted to the numeric values.
  • the conductive layer 107 A is used as the feeding layer so that the electrolytic plating can easily be used.
  • the feeding layer the seed layer
  • a processing for roughening the surface of the insulating layer a so-called desmear processing
  • a processing for forming a plated layer is complicated.
  • an expensive film forming apparatus having a vacuum treating container is required. Thus, a manufacturing cost is increased.
  • the desmear processing and the sputtering processing in a vacuum chamber are not required and the feeding layer (the conductive layer 107 A) can easily be formed by a simple method. According to the method, therefore, the semiconductor device can simply be manufactured so that the manufacturing cost can be reduced.
  • a surface of the conductive pattern 106 (Cu) is subjected to a roughening processing if necessary, and the solder resist layer (an insulating layer) 109 having an opening portion 109 A is thereafter formed on the insulating layer 105 . A part of the conductive pattern 106 is exposed from the opening portion 109 A.
  • a back face of the substrate 101 A is ground and the substrate 101 A is caused to have a predetermined thickness if necessary.
  • a solder bump 110 is formed on the conductive pattern 106 exposed from the opening portion 109 A if necessary. Furthermore, the substrate 101 A is subjected to dicing to divide the semiconductor chip into individual pieces. Consequently, it is possible to manufacture the semiconductor device 100 shown in FIG. 1A .
  • the conductive pattern 106 is formed by the subtractive process in the manufacturing method
  • the conductive pattern 106 may be formed by using the semiadditive process. In this case, for example, it is preferable that the steps shown in FIGS. 3A to 3G should be executed in the manufacturing method and steps which will be described below should be then executed in place of the steps shown in FIGS. 3H to 3J .
  • a mask pattern R 2 having an opening portion Rb is formed on the conductive layer 107 A.
  • the mask pattern R 2 can be provided by forming a resist layer through application or sticking of a film and patterning the resist layer using the photolithography.
  • the electrolytic plating using the conductive layer 107 A as the feeding layer (the seed layer) is executed to form a second conductive pattern on the conductive layer 107 A exposed from the opening portion Rb.
  • the mask pattern R 2 is peeled and the excessive feeding layer 107 A which is exposed by peeling the mask pattern R 2 is further removed by etching. Consequently, it is possible to form the conductive pattern 106 shown in FIG. 3J .
  • the insulating layer 105 is formed on the substrate 101 A and the conductive layer 107 A is then stuck onto the insulating layer 105 at the steps shown in FIGS. 3D and 3E in the manufacturing method, moreover, a lamination in which the insulating layer 105 and the conductive layer 107 A are previously provided may be stuck to the substrate 101 A.
  • the insulating layer 105 and the conductive layer 107 A which are laminated on the support layer 111 may be stuck to the substrate 101 A.

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JP5064158B2 (ja) * 2007-09-18 2012-10-31 新光電気工業株式会社 半導体装置とその製造方法
TWI394249B (zh) * 2008-11-04 2013-04-21 Unimicron Technology Corp 封裝基板結構及其製法
US8946891B1 (en) 2012-09-04 2015-02-03 Amkor Technology, Inc. Mushroom shaped bump on repassivation
KR101974191B1 (ko) * 2012-11-29 2019-04-30 에스케이하이닉스 주식회사 반도체 장치 및 그 형성방법
CN104425431B (zh) * 2013-09-03 2018-12-21 日月光半导体制造股份有限公司 基板结构、封装结构及其制造方法
CN104617001B (zh) * 2014-12-30 2017-08-11 通富微电子股份有限公司 半导体再布线封装工艺
US10636745B2 (en) * 2017-09-27 2020-04-28 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US10332757B2 (en) * 2017-11-28 2019-06-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package having a multi-portion connection element

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TW200839989A (en) 2008-10-01
CN101271853A (zh) 2008-09-24

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