US7701783B2 - Semiconductor storage device - Google Patents
Semiconductor storage device Download PDFInfo
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- US7701783B2 US7701783B2 US12/209,748 US20974808A US7701783B2 US 7701783 B2 US7701783 B2 US 7701783B2 US 20974808 A US20974808 A US 20974808A US 7701783 B2 US7701783 B2 US 7701783B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Definitions
- the present invention relates to a semiconductor storage device, such as a static random access memory, and more particularly, to a technique of controlling the voltage of a bit line.
- data is written into a memory cell by causing the potential of either one of a pair of bit lines precharged to the H level to go from the H level to the L level.
- bit line potential is controlled so that it is lower than 0 V, i.e., a negative potential
- a transistor to which only a potential difference ranging from 0 V to a power supply voltage VDD is conventionally applied suffers from application of a potential difference of the VDD level or higher. Therefore, electrical stress to the transistor is larger than that in the conventional art, so that the reliability of the element is more significantly deteriorated.
- the potential of a word line of a memory cell to which data write is not performed is the L level (0 V), however, if the potential of a bit line decreases to a potential that exceeds the threshold voltage of an access transistor included in the memory cell, the access transistor is turned ON, so that data held by the memory cell is destroyed (inversion of data).
- an object of the present invention is to provide a semiconductor storage device in which the data write characteristic of a memory cell at a low power supply voltage can be improved and a deterioration in reliability of each element can be suppressed, and which has stable write performance.
- a semiconductor storage device comprises a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at intersections of the word lines and the bit lines, a precharge circuit connected to the bit lines, and a write circuit connected to the bit lines.
- the write circuit includes a column selection circuit controlled by a write control signal, a first control circuit for controlling a potential of a selected bit line so that the potential of the selected bit line is a first potential, a second control circuit for controlling the potential of the selected bit line so that the potential of the selected bit line is a second potential that is lower than the first potential, and a clamp circuit for clamping the second potential.
- the clamp circuit may control a voltage applied to each element included in the memory cells, the precharge circuit and the write circuit so that the voltage is a third potential that is higher than the second potential.
- the clamp circuit may be connected to an output of the second control circuit, and a reduction rate of an L level of the output of the second control circuit may decrease with an increase in a power supply voltage.
- the clamp circuit may include one or more diode characteristic elements.
- the clamp circuit may include a transistor connected between the output of the second control circuit and a power supply terminal, and an output potential of the second control circuit may be controlled by controlling a gate voltage of the transistor.
- one or more switches may be provided and connected in parallel with elements included in the clamp circuit, and an output potential of the second control circuit may be adjusted by a combination of the switches.
- the clamp circuit may be disabled when it is not during data write to the memory cells.
- the clamp circuit may be connected to an input of the second control circuit, and a reduction rate of an H level of the input of the second control circuit may increase with an increase in a power supply voltage.
- the clamp circuit may include a transistor connected between the input of the second control circuit and a power supply terminal, and an input potential of the second control circuit may be controlled by controlling a gate voltage of the transistor.
- one or more switches may be provided and connected in parallel with elements included in the clamp circuit, and an input potential of the second control circuit may be adjusted by a combination of the switches.
- a semiconductor storage device comprises a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at intersections of the word lines and the bit lines, a precharge circuit connected to the bit lines, and a write circuit connected to the bit lines.
- the write circuit includes a column selection circuit controlled by a write control signal, a first control circuit for controlling a potential of a selected bit line so that the potential of the selected bit line is a first potential, and a second control circuit for controlling the potential of the selected bit line so that the potential of the selected bit line is a second potential that is lower than the first potential.
- the second control circuit is driven before a potential of the selected bit line goes to the first potential.
- the second control circuit may be driven at a more higher potential of the bit line than the first potential with an increase in the power supply voltage.
- a semiconductor storage device comprises a plurality of word lines, a plurality of bit lines, a plurality of memory cells provided at intersections of the word lines and the bit lines, a precharge circuit connected to the bit lines, and a write circuit connected to the bit lines.
- the write circuit includes a column selection circuit controlled by a write control signal, a first control circuit for controlling a potential of a selected bit line so that the potential of the selected bit line is a first potential, and a second control circuit for controlling the potential of the selected bit line so that the potential of the selected bit line is a second potential that is lower than the first potential.
- At least one of a potential applied to the memory cells, a potential applied to the column selection circuit, and a potential output from the precharge circuit is controlled so that the at least one potential is a predetermined potential.
- a potential of a word line applied to the memory cells may be lower than a power supply voltage.
- a memory cell power supply voltage applied to the memory cells may be lower than a power supply voltage.
- a potential of a write control signal applied to the column selection circuit may be lower than a power supply voltage.
- an output potential from the precharge circuit before data write to the memory cells may be lower than a power supply voltage.
- the precharge circuit includes transistors, and of the transistors, the polarity of a transistor connected to the bit line may be of N channel type.
- a data write characteristic to a memory cell with a low power supply voltage can be improved and a deterioration in reliability of each element can be suppressed, and the semiconductor storage device can have stable write performance and low power consumption.
- FIG. 1 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 1 of the present invention.
- FIG. 2 is a diagram showing a specific configuration of a clamp circuit included in the semiconductor storage device of Embodiment 1.
- FIG. 3 is a diagram showing another specific configuration of a clamp circuit included in the semiconductor storage device of Embodiment 1.
- FIG. 4 is a diagram showing still another specific configuration of a clamp circuit included in the semiconductor storage device of Embodiment 1.
- FIG. 5 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 2 of the present invention.
- FIG. 6 is a diagram showing a specific configuration of a clamp circuit included in the semiconductor storage device of Embodiment 2.
- FIG. 7 is a diagram showing another specific configuration of a clamp circuit included in the semiconductor storage device of Embodiment 2.
- FIG. 8 is a diagram showing still another specific configuration of a clamp circuit included in the semiconductor storage device of Embodiment 2.
- FIG. 9 is a timing chart showing an operation of a conventional semiconductor storage device.
- FIG. 10 is a timing chart showing an operation of a semiconductor storage device according to Embodiment 3 of the present invention.
- FIG. 11 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 4 of the present invention.
- FIG. 12 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 5 of the present invention.
- FIG. 13 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 6 of the present invention.
- FIG. 14 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 7 of the present invention.
- FIG. 1 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 1 of the present invention.
- the semiconductor storage device of FIG. 1 comprises memory cells 100 each including drive transistors QN 1 and QN 2 , access transistors QN 3 and QN 4 , and load transistors QP 1 and QP 2 , precharge circuits 101 each including P-type MOS transistors QP 3 and QP 4 , column selection circuits 102 each including N-type MOS transistors QN 5 and QN 6 , a clamp circuit 103 A including P-type MOS transistors QP 5 and QP 6 , a capacitance element CAP, and an N-type MOS transistor QN 7 .
- the semiconductor storage device of FIG. 1 further comprises word lines WL 1 and WL 2 , bit lines BL 1 and BL 2 and /BL 1 and /BL 2 , a precharge control signal PCG, write control signals WT 1 and WT 2 and /WT 1 and /WT 2 , a capacitance element control signal CIN, a capacitance element output node COUT, and a power supply voltage VDD.
- the load transistor QP 1 and the drive transistor QN 1 , and the load transistor QP 2 and the drive transistor QN 2 form respective inverters.
- the input and output terminals of these inverters are connected so as to form a flip-flop.
- the flip-flop stores and holds data.
- the gate terminals of the access transistors QN 3 and QN 4 are connected to the word line WL 1 (WL 2 ), and the drain terminals thereof are connected to the bit lines BL 1 and /BL 1 (BL 2 and /BL 2 ), respectively.
- the source terminals of the access transistors QN 3 and QN 4 are connected to the input and output terminals of the inverters.
- Data is written into the memory cell 100 by causing the potential of either one of the bit lines BL 1 and /BL 1 (BL 2 and /BL 2 ) precharged to the H level to go from the H level to the L level while the selected word line WL 1 (WL 2 ) is caused to go from the L level to the H level (activated state).
- the P-type MOS transistors QP 3 and QP 4 are connected between the power supply voltage VDD and the bit lines BL 1 and /BL 1 (BL 2 and /BL 2 ), and the precharge control signal PCG is connected to the gate terminals thereof.
- the precharge control signal PCG is caused to go to the L level so that the P-type MOS transistors QP 3 and QP 4 are turned ON to precharge the bit lines BL 1 and /BL 1 (BL 2 and /BL 2 ) to the H level.
- the precharge control signal PCG is caused to go to the H level so that the P-type MOS transistors QP 3 and QP 4 are turned OFF, i.e., do not have an influence on the bit lines BL 1 and /BL 1 (BL 2 and /BL 2 ).
- the N-type MOS transistors QN 5 and QN 6 are connected between the bit lines BL 1 and /BL 1 (BL 2 and /BL 2 ) and the capacitance element output node COUT, respectively, and the write control signals WT 1 and /WT 1 (WT 2 and /WT 2 ) are connected to the gate terminals of the N-type MOS transistors QN 5 and QN 6 , respectively.
- the column selection circuit 102 selects the bit lines BL 1 and /BL 1 (or BL 2 and /BL 2 ) and controls which data, H or L, is to be written to the memory cell 100 connected to the selected bit lines.
- the P-type MOS transistors QP 5 and QP 6 each having a gate terminal in diode connection are connected between the power supply voltage VDD and the capacitance element output node COUT.
- the capacitance element CAP is connected between the capacitance element output node COUT and the capacitance element control signal CIN.
- the N-type MOS transistor QN 7 is connected between the capacitance element output node COUT and a ground power supply voltage.
- the capacitance element control signal CIN is connected to the gate terminal of the N-type MOS transistor QN 7 .
- the word lines WL 1 and WL 2 are in the non-active state.
- all the word lines WL 1 and WL 2 are at the L level, and all the memory cells 100 that are controlled by these word lines are in the non-selected state (neither write nor read is performed).
- the precharge control signal PCG is at the L level, so that the precharge circuits 101 that are controlled by the precharge control signal PCG is in the active state and therefore all the bit lines BL 1 , /BL 1 , BL 2 and /BL 2 are precharged to the H level.
- all the write control signals WT 1 , /WT 1 , WT 2 and /WT 2 are at the L level, so that all the column selection circuits 102 that are controlled by these write control signals are in the non-active state.
- the capacitance element control signal CIN is at the H level, so that the N-type MOS transistor QN 7 is turned ON to discharge the capacitance element output node COUT to the L level.
- the two P-type MOS transistors QP 5 and QP 6 each having a gate terminal in diode connection are connected in series between the power supply voltage VDD and the capacitance element output node COUT.
- the threshold voltage of the P-type MOS transistors QP 5 and QP 6 is ⁇ 0.6 V and the potential of the capacitance element output node COUT is 0 V
- the clamp circuit 103 A is in the non-active state and therefore does not have an influence on the capacitance element output node COUT.
- the clamp circuit 103 A If the power supply voltage VDD becomes higher than 1.2 V, the clamp circuit 103 A is activated, so that electric charges flow into the capacitance element output node COUT. In this case, the amount of electric charges flowing into the capacitance element output node COUT increases with an increase in the power supply voltage VDD.
- the clamp circuit 103 A has a characteristic similar to that of a diode element.
- the precharge control signal PCG goes from the L level to the H level, so that all the precharge circuits 101 that are controlled by the precharge control signal PCG go to the non-active state. For example, the word line WL 1 is selected and goes to the H level.
- the write control signal WT 1 is selected and goes to the H level, so that the N-type MOS transistor QN 5 in the column selection circuit 102 connected to the bit line BL 1 is turned ON and therefore the bit line BL 1 and the capacitance element output node COUT are connected to each other via the N-type MOS transistor QN 5 .
- the capacitance element control signal CIN goes from the H level to the L level. Since the capacitance element control signal CIN goes to the L level, the N-type MOS transistor QN 7 is turned OFF.
- the capacitance of the capacitance element CAP is Cc
- the capacitance element control signal CIN goes from the H level (VDD) to the L level (0 V)
- an amount of electric charges corresponding to Cc ⁇ VDD are extracted from electric charges in all capacitances (capacitance C 1 ) of the bit line BL 1 , the capacitance element output node COUT and the storage node (in this case, the source terminal node of the access transistor QN 3 ) of the selected memory cell 100 .
- the potential of the bit line BL 1 or the like is changed from 0 V to ⁇ (Cc ⁇ VDD)/(Cc+C 1 ), i.e., a negative potential.
- the conductance of the access transistor in the selected memory cell 100 increases.
- a lower power supply voltage can be used to write data into the memory cell 100 .
- the absolute value of the negative potential generated by the operation of the capacitance element CAP increases with an increase in the power supply voltage VDD.
- a non-selected memory cell e.g., the memory cell 100 connected to the bit line BL 1 and the word line WL 2
- the potential of the word line WL 2 of the non-selected memory cell 100 to which data write is not performed is at the L level (0 V).
- the absolute value of the negative potential of the selected bit line BL 1 increases.
- FIG. 9 A timing chart showing an operation when the clamp circuit 103 A is not provided in the configuration of FIG. 1 (conventional semiconductor storage device) is shown in FIG. 9 .
- the clamp circuit 103 A When the power supply voltage VDD is lower than 1.0 V, the clamp circuit 103 A is in the non-active state and does not have an influence on the capacitance element output node COUT. When the power supply voltage VDD becomes higher than 1.0 V, the clamp circuit 103 A is activated, so that electric charges flow into the capacitance element output node COUT. Therefore, as the power supply voltage VDD increases after exceeding 1.0 V, the negative potential VBB is controlled so that it is higher than when the clamp circuit 103 A is not provided.
- the word line WL 1 goes from the H level to the L level, so that all the memory cells 100 go into the non-selected state.
- the write control signal WT 1 goes from the H level to the L level, so that all the column selection circuits 102 go into the non-active state.
- the capacitance element control signal CIN goes from the L level to the H level, so that the N-type MOS transistor QN 7 is turned ON and therefore the capacitance element output node COUT is discharged to the L level.
- the precharge control signal PCG goes from the H level to the L level, so that all the precharge circuits 101 go into the active state and therefore all the bit lines are precharged to the H level.
- a data write characteristic to the memory cell 100 can be improved as in the conventional art.
- the power supply voltage VDD is high, the potential of a selected bit line or the like during a data write operation to a memory cell 100 can be controlled so that it is higher than that in the conventional art. Therefore, electrical stress applied to elements connected to a selected bit line or the like can be reduced, thereby making it possible to suppress a deterioration in reliability. Also, it is possible to prevent destruction of data held by a non-selected memory cell connected to a selected bit line.
- the operation power supply voltage of the semiconductor storage device, the threshold voltage of a transistor in the semiconductor storage device, and the like vary depending on the operation power supply voltage specifications, process conditions and the like of the semiconductor storage device. It has been assumed in this embodiment that the threshold voltage of the P-type MOS transistors QP 5 and QP 6 included in the clamp circuit 103 A is ⁇ 0.6 V and the power supply voltage VDD at which operations are switched (border voltage) is 1.0 V.
- the clamp circuit 103 A may include only one P-type MOS transistor or a plurality of P-type MOS transistors connected in series (e.g., three P-type MOS transistors connected in series), for example.
- a P-type MOS transistor instead of a P-type MOS transistor, an N-type MOS transistor having a gate terminal in diode connection or a PN-junction diode may be used.
- the P-type MOS transistor, the N-type MOS transistor, the PN-junction diode, a resistance element, and the like may be used in combination. In other words, the configuration of the clamp circuit 103 A may be changed, depending on operation conditions required for the semiconductor storage device.
- FIG. 2 is a diagram showing another example of the clamp circuit 103 A of FIG. 1 .
- the clamp circuit 103 B of FIG. 2 includes fuse elements F 1 and F 2 connected in parallel with the P-type MOS transistors QP 5 and QP 6 of the clamp circuit 103 A of FIG. 1 .
- the border voltage at which operations are switched can be changed to any voltage, depending on operation conditions required for the semiconductor storage device, by cutting one of the fuse elements.
- FIG. 2 shows an example in which the fuse elements F 1 and F 2 are used as means for switching set voltages.
- the source terminal and the drain terminal of a transistor may be connected in parallel and the gate terminal of the transistor may be ON/OFF controlled, thereby achieving an operation and an effect similar to those when fuse elements are used.
- FIG. 3 is a diagram showing another example of the clamp circuit 103 A of FIG. 1 .
- another P-type MOS transistor QP 7 is connected in series between the P-type MOS transistor QP 6 included in the clamp circuit 103 A of FIG. 1 and the capacitance element output node COUT, and the gate terminal of the P-type MOS transistor QP 7 is connected to the capacitance element control signal CIN.
- the clamp circuit may be activated only during a write operation.
- the capacitance element control signal CIN is at the H level, so that the N-type MOS transistor QN 7 is turned ON and therefore the capacitance element output node COUT is discharged to the L level.
- the clamp circuit 103 A is in the non-active state when the power supply voltage VDD is low (lower than 1.2 V)
- the clamp circuit 103 A is activated when the power supply voltage VDD becomes high (exceeds 1.2 V), so that a stationary current flows from the clamp circuit 103 A via the N-Type MOS transistor QN 7 .
- FIG. 3 another P-type MOS transistor QP 7 is connected in series between the P-type MOS transistor QP 6 and the capacitance element output node COUT, so that when a word line is in the non-active state, the capacitance element control signal CIN is at the H level and therefore the P-type MOS transistor QP 7 can be turned OFF.
- the clamp circuit 103 C is activated only during a write operation, and is in the non-active state when it is not during a write operation, so that a stationary current that would otherwise flow when it is not during a write operation can be eliminated, resulting in lower power consumption.
- the configuration of FIG. 3 is applicable to the configuration of FIG. 2 .
- FIG. 4 is a diagram showing another example of the clamp circuit 103 A of FIG. 1 .
- a P-type MOS transistor QP 8 having a gate terminal in diode connection
- a P-type MOS transistor QP 9 having a gate terminal connected to the capacitance element control signal CIN
- an N-type MOS transistor QN 9 having a gate terminal connected to the power supply voltage VDD are connected in series between the power supply voltage VDD and a ground power supply voltage.
- An intersection of the drain terminal of the P-type MOS transistor QP 9 and the drain terminal of the N-type MOS transistor QN 9 is referred to as a gate control node VGN 1 .
- the gate control node VGN 1 is connected to the gate terminal of an N-type MOS transistor QN 8 connected between the capacitance element output node COUT and the ground power supply voltage.
- the capacitance element control signal CIN is at the H level, so that the P-type MOS transistor QP 9 is OFF and therefore the gate control node VGN 1 invariably outputs the L level by the N-type MOS transistor QN 9 whose gate terminal is at the power supply voltage VDD. Therefore, the N-type MOS transistor QN 8 that receives the gate control node VGN 1 at the gate terminal thereof is invariably OFF and therefore does not have an influence on the capacitance element output node COUT.
- the clamp circuit 103 D when the power supply voltage VDD is lower than 1.0 V, the clamp circuit 103 D is in the non-active state and does not have an influence on the capacitance element output node COUT.
- the clamp circuit 103 D When the power supply voltage VDD becomes higher than 1.0 V, the clamp circuit 103 D is activated, so that electric charges flow into the capacitance element output node COUT. Therefore, as the power supply voltage VDD increases after exceeding 1.0 V, the negative potential is controlled so that it is higher than when the clamp circuit 103 D is not provided.
- the configuration of the clamp circuit 103 D of FIG. 4 in which the voltage of the gate terminal of the transistor QN 8 connected between the capacitance element output node COUT and the ground power supply voltage is controlled, can also achieve an operation and an effect similar to those of FIG. 1 .
- the P-type MOS transistor QP 9 in the clamp circuit 103 D of FIG. 4 may not be provided in terms of an operation. However, when it is not during a write operation and the capacitance element control signal CIN is at the H level, the P-type MOS transistor QP 9 is turned OFF, so that a stationary current does not flow from the power supply voltage VDD via the N-type MOS transistor QN 9 to the ground power supply voltage, thereby making it possible to achieve lower power consumption.
- the N-type MOS transistor QN 8 is connected between the capacitance element output node COUT and a ground power supply voltage.
- a P-type MOS transistor may be connected between the power supply voltage VDD and the capacitance element output node COUT and the voltage of the gate terminal of the P-type MOS transistor may be controlled. Also in this case, a similar effect is obtained.
- the operation power supply voltage of a semiconductor storage device, the threshold voltage of a transistor in a semiconductor storage device, and the like vary depending on the operation power supply voltage specifications, process conditions or the like of the semiconductor storage device.
- two or more P-type MOS transistors QP 8 each having a gate terminal in diode connection may be connected in series in the clamp circuit 103 D, or alternatively, instead of a P-type MOS transistor, an N-type MOS transistor having a gate terminal in diode connection or a PN-junction diode element may be used.
- a P-type MOS transistor, an N-type MOS transistor, a PN-junction diode, a resistance element and the like may be used in combination.
- the fuse elements F 1 and F 2 of FIG. 2 may be connected in parallel with a transistor, or alternatively, instead of these fuse elements, a transistor may be connected in parallel and the gate terminal of the transistor may be ON/OFF controlled.
- the configuration of the clamp circuit 103 D may be changed, depending on operation conditions required for the semiconductor storage device.
- FIG. 5 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 2 of the present invention.
- the semiconductor storage device of FIG. 5 comprises memory cells 100 each including drive transistors QN 1 and QN 2 , access transistors QN 3 and QN 4 , and load transistors QP 1 and QP 2 , precharge circuits 101 each including P-type MOS transistors QP 3 and QP 4 , column selection circuits 102 each including N-type MOS transistors QN 5 and QN 6 , a capacitance element CAP, an N-type MOS transistor QN 7 , an inverter 104 including a P-type MOS transistor QP 10 and an N-type transistor QN 10 , and a clamp circuit 105 A including N-type MOS transistors QN 11 and QN 12 .
- the semiconductor storage device of FIG. 5 further comprises word lines WL 1 and WL 2 , bit lines BL 1 and BL 2 and /BL 1 and /BL 2 , a precharge control signal PCG, write control signals WT 1 and WT 2 and /WT 1 and /WT 2 , a capacitance element control signal /CIN (an inversion of the capacitance element control signal CIN of Embodiment 1 of the present invention), a capacitance element output node COUT, a capacitance element input node CIN 2 , and a power supply voltage VDD.
- word lines WL 1 and WL 2 , bit lines BL 1 and BL 2 and /BL 1 and /BL 2 , a precharge control signal PCG, write control signals WT 1 and WT 2 and /WT 1 and /WT 2 , a capacitance element control signal /CIN (an inversion of the capacitance element control signal CIN of Embodiment 1 of the present invention), a capac
- the memory cell 100 , the precharge circuit 101 , the column selection circuit 102 , the capacitance element CAP, and the N-type MOS transistor QN 7 are the same as those of Embodiment 1 of the present invention and will not be described.
- the P-type MOS transistor QP 10 and the N-type MOS transistor QN 10 are connected in series between the power supply voltage VDD and a ground power supply voltage.
- the inverter 104 outputs an inversion of the capacitance element control signal /CIN to the capacitance element input node CIN 2 .
- the N-type MOS transistors QN 11 and QN 12 each having a gate terminal in diode connection are connected between the capacitance element input node CIN 2 and the ground power supply voltage.
- the word lines WL 1 and WL 2 are in the non-active state.
- all the word lines WL 1 and WL 2 are at the L level, and all the memory cells 100 that are controlled by these word lines are in the non-selected state (neither write nor read is performed).
- the precharge control signal PCG is at the L level, so that the precharge circuits 101 that are controlled by the precharge control signal PCG is in the active state and therefore all the bit lines BL 1 , /BL 1 , BL 2 and /BL 2 are precharged to the H level.
- all the write control signals WT 1 , /WT 1 , WT 2 and /WT 2 are at the L level, so that all the column selection circuits 102 that controlled by these write control signals are in the non-active state.
- the capacitance element control signal /CIN is at the L level, so that the capacitance element input node CIN 2 is caused to go to the H level by the inverter 104 and therefore the N-type MOS transistor QN 7 is turned ON to discharge the capacitance element output node COUT to the L level.
- the two N-type MOS transistors QN 11 and QN 12 having gate terminals in diode connection are connected in series between the capacitance element input node CIN 2 and the ground power supply voltage.
- the threshold voltage of the N-type MOS transistors QN 11 and QN 12 is 0.6 V
- the clamp circuit 105 A is in the non-active state and therefore does not have an influence on the capacitance element input node CIN 2 .
- the clamp circuit 105 A If the potential of the capacitance element input node CIN 2 becomes higher than 1.2 V, the clamp circuit 105 A is activated, so that electric charges of the capacitance element input node CIN 2 flow into the ground power supply voltage. In this case, the amount of electric charges flow into the ground power supply voltage increases with an increase in the power supply voltage VDD.
- the clamp circuit 105 A has a characteristic similar to that of a diode element.
- the precharge control signal PCG goes from the L level to the H level, so that all the precharge circuits 101 that are controlled by the precharge control signal PCG go to the non-active state. For example, the word line WL 1 is selected and goes to the H level.
- the write control signal WT 1 is selected and goes to the H level, so that the N-type MOS transistor QN 5 in the column selection circuit 102 connected to the bit line BL 1 is turned ON and therefore the bit line BL 1 and the capacitance element output node COUT are connected to each other via the N-type MOS transistor QN 5 .
- the capacitance element control signal /CIN goes from the L level to the H level. Since the capacitance element control signal /CIN goes to the H level, the capacitance element input node CIN 2 goes to the L level, so that the N-type MOS transistor QN 7 is turned OFF.
- the capacitance of the capacitance element CAP is Cc and the H-level voltage of the capacitance element input node CIN 2 is VCH
- the capacitance element input node CIN 2 goes from the H level (VCH) to the L level (0 V)
- an amount of electric charges corresponding to Cc ⁇ VCH are extracted from electric charges in all capacitances (capacitance C 1 ) of the bit line BL 1 , the capacitance element output node COUT and the storage node (in this case, the source terminal node of the access transistor QN 3 ) of the selected memory cell 100 .
- the potential of the bit line BL 1 or the like is changed from 0 V to ⁇ (Cc ⁇ VCH)/(Cc+C 1 ), i.e., a negative potential.
- the conductance of the access transistor in the selected memory cell 100 increases.
- a lower power supply voltage can be used to write data into the memory cell 100 .
- the absolute value of the negative potential generated by the operation of the capacitance element CAP increases with an increase in the power supply voltage VDD.
- the H-level potential VCH of the capacitance element input node CIN 2 is equal to the power supply voltage VDD.
- a non-selected memory cell e.g., the memory cell 100 connected to the bit line BL 1 and the word line WL 2
- the potential of the word line WL 2 of the non-selected memory cell 100 in which data write is not performed is at the L level (0 V).
- the absolute value of the negative potential of the selected bit line BL 1 increases.
- the potential of a selected bit line may be caused to be negative so that the conductance of the access transistor in the selected memory cell 100 is increased, whereby data can be easily written, only if the power supply voltage is low.
- the power supply voltage VDD is high
- data can be written into the memory cell 100 without causing the potential of the selected bit line to be negative. This is because, if each node is caused to have a negative potential, then particularly when the power supply voltage VDD is high, excessively large electrical stress is applied to elements connected to the nodes having a negative potential, so that the reliability of the element is deteriorated and data held by a non-selected memory cell connected to a selected bit line is destroyed.
- the clamp circuit 105 A When the power supply voltage VDD becomes higher than 1.2 V, the clamp circuit 105 A is activated, so that the H-level potential VCH of the capacitance element input node CIN 2 becomes a potential that is determined by a ratio of drive performance between the P-type MOS transistor OP 10 and the clamp circuit 105 A.
- the absolute value of the negative potential VBB is not high even if the power supply voltage VDD is high.
- the word line WL 1 goes from the H level to the L level, and all the memory cells 100 go into the non-selected state.
- the write control signal WT 1 goes from the H level to the L level, so that all the column selection circuits 102 go into the non-active state.
- the capacitance element control signal /CIN goes from the H level to the L level and then the capacitance element input node CIN 2 goes to the H level, so that the N-type MOS transistor QN 7 is turned ON and therefore the capacitance element output node COUT is discharged to the L level.
- the precharge control signal PCG goes from the H level to the L level, so that all the precharge circuits 101 go into the active state and therefore all the bit lines are precharged to the H level.
- a data write characteristic to the memory cell 100 can be improved as in the conventional art.
- the power supply voltage VDD is high, the potential of a selected bit line or the like during a data write operation to a memory cell 100 can be controlled so that it is higher than that in the conventional art. Therefore, electrical stress applied to elements connected to a selected bit line or the like can be reduced, thereby making it possible to suppress a deterioration in reliability. Also, it is possible to prevent destruction of data held by a non-selected memory cell connected to a selected bit line.
- the operation power supply voltage of the semiconductor storage device, the threshold voltage of a transistor in the semiconductor storage device, and the like vary depending on the operation power supply voltage specifications, process conditions and the like of the semiconductor storage device. It has been assumed in this embodiment that the threshold voltage of the N-type MOS transistors QN 11 and QN 12 included in the clamp circuit 105 A is 0.6 V and the power supply voltage VDD at which operations are switched (border voltage) is 1.2 V.
- the clamp circuit 105 A may include only one N-type MOS transistor or a plurality of N-type MOS transistors connected in series (e.g., three N-type MOS transistors connected in series), for example.
- a P-type MOS transistor having a gate terminal in diode connection or a PN-junction diode may be used instead of an N-type MOS transistor.
- the P-type MOS transistor, the N-type MOS transistor, the PN-junction diode, a resistance element, and the like may be used in combination.
- the configuration of the clamp circuit 105 A may be changed, depending on operation conditions required for the semiconductor storage device.
- FIG. 6 is a diagram showing another example of the clamp circuit 105 A of FIG. 5 .
- the clamp circuit 105 B of FIG. 6 further includes fuse elements F 3 and F 4 connected in parallel with the N-type MOS transistors QN 11 and QN 12 of the clamp circuit 105 A of FIG. 5 .
- the border voltage at which operations are switched can be changed to any voltage, depending on operation conditions required for the semiconductor storage device, by cutting one of the fuse elements.
- FIG. 6 shows an example in which the fuse elements F 3 and F 4 are used as means for switching set voltages.
- the source terminal and the drain terminal of a transistor may be connected in parallel and the gate terminal of the transistor may be ON/OFF controlled, thereby achieving an operation and an effect similar to those when fuse elements are used.
- FIG. 7 is a diagram showing another example of the clamp circuit 105 A of FIG. 5 .
- another N-type MOS transistor QN 13 is connected in series between the N-type MOS transistor QN 11 included in the clamp circuit 105 A of FIG. 5 and the capacitance element input node CIN 2 , and the gate terminal of the N-type MOS transistor QN 13 is connected to the capacitance element control signal /CIN.
- the clamp circuit may be activated only during a write operation.
- the capacitance element control signal /CIN is at the L level and therefore the capacitance element input node CIN 2 is at the H level, so that the N-type MOS transistor QN 7 is turned ON and therefore the capacitance element output node COUT is discharged to the L level.
- the clamp circuit 105 A is in the non-active state when the power supply voltage VDD is low (lower than 1.2 V)
- the clamp circuit 105 A is activated when the power supply voltage VDD becomes high (exceeds 1.2 V), so that a stationary current flows from the P-type MOS transistor QP 10 via the clamp circuit 105 A.
- the clamp circuit 105 C of FIG. 7 another N-type MOS transistor QN 13 is connected in series between the N-type MOS transistor QN 11 and the capacitance element input node CIN 2 , so that when a word line is in the non-active state, the capacitance element control signal /CIN is at the L level and therefore the N-type MOS transistor QN 13 can be turned OFF.
- the clamp circuit 105 C is activated only during a write operation, and is in the non-active state when it is not during a write operation, so that a stationary current that would otherwise flow when it is not during a write operation can be eliminated, resulting in lower power consumption.
- the configuration of FIG. 7 is applicable to the configuration of FIG. 6 .
- FIG. 8 is a diagram showing another example of the clamp circuit 105 A of FIG. 5 .
- a P-type MOS transistor QP 11 having a gate terminal in diode connection
- a P-type MOS transistor QP 12 having a gate terminal connected to the capacitance element input node CIN 2
- an N-type MOS transistor QN 15 having a gate terminal connected to the power supply voltage VDD are connected in series between the power supply voltage VDD and a ground power supply voltage.
- An intersection of the drain terminal of the P-type MOS transistor QP 12 and the drain terminal of the N-type MOS transistor QN 15 is referred to as a gate control node VGN 2 .
- the gate control node VGN 2 is connected to the gate terminal of an N-type MOS transistor QN 14 connected between the capacitance element input node CIN 2 and the ground power supply voltage.
- the capacitance element control signal /CIN is at the L level, so that the P-type MOS transistor QP 12 is OFF and therefore the gate control node VGN 2 invariably outputs the L level by the N-type MOS transistor QN 15 whose gate terminal is at the power supply voltage VDD. Therefore, the N-type MOS transistor QN 14 that receives the gate control node VGN 2 at the gate terminal thereof is invariably OFF and therefore does not have an influence on the capacitance element input node CIN 2 .
- the configuration of the clamp circuit 105 D of FIG. 8 in which the voltage of the gate terminal of the transistor QN 14 connected between the capacitance element input node CIN 2 and the ground power supply voltage is controlled, can also achieve an operation and an effect similar to those of FIG. 5 .
- the P-type MOS transistor QP 12 in the clamp circuit 105 D of FIG. 8 may not be provided in terms of an operation. However, when it is not during a write operation and the capacitance element control signal /CIN is at the L level and therefore the capacitance element input node CIN 2 is at the H level, the P-type MOS transistor QP 12 is turned OFF, so that a stationary current does not flow from the power supply voltage VDD via the N-type MOS transistor QN 15 to the ground power supply voltage, thereby making it possible to achieve lower power consumption.
- the operation power supply voltage of a semiconductor storage device, the threshold voltage of a transistor in a semiconductor storage device, and the like vary depending on the operation power supply voltage specifications, process conditions or the like of the semiconductor storage device.
- two or more P-type MOS transistors QP 11 each having a gate terminal in diode connection may be connected in series in the clamp circuit 105 D, or alternatively, instead of a P-type MOS transistor, an N-type MOS transistor having a gate terminal in diode connection or a PN-junction diode element may be used.
- a P-type MOS transistor, an N-type MOS transistor, a PN-junction diode, a resistance element and the like may be used in combination.
- the fuse elements F 3 and F 4 of FIG. 6 may be connected in parallel with a transistor, or alternatively, instead of these fuse elements, a transistor may be connected in parallel and the gate terminal of the transistor may be ON/OFF controlled.
- the configuration of the clamp circuit 105 D may be changed, depending on operation conditions required for the semiconductor storage device.
- FIG. 10 is a timing chart showing an operation of a semiconductor storage device according to Embodiment 3 of the present invention.
- FIG. 9 is a timing chart showing an operation of a conventional semiconductor storage device. The timing chart of FIG. 9 corresponds to an operation of a configuration that is obtained by removing the clamp circuit 103 A from the configuration of FIG. 1 of Embodiment 1 of the present invention.
- Embodiment 1 of the present invention an operation in which a selected bit line or the like is caused to have a negative potential during a write operation, will be described.
- the word line WL 1 is selected and caused to go to the H level.
- the write control signal WT 1 is selected and caused to go to the H level. Therefore, the N-type MOS transistor QN 5 in the column selection circuit 102 connected to the bit line BL 1 is turned ON, so that the bit line BL 1 and the capacitance element output node COUT are connected to each other via the N-type MOS transistor QN 5 .
- the capacitance element control signal CIN is caused to go from the H level to the L level. Since the capacitance element control signal CIN goes to the L level, the N-type MOS transistor QN 7 is turned OFF.
- the capacitance of the capacitance element CAP is Cc
- the capacitance element control signal CIN goes from the H level (VDD) to the L level (0 V)
- an amount of electric charges corresponding to Cc ⁇ VDD are extracted from electric charges in all capacitances (capacitance C 1 ) of the bit line BL 1 , the capacitance element output node COUT and the storage node (in this case, the source terminal node of the access transistor QN 3 ) of the selected memory cell 100 .
- the potential of the bit line BL 1 or the like is changed from 0 V to ⁇ (Cc ⁇ VDD)/(Cc+C 1 ), i.e., a negative potential.
- the capacitance element control signal CIN is caused to go from the H level to the L level.
- the potential of the bit line BL 1 when the capacitance element control signal CIN is caused to go from the H level to the L level is VBL
- the potential of the bit line BL 1 or the like when the capacitance element control signal CIN is caused to go from the H level to the L level is (C 1 ⁇ VBL ⁇ Cc ⁇ VDD)/(Cc+C 1 ).
- the potential of the bit line BL 1 or the like can be controlled so that it has a higher value than when the capacitance element control signal CIN is caused to go from the H level to the L level after the potential of the bit line BL 1 becomes 0 V.
- the time T 1 of FIG. 9 may be changed to the time T 2 of FIG. 10 as follows, for example. If the operation timing of the capacitance element control signal CIN is determined from the timing of activation of a word line or activation of a write control signal using a delay circuit or the like, the delay circuit may be changed so that the number of connection stages of delay elements (inverters, etc.) is reduced. Also, a switching circuit or the like including a switching means in a delay circuit may be used to finely adjust a time. Also, the switching timing of the capacitance element control signal CIN may be changed using an external control signal.
- FIG. 11 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 4 of the present invention.
- the semiconductor storage device of FIG. 11 comprises a memory cell 100 including drive transistors QN 1 and QN 2 , access transistors QN 3 and QN 4 , and load transistors QP 1 and QP 2 , and a word driver circuit 106 including a P-type MOS transistor QP 13 and N-type MOS transistors QN 16 and QN 17 .
- the semiconductor storage device of FIG. 11 further comprises a word line WL, bit lines BL and /BL, a row address signal /RAD, and a power supply voltage VDD.
- Parts other than the word driver circuit 106 are assumed to be the same as a configuration (conventional semiconductor storage device) obtained by removing the clamp circuit 103 A from the configuration of FIG. 1 of Embodiment 1 of the present invention, though they are not shown for the sake of simplicity. Therefore, during a write operation to the memory cell 100 , the potential of the bit line BL or the like is lower than the negative potential VBB.
- the memory cell 100 is the same as that described in Embodiment 1 of the present invention and will not be described.
- a P-type MOS transistor QP 13 and an N-type MOS transistor QN 16 are connected in series between the power supply voltage VDD and a ground power supply voltage so that an inversion of the row address signal /RAD is output to the word line WL.
- an N-type MOS transistor QN 17 having a gate terminal connected to the power supply voltage VDD is provided between the word line WL and the ground power supply voltage, so that when the row address signal /RAD is at the L level and the word line WL goes to the H level (the word line goes to the active state), the H level of the word line WL can be controlled so that it is a potential that is lower than the power supply voltage VDD.
- the N-type MOS transistor QN 17 does not have an influence on the word line WL.
- a word driver circuit of a typical semiconductor storage device outputs a VDD level that is equal to a power supply voltage, as the H level of the word line WL.
- the N-type MOS transistor QN 17 is not provided. Therefore, in conventional semiconductor storage devices, when data is written into the memory cell 100 , an activated word line is at the VDD level and the potential of the bit line BL is the negative potential VBB that is lower than 0 V, so that the potential difference between the gate terminal and the drain terminal of the access transistor QN 3 in the memory cell 100 is higher than VDD, specifically VDD+
- the H level of the word line WL is controlled so that it is a potential that is lower than the power supply voltage VDD, so that electrical stress to the access transistor QN 3 of the memory cell 100 is reduced, whereby a deterioration in reliability can be suppressed.
- the word driver circuit 106 of this embodiment is only for illustrative purposes. Any configuration in which the H-level potential of the word line WL in the active state can be controlled so that it is a potential that is lower than the power supply voltage VDD, can be used to obtain a similar effect.
- FIG. 12 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 5 of the present invention.
- the semiconductor storage device of FIG. 12 comprises a memory cell 100 B including drive transistors QN 1 and QN 2 , access transistors QN 3 and QN 4 , and load transistors QP 1 and QP 2 , and a memory cell power supply control circuit 107 including a P-type MOS transistor QP 14 and an N-type MOS transistor QN 18 .
- the semiconductor storage device of FIG. 12 further comprises a word line WL, bit lines BL and /BL, a write enable signal WEN, a memory cell power supply voltage VDDM, and a power supply voltage VDD.
- Parts other than the memory cell power supply control circuit 107 are assumed to be the same as a configuration (conventional semiconductor storage device) obtained by removing the clamp circuit 103 A from the configuration of FIG. 1 of Embodiment 1 of the present invention, though they are not shown for the sake of simplicity. Therefore, during a write operation to the memory cell 100 B, the potential of the bit line BL or the like is lower than the negative potential VBB that is lower than 0 V.
- the memory cell 100 B has the same configuration as that of the memory cell 100 of FIG. 1 , except that, instead of the power supply voltage VDD, the memory cell power supply voltage VDDM is connected to the load transistors QP 1 and QP 2 .
- the P-type MOS transistor QP 14 having a gate terminal connected to a ground power supply voltage and the N-type MOS transistor QN 18 having a gate terminal connected to the write enable signal WEN are connected in series between the power supply voltage VDD and the ground power supply voltage, and the voltage of the drain terminals of the connected P-type MOS transistor QP 14 and N-type MOS transistor QN 18 is output as the memory cell power supply voltage VDDM.
- the write enable signal WEN is at the L level and therefore the N-type MOS transistor QN 18 is OFF. Since the P-type MOS transistor QP 14 is invariably ON, the memory cell power supply voltage VDDM is a VDD level that is equal to the power supply voltage.
- the write enable signal WEN goes to the H level and therefore the N-type MOS transistor QN 18 is turned ON, so that the memory cell power supply voltage VDDM becomes a potential that is determined by a ratio of drive performance between the P-type MOS transistor QP 14 and the N-type MOS transistor QN 18 .
- the memory cell power supply voltage VDDM can be controlled so that it is lower than the power supply voltage VDD.
- a VDD level that is equal to a power supply voltage is applied to a memory cell power supply of a typical semiconductor storage device (conventional semiconductor storage device). In other words, in such a configuration, the memory cell power supply control circuit 107 is not provided.
- the potential of the source terminal of the access transistor QN 3 becomes the negative potential VBB that is lower than 0 V. Therefore, the drain terminal of the load transistor QP 1 , the drain terminal of the drive transistor QN 1 , the gate terminal of the load transistor QP 2 , and the gate terminal of the drive transistor QN 2 that are connected to the source terminal of the access transistor QN 3 each become the negative potential VBB that is lower than 0 V. Also, in conventional semiconductor storage devices, the VDD level is applied to the source terminals of the load transistors QP 1 and QP 2 .
- that is larger than the power supply voltage VDD is applied between the drain terminal and the source terminal of the load transistor QP 1 , between the gate terminal and the drain terminal of the load transistor QP 1 , between the gate terminal and the drain terminal of the drive transistor QN 1 , the gate terminal and the source terminal of the load transistor QP 2 , between the gate terminal and the drain terminal of the load transistor QP 2 , and between the gate terminal and the drain terminal of the drive transistor QN 2 .
- the memory cell power supply voltage VDDM is controlled so that it is lower than the power supply voltage VDD during a data write operation to the memory cell 100 B as in this embodiment, the potential difference applied to each terminal of the load transistors QP 1 and QP 2 and the drive transistors QN 1 and QN 2 in the memory cell 100 B can be caused to be smaller than that in the conventional art. Therefore, electrical stress to the load transistors QP 1 and QP 2 and the drive transistors QN 1 and QN 2 in the memory cell 100 B can be reduced, so that a deterioration in reliability can be suppressed.
- the memory cell power supply control circuit 107 of this embodiment is only for illustrative purposes. Any configuration in which the memory cell power supply voltage can be controlled so that it is lower than the power supply voltage VDD during a data write operation to a memory cell 100 B, can be used to obtain a similar effect.
- FIG. 13 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 6 of the present invention.
- the semiconductor storage device of FIG. 13 comprises a column selection circuit 102 including an N-type MOS transistor QN 5 , an inverter 108 including a P-type MOS transistor QP 15 and an N-type MOS transistor QN 19 , and a clamp circuit 109 including N-type MOS transistors QN 20 and QN 21 .
- the semiconductor storage device of FIG. 13 further comprises a bit line BL, a capacitance element output node COUT, a write control signal WT, an inverted write control signal /WT, and a power supply voltage VDD.
- the configuration of this embodiment is obtained by adding the inverter 108 and the clamp circuit 109 to a configuration (conventional semiconductor storage device) that is obtained by removing the clamp circuit 103 A from the configuration of FIG. 1 of Embodiment 1 of the present invention, though it is not shown for the sake of simplicity. Therefore, during a write operation to a memory cell 100 , the potential difference between the bit line BL and the capacitance element output node COUT is the negative potential VBB that is lower than 0 V.
- the P-type MOS transistor QP 15 and the N-type MOS transistor QN 19 are connected between the power supply voltage VDD and the ground power supply voltage, and the inverted write control signal /WT is input to the gate terminal of each transistor.
- the N-type MOS transistors QN 20 and QN 21 each having a gate terminal in diode connection are connected in series between the write control signal WT and the ground power supply voltage. Therefore, when it is not during a data write operation to a memory cell 100 , the clamp circuit 109 does not have an influence on the write control signal WT, because the inverted write control signal /WT is at the H level and the write control signal WT is at the L level.
- the inverted write control signal /WT is at the L level and the write control signal WT is at the H level.
- the clamp circuit 109 is inactive and does not have an influence on the H level (VDD level) of the write control signal WT.
- the clamp circuit 109 is activated, so that the H level of the write control signal WT becomes a potential that is determined by a ratio of drive performance between the P-type MOS transistor QP 15 and the clamp circuit 109 .
- the H level of the write control signal WT is controlled so that it is lower than the power supply voltage VDD.
- the VDD level that is equal to the power supply voltage is invariably applied to the H-level potential of the write control signal WT of a typical semiconductor storage device (conventional semiconductor storage device).
- the potential of the bit line BL or the capacitance element output node COUT is the negative potential VBB that is lower than 0 V, so that the potential difference VDD+
- the H level of the write control signal WT is controlled so that it is lower than the power supply voltage VDD during a data write operation to a memory cell 100 as in this embodiment, the potential difference applied between the gate terminal and the drain terminal or between the gate terminal and the source terminal of the N-type MOS transistor QN 5 of the column selection circuit 102 , can be caused to be smaller than that in the conventional art. Therefore, electrical stress to the N-type MOS transistor QN 5 of the column selection circuit 102 can be reduced, so that a deterioration in reliability can be suppressed.
- the circuit configuration of this embodiment in which the H level of the write control signal WT is controlled so that it is lower than the power supply voltage VDD, is only for illustrative purposes. Any configuration in which the H level of the write control signal WT can be controlled so that it is lower than the power supply voltage VDD during a data write operation to a memory cell 100 , can be used to obtain a similar effect.
- FIG. 14 is a diagram showing a configuration of a semiconductor storage device according to Embodiment 7 of the present invention.
- the semiconductor storage device of FIG. 14 comprises a precharge circuit 101 B including N-type MOS transistors QN 22 , QN 23 , QN 24 , and QN 25 .
- the semiconductor storage device of FIG. 14 further comprises bit lines BL and /BL, a precharge signal /PCG, and a power supply voltage VDD.
- the configuration of this embodiment is obtained by replacing the precharge circuit 101 with the precharge circuit 101 B of FIG. 14 in a configuration (conventional semiconductor storage device) that is obtained by removing the clamp circuit 103 A from the configuration of FIG. 1 of Embodiment 1 of the present invention, though it is not shown for the sake of simplicity. Therefore, during a write operation to a memory cell 100 , the potential of the bit line BL or the like is the negative potential VBB that is lower than 0 V.
- the N-type MOS transistor QN 24 having a gate terminal in diode connection and the N-type MOS transistor QN 22 are connected in series between the power supply voltage VDD and the bit line BL
- the N-type MOS transistor QN 25 having a gate terminal in diode connection and the N-type MOS transistor QN 23 are connected in series between the power supply voltage VDD and the bit line /BL
- the precharge control signal /PCG is connected to the gate terminals of the N-type MOS transistors QN 22 and QN 23 .
- the precharge control signal /PCG when a word line is in the non-active state, the precharge control signal /PCG is caused to go to the H level, so that the N-type MOS transistors QN 22 and QN 23 are turned ON and therefore the bit lines BL and /BL are precharged to the H level.
- VTN threshold voltage of the N-type MOS transistor
- the precharge control signal /PCG is caused to be at the L level, so that the N-type MOS transistors QN 22 and QN 23 are turned OFF not to have an influence on the bit lines BL and /BL.
- a precharge circuit of a typical semiconductor storage device includes a P-type MOS transistor as in the precharge circuit 101 of FIG. 1 .
- the H-level precharge potential of a bit line is the VDD level that is equal to the power supply voltage.
- the potential of a bit line or the capacitance element output node COUT is the negative potential VBB that is lower than 0 V.
- that is larger than the power supply voltage VDD is applied between the drain terminal and the source terminal of an N-type MOS transistor connected to a non-selected bit line in the column selection circuit 102 (assuming that a selected bit line is BL 1 , the N-type MOS transistor connected to the non-selected bit line is an N-type MOS transistor that receives the write control signals /WT 1 , WT 2 and /WT 2 at the gate terminal thereof).
- that is larger than the power supply voltage VDD is applied between the gate terminal and the drain terminal or between the source terminal and the drain terminal of a P-type MOS transistor in a precharge circuit connected to the selected bit line BL 1 (e.g., the P-type MOS transistor QP 3 connected to the bit line BL 1 of FIG. 1 ).
- the H-level precharge potential of a bit line is controlled so that it is lower than the power supply voltage VDD, a potential difference applied to the drain terminal and the source terminal of an N-type MOS transistor connected to a non-selected bit line in a column selection circuit, or a potential difference applied between the gate terminal and the drain terminal and between the source terminal and the drain terminal of the precharge circuit transistor QN 22 or QN 23 connected to a selected bit line, can be caused to be smaller than that in the conventional art.
- the N-type MOS transistors QN 24 and QN 25 each having a gate terminal in diode connection in the precharge circuit 101 B may be each replaced with a P-type MOS transistor having a gate terminal in diode connection. In this case, the same effect is obtained.
- the N-type MOS transistors QN 22 and QN 23 are each replaced with a P-type MOS transistor and the polarity of the precharge signal /PCG is inverted, a similar operation can be performed.
- the P-type MOS transistor since a substrate potential is at the power supply voltage VDD, the potential difference VDD+
- the substrate potential is determined by a ground power supply voltage.
- the potential difference applied between the drain terminal and the substrate can be smaller in the case of P type than that in the case of N type. Therefore, in the case of P type, electrical stress to the precharge circuit 101 B can be reduced, so that a deterioration in reliability can be suppressed.
- a data write characteristic to a memory cell with a low power supply voltage can be improved by controlling the potential of a bit line. Particularly, a deterioration in reliability of each element can be suppressed, and the semiconductor storage device can have stable write performance and low power consumption.
- the present invention is useful as a semiconductor storage device, such as a static random access memory or the like.
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Also Published As
Publication number | Publication date |
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JP4579965B2 (en) | 2010-11-10 |
JP2009151847A (en) | 2009-07-09 |
CN101465160B (en) | 2013-04-03 |
CN101465160A (en) | 2009-06-24 |
US20090161449A1 (en) | 2009-06-25 |
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