JP7418814B2 - semiconductor circuit - Google Patents

Description

The present invention relates to a semiconductor circuit for performing pattern matching.

Non-Patent Document 1 discloses a configuration in which each weight of a kernel is expressed using a resistance value of a memristor in a convolution operation in a convolutional neural network (CNN). The configuration of Non-Patent Document 1 changes each weight of the kernel by changing the resistance value of the memristor. The configuration of Non-Patent Document 1 executes pattern matching using each weight of a desired kernel.

A memristor is a passive element that stores the electric charge that has passed through it and has the property of changing its resistance value. A memristor has two roles: a logical arithmetic unit and a storage element. Since memristors hold data in analog form as storage elements, they can be used as nonvolatile memories.

Peng Yao, Huaqiang Wu, Bin Gao, Jianshi Tang, Qingtian Zhang, Wenqiang Zhang, J. Joshua Yang & He Qian, "Fully hardware-implemented memristor convolutional neural network", Nature, Vol 577, pages 641-646, 30 January 2020

In the configuration of Non-Patent Document 1, memristors are arranged in a grid pattern, and a voltage is applied to the memristors to generate a current. In the configuration of Non-Patent Document 1, since current flows through the memristor, there is room for improvement from the viewpoint of reducing power consumption.

Therefore, in the configuration of Non-Patent Document 1, it can be expected to be effective to arrange memcapacitors including capacitors in a grid pattern instead of memristors. This is because capacitors do not conduct current, so if a memcapacitor is used, there is no need to generate current. When memcapacitors are used, each weight of the kernel is expressed using the capacitance value of each memcapacitor. A memcapacitor is a passive element that not only stores charge in the capacitor, but also has the characteristic that the capacitance value of the capacitor changes depending on the history of applied voltage.

However, it is usually not easy to accurately control the capacitance value of a capacitor. It must be said that a configuration in which the memristor is simply replaced with a memcapacitor lacks practicality.

An object of one embodiment of the present invention is to realize a semiconductor circuit that can perform pattern matching using each weight of a kernel expressed using a capacitance value of a capacitor.

In order to solve the above problems, a semiconductor circuit according to one embodiment of the present invention includes a pair of terminals BL and a terminal XBL, a terminal Y, a first capacitor having an upper electrode connected to the terminal BL, a second capacitor whose upper electrode is connected to XBL; a first transistor connected between the lower electrode of the first capacitor and the terminal Y; and between the lower electrode of the second capacitor and the terminal Y. a second transistor connected to the first transistor; a first storage element capable of storing a first signal for turning on the first transistor; and a second storage element capable of storing a second signal for turning on the second transistor. and when the first storage element stores the first signal, if the BL signal input from the terminal BL is at a predetermined level, the terminal Y has a capacitance value of the first capacitor. When outputting a Y signal of a voltage value and storing the second signal in the second storage element, if the XBL signal input from the terminal XBL is at a predetermined level, the terminal Outputs a Y signal with a voltage value corresponding to the value.

In the above configuration, the first storage element stores the first signal for turning on the first transistor, and the second storage element stores the second signal for turning on the second transistor, so that the first transistor and Turn on the second transistor. When the first transistor is turned on, the first capacitor is connected between the terminal BL and the terminal Y. By turning on the second transistor, the second capacitor is connected between the terminal XBL and the terminal Y. If the BL signal is at a predetermined level, the terminal Y outputs a Y signal with a voltage value corresponding to the capacitance value of the first capacitor. If the XBL signal is at a predetermined level, the terminal Y outputs a Y signal with a voltage value corresponding to the capacitance value of the second capacitor.

Therefore, according to the above configuration, it is possible to realize a semiconductor circuit that can perform pattern matching using each weight of the kernel expressed using the capacitance value of the capacitor.

The device includes a plurality of first capacitors, a plurality of first transistors, and a plurality of first storage elements, and the plurality of first capacitors are connected in parallel between the terminal BL and the terminal Y. Preferably.

According to the above configuration, the voltage value of the Y signal can be the sum of voltage values according to the capacitance values of the plurality of first capacitors.

The device includes a plurality of second capacitors, a plurality of second transistors, and a plurality of second storage elements, and the plurality of second capacitors are connected in parallel between the terminal XBL and the terminal Y. Preferably.

According to the above configuration, the voltage value of the Y signal can be the sum of voltage values according to the capacitance values of the plurality of second capacitors.

Preferably, each of the plurality of first capacitors has a different capacitance value, and each of the plurality of second capacitors has a different capacitance value.

According to the above configuration, by changing the combination of the first capacitors connected between the terminal BL and the terminal Y, the voltage value of the Y signal can be set to a voltage value corresponding to the combination.

A semiconductor circuit according to another aspect of the present invention includes a pair of terminals BL and XBL, a terminal Y, a first capacitor whose connection destination of an upper electrode can be switched to the terminal BL or the terminal XBL, and the first capacitor. a first transistor connected between a lower electrode of one capacitor and the terminal Y; and a first storage element capable of storing a first signal for turning on the first transistor, the first storage element When storing the first signal, if the signal input from the terminal BL or XBL to which the upper electrode of the first capacitor is connected is at a predetermined level, the terminal Y stores the first signal. A Y signal having a voltage value corresponding to the capacitance value of the first capacitor is output.

In the above configuration, whether the first capacitor is connected between the terminal BL and the terminal Y or between the terminal XBL and the terminal Y is switched. For example, when the first capacitor is connected between the terminal BL and the terminal Y, the first storage element stores the first signal for turning on the first transistor, thereby turning on the first transistor. If the BL signal is at a predetermined level, the terminal Y outputs a Y signal with a voltage value corresponding to the capacitance value of the first capacitor.

Therefore, according to the above configuration, it is possible to realize a semiconductor circuit that can perform pattern matching using each weight of the kernel expressed using the capacitance value of the capacitor.

The plurality of first capacitors includes a plurality of first capacitors, a plurality of first transistors, and a plurality of first storage elements, and the plurality of first capacitors are connected to one of the first capacitors of the terminal BL or the XBL. It is preferable that the terminal to which the upper electrode is connected and the terminal Y are connected in parallel.

According to the above configuration, the voltage value of the Y signal can be the sum of voltage values according to the capacitance values of the plurality of first capacitors.

Preferably, the capacitance values of the plurality of first capacitors are different from each other.

According to the above configuration, by changing the combination of the first capacitors connected between the terminal BL and the terminal Y, the voltage value of the Y signal can be set to a voltage value corresponding to the combination.

According to one aspect of the present invention, it is possible to perform pattern matching using each weight of a kernel expressed using a capacitance value of a capacitor.

1 is a schematic configuration diagram of a memory element according to Embodiment 1 of the present invention. FIG. 1 is a schematic configuration diagram of a capacitor element according to Embodiment 1 of the present invention. FIG. 1 is a schematic configuration diagram of a basic circuit according to Embodiment 1 of the present invention. 1 is a schematic configuration diagram of a semiconductor circuit according to Embodiment 1 of the present invention. FIG. 3 is an explanatory diagram for explaining pattern matching performed by the semiconductor circuit. FIG. 3 is an explanatory diagram for explaining pattern matching performed by the semiconductor circuit. FIG. 2 is a schematic configuration diagram of a basic circuit according to Embodiment 2 of the present invention. FIG. 2 is a schematic configuration diagram of a memory element according to Embodiment 2 of the present invention.

[Embodiment 1]
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a memory element 10 according to the first embodiment. FIG. 2 is a schematic configuration diagram of the capacitor element 20 according to the first embodiment. FIG. 3 is a schematic configuration diagram of the basic circuit 30 according to the first embodiment. FIG. 4 is a schematic configuration diagram of a semiconductor circuit 40 according to the first embodiment.

As shown in FIG. 4, the semiconductor circuit 40 includes basic circuits 401 to 409 and a determination circuit 41. In the example of FIG. 4, the number of basic circuits 401 to 409 is nine, but the first embodiment is not limited to this number. Each configuration of basic circuits 401 to 409 is the same as the configuration of basic circuit 30 in FIG. Note that the determination circuit 41 is not an essential component.

As shown in FIG. 3, the basic circuit 30 includes memory elements ME31 to ME34 and capacitor elements CE31 to CE34. In the example of FIG. 3, the number of memory elements ME31 to ME34 is four, but the first embodiment is not limited to this number. Further, in the example of FIG. 3, the number of capacitor elements CE31 to CE34 is four, but the first embodiment is not limited to this number. However, the number of memory elements ME31 to ME34 and the number of capacitor elements CE31 to CE34 are the same. Each configuration of memory elements ME31 to ME34 is the same as the configuration of memory element 10 in FIG. Each configuration of capacitor elements CE31 to CE34 is the same as the configuration of capacitor element 20 in FIG.

The semiconductor circuit 40 is a circuit that can perform pattern matching using each weight of a kernel expressed using the capacitance value of a capacitor. In particular, the semiconductor circuit 40 can provide ambiguity in pattern matching. Pattern matching with ambiguity is called "ambiguous pattern matching." Fuzzy pattern matching is a basic operation of artificial intelligence (AI).

Hereinafter, the memory element 10, capacitor element 20, basic circuit 30, and semiconductor circuit 40 will be explained in order.

(Configuration of memory element)
As shown in FIG. 1, the memory element 10 includes n-type MOS transistors N101 to N104 and p-type MOS transistors P101 to P102. In FIG. 1, WL, BL, XBL, and X represent terminal names, respectively. Hereinafter, the input signal from the terminal WL will be referred to as the WL signal, the input signal from the terminal BL will be referred to as the BL signal, the input signal from the terminal XBL will be referred to as the XBL signal, and the output signal from the terminal X will be referred to as the X signal.

Note that in FIGS. 1 to 4, terminals having the same terminal name in each figure are connected to each other unless otherwise specified. For example, the terminal X shown in FIG. 1 and the terminal X shown in FIG. 2 are connected to each other.

In FIG. 1, the drains and gates of p-type MOS transistor P1 and n-type MOS transistor N3 are connected to each other, the source of p-type MOS transistor P1 is connected to a power supply potential, and the source of n-type MOS transistor N3 is grounded. A CMOS inverter IN1 is connected to the potential. The input of the CMOS inverter IN1 is the connection point between each gate, and the output is the connection point between each drain.

Further, the drains and gates of the p-type MOS transistor P102 and the n-type MOS transistor N104 are connected to each other, the source of the p-type MOS transistor P102 is connected to the power supply potential, and the source of the n-type MOS transistor N104 is connected to the ground potential. By connecting them, a COMS inverter IN2 is constructed. The input of the CMOS inverter IN2 is the connection point between each gate, and the output is the connection point between each drain. The output of the COMS inverter IN2 is connected to the terminal X.

The output of CMOS inverter IN1 is connected to the input of CMOS inverter IN2. Further, the output of the CMOS inverter IN2 is connected to the input of the CMOS inverter IN1. CMOS inverter IN1 and CMOS inverter IN2 constitute a so-called latch circuit.

The source of the n-type MOS transistor N101 is connected to the terminal XBL, and the drain thereof is connected to the input of the CMOS inverter IN1. Further, the source of the n-type MOS transistor N102 is connected to the terminal BL, and the drain thereof is connected to the input of the CMOS inverter IN2. Each gate of the n-type MOS transistor N101 and the n-type MOS transistor N102 is connected to the terminal WL.

Normally, the BL signal input from the terminal BL and the XBL signal input from the terminal XBL are inverses of each other, that is, complementary, when their potentials are viewed as logical signals. Further, the logic signal levels of the output of the CMOS inverter IN1 and the output of the CMOS inverter IN2 are also complementary in the steady state. That is, if one is at high level, the other is at low level. For example, when the output of CMOS inverter IN1 is low level and the output of CMOS inverter IN2 is high level, it is assumed that logic "1" is stored, and vice versa, logic "0" is stored. has been decided.

The n-type MOS transistor N101 and the n-type MOS transistor N102 are used as write control transistors when writing the BL signal and the XBL signal into the memory element 10.

(Operation of memory element)
Write operation:
The write operation is an operation in which the memory element 10 writes a high level (first signal, second signal) into the memory element 10. A high level is input to the terminal BL, and the BL signal becomes high level. On the other hand, a low level is input to the terminal XBL, and the XBL signal becomes low level.

When the WL signal input to the terminal WL becomes high level, both the n-type MOS transistor N101 and the n-type MOS transistor N102 are turned on. By turning on the n-type MOS transistor N101, the XBL signal is input to the CMOS inverter IN1. By turning on the n-type MOS transistor N102, the BL signal is input to the CMOS inverter IN2.

The CMOS inverter IN1 inverts the low level of the input XBL signal to a high level, and inputs the high level to the CMOS inverter IN2. On the other hand, the CMOS inverter IN2 inverts the high level of the input XBL signal to a low level, and inputs the low level to the CMOS inverter IN1.

The output of the CMOS inverter IN1 maintains a high level, while the output of the CMOS inverter IN2 maintains a low level. Terminal X is connected to the output of CMOS inverter IN1. The X signal output from terminal X becomes high level.

Hereinafter, the above write operation will be referred to as a "write operation."

Read operation:
The read operation is an operation in which the memory element 10 reads a high level from the memory element 10.

When the WL signal input to the terminal WL becomes low level, both the n-type MOS transistor N101 and the n-type MOS transistor N102 are turned off. Therefore, the memory element 10 retains the written high level. An X signal, which is the output of the inverter IN1, is output from the terminal X. The X signal becomes a high level written in the storage element 10.

Hereinafter, the above read operation will be referred to as a "read operation".

(Configuration of capacitor element)
As shown in FIG. 2, the capacitor element 20 includes n-type MOS transistors N201 to N203 and a capacitor C201. In FIG. 2, RST, BL, X, and Y are terminal names, respectively. Hereinafter, the input signal from the terminal RST will be referred to as the RST signal, the input signal from the terminal BL will be referred to as the BL signal, the input signal from the terminal X will be referred to as the X signal, and the output signal from the terminal Y will be referred to as the Y signal.

In FIG. 2, the upper electrode of capacitor C201 is connected to terminal BL, and the lower electrode is connected to each drain of n-type MOS transistors N201 and N202. The gate of n-type MOS transistor N201 is connected to terminal X, and the source thereof is connected to the drain of n-type MOS transistor N203.

Each gate of the n-type MOS transistors N202 and N203 is connected to the terminal RST, and each source is connected to the ground potential.

The capacitor C201 is composed of an upper electrode, a lower electrode, and a dielectric material sandwiched between the upper electrode and the lower electrode. The capacitance value of the capacitor C201 is determined by at least the following: (i) the area where the upper electrode and the lower electrode face each other, (ii) the inter-electrode distance between the upper electrode and the lower electrode, and (iii) the permittivity of the dielectric material. By changing one, it can be changed.

(Operation of capacitor element)
Reset operation:
The reset operation is an operation in which the capacitor element 20 discharges the charge accumulated in the capacitor C201 of the capacitor element 20.

When the X signal input from the terminal X becomes high level and the RST signal input from the terminal RST becomes high level, the n-type MOS transistors N201 to N203 are turned on. By turning on the n-type MOS transistors N201 to N203, a low level from the ground potential is applied to the lower electrode of the capacitor C201. When the BL signal input from the terminal BL becomes low level, the low level is also applied to the upper electrode of the capacitor C201. By applying a low level to the upper and lower electrodes of the capacitor C201, the charges accumulated in the capacitor C201 are transferred to the ground potential via the n-type MOS transistors N201 and N203 or the n-type MOS transistor N202. Discharged. That is, capacitor element 20 is reset.

Hereinafter, the above-described reset operation will be referred to as a "reset operation."

Charge accumulation operation:
The charge accumulation operation is an operation in which the capacitor element 20 causes the capacitor C201 of the capacitor element 20 to accumulate charges.

When the X signal input from the terminal is turned off. By turning on the n-type MOS transistor N201, the lower electrode of the capacitor C201 is connected to the terminal Y. When the BL signal input from the terminal BL becomes a high level, a high level is applied to the upper electrode of the capacitor C201. Due to this application, charges are accumulated between the upper electrode and the lower electrode of the capacitor C201. Due to this charge accumulation, the capacitor element 20 outputs a Y signal from the terminal Y.

Here, the amount of charge accumulated in the capacitor C201 corresponds to the capacitance value of the capacitor C201. That is, the larger the capacitance value of capacitor C201, the larger the amount of charge stored in capacitor C201, and the smaller the capacitance value of capacitor C201, the smaller the amount of charge stored in capacitor C201. The voltage value of the Y signal is a voltage value according to the capacitance value of the capacitor C201.

Hereinafter, the above-described charge accumulation operation will be referred to as a "charge accumulation operation."

(Basic circuit configuration)
In FIG. 3, RST, BL, XBL, WLWP1, WLWP2, WLWM1, WLWM2, and Y are terminal names, respectively. The input signal from the terminal RST is the RST signal, the input signal from the terminal BL is the BL signal, the input signal from the terminal XBL is the XBL signal, the input signal from the terminal WLWP1 is the WLWP1 signal, the input signal from the terminal WLWP2 is the WLWP2 signal, The input signal from the terminal WLWM1 is called the WLWM1 signal, the input signal from the terminal WLWM2 is called the WLWM2 signal, and the output signal from the terminal Y is called the Y signal.

As shown in FIG. 3, terminal RST is connected to each terminal RST of capacitor elements CE31 to CE34. Terminal BL is connected to each terminal BL of memory elements ME31 to ME34 and each terminal BL of capacitor elements CE31 to CE32. Terminal XBL is connected to each terminal XBL of memory elements ME31 to ME34 and to each terminal XBL of capacitor elements CE33 to CE34. Terminal WLWP2 is connected to terminal WL of storage element ME31, terminal WLWP1 is connected to terminal WL of storage element ME32, terminal WLWM2 is connected to terminal WL of storage element ME33, and terminal WLWM1 is connected to terminal WL of storage element ME34. Terminal Y is connected to each terminal Y of capacitor elements CE31 to CE34.

Further, each of the memory elements ME31 to ME34 corresponds to each of the capacitor elements CE31 to CE34 one-to-one. Specifically, the terminal X of the memory element ME31 (first memory element) and the terminal X of the capacitor element CE31 are connected, and the X signal output from the terminal X of the memory element ME31 is input to the terminal X of the capacitor element CE31. Ru. Terminal X of memory element ME32 (first memory element) and terminal X of capacitor element CE32 are connected, and an X signal output from terminal X of memory element ME32 is input to terminal X of capacitor element CE32. Terminal X of memory element ME33 (second memory element) and terminal X of capacitor element CE33 are connected, and an X signal output from terminal X of memory element ME33 is input to terminal X of capacitor element CE33. Terminal X of memory element ME34 (second memory element) and terminal X of capacitor element CE34 are connected, and an X signal output from terminal X of memory element ME34 is input to terminal X of capacitor element CE34.

The memory elements ME31 to ME34 execute a write operation when a low level is applied to each terminal XBL, a high level is applied to each terminal BL, and a high level is applied to each terminal WL. Specifically, a low level is input to each terminal XBL of the memory elements ME31 to ME34 at the same time, and a high level is input to each terminal BL at the same time. Of the memory elements ME31 to ME34, only the memory element whose terminal WL is at a high level executes a write operation. For example, when the WLWP2 signal input from the terminal WLWP2 becomes high level, the memory element ME31, where the high level is input from the terminal WLWP2 to the terminal WL, executes a write operation.

Further, the memory elements ME31 to ME34 execute a read operation when a low level is input to each terminal WL. Specifically, among the memory elements ME31 to ME34, only the memory element whose terminal WL is at a low level executes a read operation. For example, when the WLWP2 signal input from the terminal WLWP2 becomes a low level, the storage element ME31, whose low level is input from the terminal WLWP2 to the terminal WL, executes a read operation.

Capacitor elements CE31 to CE34 execute a reset operation when a high level is applied to each terminal X, a high level is applied to each terminal RST, and a low level is applied to each terminal BL. Specifically, a high level is input to each terminal RST of the capacitor elements CE31 to CE34 at the same time, and a high level is input to each terminal BL at the same time. Of the capacitor elements CE31 to CE34, only the capacitor element whose terminal X receives a high level executes the reset operation. For example, when the X signal output from the terminal X of the memory element ME31 becomes a high level, the capacitor element CE31 to which the high level is input from the terminal X of the memory element ME31 executes a reset operation. Note that during the reset operation of the capacitor elements CE31 to CE32, the BL signal input to the terminal BL becomes high level. Furthermore, during the reset operation of the capacitor elements CE33 to CE34, the BL signal input to the terminal XBL becomes high level. When the reset operations of the capacitor elements CE31 to CE34 are performed all at once, both the BL signal input to the terminal BL and the XBL signal input to the terminal XBL become high level.

Further, the capacitor elements CE31 to CE34 execute a charge storage operation when a high level is applied to each terminal X, a low level is applied to each terminal RST, and a high level is applied to each terminal BL. Specifically, a low level is input to each terminal RST of the capacitor elements CE31 to CE34 at the same time, and a high level is input to each terminal BL at the same time. Of the capacitor elements CE31 to CE34, only the capacitor element whose terminal X receives a high level performs a charge storage operation. Conversely, among the capacitor elements CE31 to CE34, the capacitor element whose terminal X does not receive a high level does not perform the charge storage operation. For example, when the X signal output from the terminal X of the storage element ME31 becomes a high level, the capacitor element CE31 to which the high level is input from the terminal X of the storage element ME31 executes a charge storage operation. Note that during the charge storage operation of the capacitor elements CE31 to CE32, the BL signal input to the terminal BL becomes high level. In this case, the XBL signal input to the terminal XBL becomes low level. Further, when the capacitor elements CE33 to CE34 perform charge storage operation, the XBL signal input to the terminal XBL becomes high level. In this case, the BL signal input to the terminal BL becomes low level.

(Basic circuit operation)
The operation of the basic circuit 30 will be described below, taking as an example a case where the basic circuit 30 causes the capacitor elements CE31 and CE33 to perform the charge accumulation operation, but does not cause the capacitor elements CE32 and CE34 to perform the charge accumulation operation.

Discharge operation:
The discharging operation is an operation in which the basic circuit 30 causes each of the capacitor elements CE31 to CE34 to perform a reset operation.

First, the memory elements ME31 to ME34 perform a write operation. That is, a high level is written to the memory elements ME31 to ME34.

Next, the memory elements ME31 to ME34 perform a read operation. That is, the X signal output from each terminal X of the memory elements ME31 to ME34 becomes high level.

Finally, capacitor elements CE31 to CE34 perform a reset operation. That is, capacitor elements CE31 to CE34 discharge the charges accumulated in each capacitor C201.

Hereinafter, the above-mentioned discharging operation will be referred to as "discharging operation".

Weight setting behavior:
The weight setting operation is an operation in which the basic circuit 30 sets a capacitor element among the capacitor elements CE31 to CE34 to perform a charge storage operation. Note that "weight" is each weight of a kernel used in a convolution operation in a convolutional neural network. Among the capacitor elements CE31 to CE34, the capacitor element that performs a charge storage operation is a capacitor element that expresses one weight of the kernel using the capacitor C201.

Memory elements ME31 and ME33 perform write operations. Memory elements ME32 and ME34 do not perform write operations. That is, a high level is written to the memory elements ME31 and ME33. On the other hand, a high level is not written to the memory elements ME32 and ME34.

As a result, the capacitor element CE31, to which the high-level X signal output from the terminal X of the memory element ME31 is input, can perform a charge storage operation. Further, the capacitor element CE33, to which the high-level X signal outputted from the terminal X of the memory element ME33 is inputted, can perform a charge storage operation. On the other hand, the capacitor elements CE32 and CE34 to which the high-level X signal is not input to the terminal X cannot perform the charge storage operation. In other words, capacitor elements CE31 and CE33 are set as capacitor elements that perform a charge storage operation.

Hereinafter, the above-described weight setting operation will be referred to as a "weight setting operation."

Output operation:
The output operation is an operation in which the basic circuit 30 causes the capacitor elements CE31 and CE33 to perform a charge accumulation operation, and outputs a Y signal to the terminal Y.

If the BL signal input to the terminal BL is at a high level (at this time, the XBL signal input to the terminal XBL is at a low level), the capacitor element CE31 performs a charge storage operation. That is, at the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 (first capacitor) of the capacitor element CE31 is output.

On the other hand, if the XBL signal input to the terminal XBL is at a high level (at this time, the BL signal input to the terminal BL is at a low level), the capacitor element CE33 performs a charge storage operation. That is, at the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 (second capacitor) of the capacitor element CE33 is output.

Note that, as described above, among the capacitor elements CE31 and CE33 that are set as capacitor elements that perform a charge accumulation operation, if the BL signal input to the terminal BL is at a high level, the basic circuit 30 charges the capacitor element CE31. On the other hand, if the XBL signal input to the terminal XBL is at a high level, the capacitor element CE33 is caused to perform the charge accumulation operation. That is, the basic circuit 30 causes only one of the capacitor elements CE31 and CE33 to perform a charge accumulation operation according to the level of the BL signal input to the terminal BL and the level of the XBL signal input to the terminal XBL. should be kept in mind.

Hereinafter, the above-described output operation will be referred to as an "output operation."

In the above description, the basic circuit 30 causes the capacitor elements CE31 and CE33 to perform the charge accumulation operation, and causes the capacitor elements CE32 and CE34 to perform the charge accumulation operation in the above-mentioned "discharge operation", "weight setting operation", and "output operation". Although a case has been described as an example in which the process is not executed, the first embodiment is not limited to this case. For example, the basic circuit 30 may cause the capacitor elements CE32 and CE34 to perform the charge accumulation operation, but not cause the capacitor elements CE31 and CE33 to perform the charge accumulation operation. Further, for example, the basic circuit 30 may cause the capacitor elements CE31 to CE34 to perform the charge accumulation operation, or may not cause the capacitor elements CE31 to CE34 to perform the charge accumulation operation.

(Effect of basic circuit)
In the example of FIG. 3, the capacitor element CE31 and the capacitor element CE32 are connected to the terminal BL, and the capacitor elements CE33 and CE34 are connected to the terminal XBL. Between terminal BL and terminal Y, capacitor C201 of capacitor element CE31 and capacitor C201 of capacitor element CE32 are connected in parallel. Further, between the terminal XBL and the terminal Y, the capacitor C201 of the capacitor element CE33 and the capacitor C201 of the capacitor element CE34 are connected in parallel.

Regarding the terminal BL, when the BL signal input to the terminal BL is at a high level, the combinations of capacitor elements that cause the basic circuit 30 to perform a charge storage operation are as follows.
・Capacitor elements CE31 and CE32,
・Capacitor element CE31 only,
・Capacitor element CE32 only,
·none.

Here, if the capacitance value ratio of each capacitor C201 of capacitor elements CE31 and CE32 is 2:1, then in each of the above combinations, the voltage value ratio of the Y signal output at terminal Y is 3:2:1:0. becomes. That is, when the BL signal input to the terminal BL is at a high level, there are four voltage values of the Y signal output from the terminal Y. In addition, the relationship between each of the above-mentioned voltage value ratios and each of the above-mentioned combinations is as follows.
・Capacitor elements CE31 and CE32:3,
・Capacitor element CE31 only: 2,
・Capacitor element CE32 only: 1,
・None: 0,
Similarly, if the capacitance value ratio of each capacitor C201 of capacitor elements CE32 and CE33 is 2:1, when the XBL signal input to the terminal XBL is at a high level, the voltage value of the Y signal output at the terminal Y There are 4 ways.

The basic circuit 30 uses one of the four voltage values described above to represent one weight included in the kernel used in the convolution operation in the convolutional neural network. In the above example, the basic circuit 30 can express four types of weights when the BL signal input to the terminal BL is at a high level. Furthermore, the basic circuit 30 can express four types of weights even when the XBL signal input to the terminal XBL is at a high level. Further, for example, in the case of a 3×3 kernel, the total number of weights included in the kernel is 3×3=9. Therefore, nine basic circuits are required to express each weight of a 3×3 kernel.

Note that in the example of FIG. 3, two capacitor elements 20 are connected to the terminal BL, but for example, three capacitor elements 20 may be connected. In this case, if the capacitance ratio of the capacitor C201 of each capacitor element 20 is 4:2:1, when the BL signal input to the terminal BL is at a high level, the voltage value ratio of the Y signal output at the terminal Y becomes 7:6:5:4:3:2:1:0. That is, when the BL signal input to the terminal BL is at a high level, there are eight voltage values of the Y signal output from the terminal Y.

Note that the number of capacitor elements 20 connected to the terminal BL is not limited to the two or three described above. Further, the number of capacitor elements 20 connected to the terminal XBL is not limited to the above-mentioned two or three, as in the case of the terminal BL.

(Semiconductor circuit configuration)
In FIG. 4, RST, BL, XBL, WLWP1, WLWP2, WLWM1, WLWM2, and Y are terminal names, respectively. The input signal from the terminal RST is the RST signal, the input signal from the terminal BL is the BL signal, the input signal from the terminal XBL is the XBL signal, the input signal from the terminal WLWP1 is the WLWP1 signal, the input signal from the terminal WLWP2 is the WLWP2 signal, The input signal from the terminal WLWM1 is called the WLWM1 signal, the input signal from the terminal WLWM2 is called the WLWM2 signal, and the output signal from the terminal Y is called the Y signal.

As shown in FIG. 4, terminal RST is connected to each terminal RST of basic circuits 401 to 409. Terminal WLWP2 is connected to each terminal WLWP2 of basic circuits 401-409. Terminal WLWP1 is connected to each terminal WLWP1 of basic circuits 401-409. Terminal WLWM2 is connected to each terminal WLWM2 of basic circuits 401-409. Terminal WLWM1 is connected to each terminal WLWM1 of basic circuits 401-409. Terminal Y is connected to each terminal Y of basic circuits 401-409. The voltage value of the Y signal output from terminal Y is the sum of the voltage values of the Y signals output from each terminal Y of basic circuits 401 to 409.

Terminal group BL<0:8> includes nine terminals. In detail, the terminal group BL<0:8> includes terminal BL<0>, terminal BL<1>, terminal BL<2>, terminal BL<3>, terminal BL<4>, terminal BL<5>, It includes a terminal BL<6>, a terminal BL<7>, and a terminal BL<8>. Terminal BL<0> is connected to terminal BL of basic circuit 401. Terminal BL<1> is connected to terminal BL of basic circuit 402. Terminal BL<2> is connected to terminal BL of basic circuit 403. Terminal BL<3> is connected to terminal BL of basic circuit 404. Terminal BL<4> is connected to terminal BL of basic circuit 405. Terminal BL<5> is connected to terminal BL of basic circuit 406. Terminal BL<6> is connected to terminal BL of basic circuit 407. Terminal BL<7> is connected to terminal BL of basic circuit 408. Terminal BL<8> is connected to terminal BL of basic circuit 409.

Terminal group XBL<0:8> includes nine terminals. In detail, the terminal group XBL<0:8> includes terminals XBL<0>, terminals XBL<1>, terminals XBL<2>, terminals XBL<3>, terminals XBL<4>, terminals XBL<5>, It includes a terminal XBL<6>, a terminal XBL<7>, and a terminal XBL<8>. Terminal XBL<0> is connected to terminal XBL of basic circuit 401. Terminal XBL<1> is connected to terminal XBL of basic circuit 402. Terminal XBL<2> is connected to terminal XBL of basic circuit 403. Terminal XBL<3> is connected to terminal XBL of basic circuit 404. Terminal XBL<4> is connected to terminal XBL of basic circuit 405. Terminal XBL<5> is connected to terminal XBL of basic circuit 406. Terminal XBL<6> is connected to terminal XBL of basic circuit 407. Terminal XBL<7> is connected to terminal XBL of basic circuit 408. Terminal XBL<8> is connected to terminal XBL of basic circuit 409. Terminals BL and terminals XBL with the same numbers in <> are a pair. That is, in a pair of terminals BL and XBL, if one is at high level, the other is at low level, and if one is at low level, the other is at high level.

A Y signal output from terminal Y is input to the determination circuit 41 . The determination circuit 41 compares the voltage value of the Y signal with a predetermined threshold T. When the voltage value of the Y signal is equal to or greater than the threshold value T, the determination circuit 41 outputs a first signal indicating that the voltage value of the Y signal is equal to or greater than the threshold value T. The first signal is, for example, a high level signal. On the other hand, when the voltage value of the Y signal is less than the threshold T, a second signal indicating that the signal level of the Y signal is less than the threshold T is output. The second signal is, for example, a low level signal.

(Operation of semiconductor circuit)
The operation of the semiconductor circuit 40, that is, the pattern matching performed by the semiconductor circuit 40 will be described using FIGS. 5 and 6. 5 and 6 are explanatory diagrams for explaining pattern matching performed by the semiconductor circuit 40. First, FIGS. 5 and 6 will be explained.

The example in FIG. 5 is the result of pattern matching performed by the semiconductor circuit 40 by comparing the normal pattern with each of the input patterns P1 to P17. Hereinafter, input patterns P1 to P17 will be collectively referred to as input pattern P. In FIG. 5, "BL0" to "BL8" respectively mean terminals corresponding to terminals BL<0> to BL<8> included in the terminal group BL<0:8> in FIG. 4, respectively. The numbers following "BL" in FIG. 5 and the numbers in <> following the terminal BL in FIG. 4 correspond to each other.

Further, in the example of FIG. 5, the normal pattern and the input pattern P are a 9-bit binary number sequence consisting of logic "1" and logic "0". In both the normal pattern and the input pattern P, 1 bit, 2 bits, . . . , 8 bits, and 9 bits are lined up from the top to the bottom of the paper in FIG. In FIG. 4, 1 bit of the input pattern P is stored in the terminal BL<0>, 2 bits of the input pattern P is stored in the terminal BL<1>, 3 bits of the input pattern P is stored in the terminal BL<2>, and the terminal BL <3> has 4 bits of input pattern P, terminal BL <4> has 5 bits of input pattern P, terminal BL <5> has 6 bits of input pattern P, and terminal BL <6> has 7 bits of the input pattern P are input to the terminal BL<7>, 8 bits of the input pattern P are input to the terminal BL<8>, and 9 bits of the input pattern P are input to the terminal BL<8>. Note that when the BL signal input to the terminal group BL<0:8> in FIG. 4 is at a high level, logic "1" is input. Furthermore, when the BL signal input to the terminal group BL<0:8> in FIG. 4 is at a low level, logic "0" is input. Furthermore, when the XBL signal input to the terminal group XBL<0:8> in FIG. 4 is at a high level, logic "1" is input. Furthermore, when the XBL signal input to the terminal group XBL<0:8> in FIG. 4 is at a low level, logic "0" is input.

Note that the logic of each bit of the input pattern P is input as is to the terminal group BL<0:8> in FIG. On the other hand, logic obtained by inverting the logic of each bit of the input pattern P is input to the terminal group XBL<0:8> in FIG. For example, when each bit of "000000000" which is the input pattern P1 is input to the terminal group BL<0:8>, each bit of "111111111" is input to the terminal group XBL<0:8>. It turns out.

Further, in FIG. 5, the "number of matches" indicates the number of matches between the same bits of the original pattern and the input pattern P. Moreover, the "number of mismatches" indicates the number of times when the same bits of the normal pattern and the input pattern P do not match. In the example of FIG. 5, the number of matches between the same bits of the normal pattern and the input pattern P1 is "4". Specifically, 1 bit, 2 bits, 5 bits, and 6 bits of the normal pattern and the input pattern P1 match each other. On the other hand, the number of times in which the same bits of the normal pattern and the input pattern P1 do not match is "5". Specifically, the 3rd bit, 4th bit, and 7th to 9th bits of the normal pattern and the input pattern P1 do not match.

Furthermore, in FIG. 5, "output" indicates the voltage value of the Y signal output to terminal Y in FIG. When each bit of the input pattern P is input to the terminal group BL<0:8> in FIG. 4, a Y signal is output to the terminal Y. In the example of FIG. 5, the voltage value of the Y signal is roughly divided into three voltage values "I," "II," and "III."

FIG. 6 is a schematic diagram showing changes in the voltage value of the Y signal output to the terminal Y when input patterns P1 to P17 are sequentially input to the terminal group BL<0:8>. In FIG. 6, the vertical axis represents the voltage value of the Y signal, and the horizontal axis represents time. Note that the vertical axis indicates that the voltage value increases from the top to the bottom of the paper in FIG. Furthermore, as mentioned above, input patterns P1, P2, ..., P16, P17 are input in this order to the terminal group BL<0:8>, so in the example of FIG. Then, a voltage value corresponding to input pattern P1, a voltage value corresponding to input pattern P2, . . . , a voltage value corresponding to input pattern P16, a voltage value corresponding to input pattern P17 appear in this order. In the example of FIG. 6, "I", "II", and "II" are respectively output to the locations where the Y signals of voltage values "I", "II", and "III", which are the voltage values shown in "Output" of FIG. 5, are output. and "III". Furthermore, by referring to "P1", "P2", etc. written below each symbol, it is understood which of the input patterns P1, P2, etc. in FIG. 5 each symbol corresponds to. Further, in the example of FIG. 6, the voltage values "I" and "II" are voltage values exceeding the threshold value T. On the other hand, the voltage value "III" is a voltage value below the threshold value T.

The pattern matching performed by the semiconductor circuit 40 is ambiguous pattern matching. Specifically, the semiconductor circuit 40 determines that the input pattern P matches the normal pattern when all the bits of the normal pattern and the input pattern P match. Further, even if all the bits of the input pattern P and the input pattern P do not match, the semiconductor circuit 40 determines that the input pattern P matches the input pattern if the number of matches exceeds a certain percentage. The semiconductor circuit 40 performs pattern matching vaguely, that is, it allows a certain degree of mismatch, and even if the input pattern does not exactly match the correct pattern, it determines that they match.

Ambiguous pattern matching performed by the semiconductor circuit 40 will be described below with reference to FIGS. 5 and 6. Note that in the following, it is assumed that the basic circuit 30 of FIG. 3 uses the memory elements ME31 and ME33 and the capacitor elements CE31 and CE33, and does not use the memory elements ME32 and ME34 and the capacitor elements CE32 and CE34. do. Further, it is assumed that the capacitance values of each capacitor C201 of capacitor elements CE31 and CE33 are the same.

First, the semiconductor circuit 40 causes each of the basic circuits 401 to 409 to perform a discharging operation.

Next, the semiconductor circuit 40 causes each of the basic circuits 401 to 409 to execute a weight setting operation. More specifically, since one bit of the positive pattern in FIG. 5 is logic "0", the semiconductor circuit 40 causes the memory element ME33 of the basic circuit 401 to execute the write operation.

The semiconductor circuit 40 causes the memory element ME33 of the basic circuit 402 to execute the write operation since the two bits of the positive pattern in FIG. 5 are logic "0".

The semiconductor circuit 40 causes the memory element ME31 of the basic circuit 403 to execute the write operation since the three bits of the positive pattern in FIG. 5 are logic "1".

Since the four bits of the positive pattern in FIG. 5 are logic "1", the semiconductor circuit 40 causes the memory element ME31 of the basic circuit 404 to execute the write operation.

Since the 5 bits of the positive pattern in FIG. 5 are logic "0", the semiconductor circuit 40 causes the memory element ME33 of the basic circuit 405 to execute the write operation.

Since the six bits of the positive pattern in FIG. 5 are logic "0", the semiconductor circuit 40 causes the memory element ME33 of the basic circuit 406 to execute the write operation.

The semiconductor circuit 40 causes the memory element ME31 of the basic circuit 407 to execute the write operation since the 7 bits of the positive pattern in FIG. 5 are logic "1".

The semiconductor circuit 40 causes the memory element ME31 of the basic circuit 408 to execute the write operation since the 8 bits of the positive pattern in FIG. 5 are logic "1".

Since the 9 bits of the positive pattern in FIG. 5 are logic "1", the semiconductor circuit 40 causes the memory element ME31 of the basic circuit 406 to execute the write operation.

Next, the semiconductor circuit 40 causes each of the basic circuits 401 to 409 to perform an output operation. Hereinafter, a case in which the semiconductor circuit 40 compares the normal pattern with each of the input patterns P1, P5, and P13 and performs pattern matching will be described in more detail.

First, a case will be described in which the semiconductor circuit 40 compares the normal pattern with the input pattern P1 and performs pattern matching.

Since one bit of the input pattern P1 is logic "0", the BL signal input to the terminal BL<0> becomes a low level, and the XBL signal input to the terminal XBL<0> becomes a high level. The semiconductor circuit 40 causes the capacitor element CE33 of the basic circuit 401 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 401 is output.

Since two bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<1> becomes a low level, and the XBL signal input to the terminal XBL<1> becomes a high level. The semiconductor circuit 40 causes the capacitor element CE33 of the basic circuit 402 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 402 is output.

Since three bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<2> becomes a low level, and the XBL signal input to the terminal XBL<2> becomes a high level. The memory element ME33 of the basic circuit 403 is not performing a write operation. Therefore, the semiconductor circuit 40 does not cause the capacitor element CE33 of the basic circuit 403 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 403 is not output.

Since the four bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<3> becomes a low level, and the XBL signal input to the terminal XBL<3> becomes a high level. The memory element ME33 of the basic circuit 404 is not performing a write operation. Therefore, the semiconductor circuit 40 does not cause the capacitor element CE33 of the basic circuit 404 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 404 is not output.

Since 5 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<4> becomes a low level, and the XBL signal input to the terminal XBL<4> becomes a high level. The semiconductor circuit 40 causes the capacitor element CE33 of the basic circuit 405 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 405 is output.

Since the 6 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<5> becomes a low level, and the XBL signal input to the terminal XBL<5> becomes a high level. The semiconductor circuit 40 causes the capacitor element CE33 of the basic circuit 406 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 406 is output.

Since the 7 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<6> becomes a low level, and the XBL signal input to the terminal XBL<6> becomes a high level. The memory element ME33 of the basic circuit 407 is not performing a write operation. Therefore, the semiconductor circuit 40 does not cause the capacitor element CE33 of the basic circuit 407 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 407 is not output.

Since the 8 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<7> becomes a low level, and the XBL signal input to the terminal XBL<7> becomes a high level. The memory element ME33 of the basic circuit 408 is not performing a write operation. Therefore, the semiconductor circuit 40 does not cause the capacitor element CE33 of the basic circuit 408 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 408 is not output.

Since the 9 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<8> becomes a low level, and the XBL signal input to the terminal XBL<8> becomes a high level. The memory element ME33 of the basic circuit 409 is not performing a write operation. Therefore, the semiconductor circuit 40 does not cause the capacitor element CE33 of the basic circuit 409 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 409 is not output.

As described above, when the semiconductor circuit 40 compares the positive pattern and the input pattern P1 and performs pattern matching, the voltage value of the Y signal output from the terminal Y of the semiconductor circuit 40 is , 405 and 406 are the sum of the voltage values of the Y signals output from each terminal Y. The voltage value is "III" in FIGS. 5 and 6.

Next, a case will be described in which the semiconductor circuit 40 compares the normal pattern with the input pattern P5 and performs pattern matching.

Since one bit of the input pattern P5 is logic "0", the BL signal input to the terminal BL<0> becomes a low level, and the XBL signal input to the terminal XBL<0> becomes a high level. The semiconductor circuit 40 causes the capacitor element CE33 of the basic circuit 401 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 401 is output.

Since two bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<1> becomes a low level, and the XBL signal input to the terminal XBL<1> becomes a high level. The semiconductor circuit 40 causes the capacitor element CE33 of the basic circuit 402 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 402 is output.

Since three bits of the input pattern P1 are logic "1", the BL signal input to the terminal BL<2> becomes a high level, and the XBL signal input to the terminal XBL<2> becomes a low level. The semiconductor circuit 40 causes the capacitor element CE31 of the basic circuit 403 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE31 of the basic circuit 403 is output.

Since the four bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<3> becomes a low level, and the XBL signal input to the terminal XBL<3> becomes a high level. The memory element ME33 of the basic circuit 404 is not performing a write operation. Therefore, the semiconductor circuit 40 does not cause the capacitor element CE33 of the basic circuit 404 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 404 is not output.

Since 5 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<4> becomes a low level, and the XBL signal input to the terminal XBL<4> becomes a high level. The semiconductor circuit 40 causes the capacitor element CE33 of the basic circuit 405 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 405 is output.

Since the 6 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<5> becomes a low level, and the XBL signal input to the terminal XBL<5> becomes a high level. The semiconductor circuit 40 causes the capacitor element CE33 of the basic circuit 406 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 406 is output.

Since the 7 bits of the input pattern P1 are logic "1", the BL signal input to the terminal BL<6> becomes high level, and the XBL signal input to the terminal XBL<6> becomes low level. The semiconductor circuit 40 causes the capacitor element CE31 of the basic circuit 407 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE31 of the basic circuit 407 is output.

Since the 8 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<7> becomes a low level, and the XBL signal input to the terminal XBL<7> becomes a high level. The memory element ME33 of the basic circuit 408 is not performing a write operation. Therefore, the semiconductor circuit 40 does not cause the capacitor element CE33 of the basic circuit 408 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 408 is not output.

Since the 9 bits of the input pattern P1 are logic "0", the BL signal input to the terminal BL<8> becomes a low level, and the XBL signal input to the terminal XBL<8> becomes a high level. The memory element ME33 of the basic circuit 409 is not performing a write operation. Therefore, the semiconductor circuit 40 does not cause the capacitor element CE33 of the basic circuit 409 to perform a charge storage operation. At the terminal Y, a Y signal having a voltage value corresponding to the capacitance value of the capacitor C201 of the capacitor element CE33 of the basic circuit 409 is not output.

As described above, when the semiconductor circuit 40 compares the positive pattern and the input pattern P5 and performs pattern matching, the voltage value of the Y signal output from the terminal Y of the semiconductor circuit 40 is , 403, 405, 406, and 407. The voltage value is "II" in FIGS. 5 and 6.

Although the description is omitted, when the semiconductor circuit 40 compares the positive pattern and the input pattern P13 and performs pattern matching, the voltage value of the Y signal output from the terminal Y of the semiconductor circuit 40 is equal to that of the basic circuit 401. This is the sum of the voltage values of the Y signals output from each terminal Y of 409 to 409. The voltage value is "I" in FIGS. 5 and 6.

(Effects of semiconductor circuits)
As described above, when the semiconductor circuit 40 compares the normal pattern with each of the input patterns P1, P5, and P13 and performs pattern matching, if the normal pattern and the input pattern P1 are compared, the semiconductor circuit 40 The voltage value of the Y signal output from the terminal Y is the sum of the voltage values of the Y signals output from each terminal Y of the basic circuits 401, 402, 405, and 406. Note that when comparing the normal pattern and the input pattern P1, 1 bit, 2 bits, 5 bits, and 6 bits match. That is, the number of matches is four.

In addition, when comparing the positive pattern and the input pattern P5, the voltage value of the Y signal output from the terminal Y of the semiconductor circuit 40 is This is the sum of the voltage values of the output Y signals. Note that when comparing the correct pattern and the input pattern P5, 1 bits match each other, 2 bits match each other, 3 bits match each other, 5 bits match each other, 6 bits match each other, and 7 bits match each other. That is, the number of matches is 6.

Furthermore, when comparing the positive pattern and the input pattern P13, the voltage value of the Y signal output from the terminal Y of the semiconductor circuit 40 is the voltage value of the Y signal output from each terminal Y of the basic circuits 401 to 409. is the sum of In addition, when comparing the correct pattern and input pattern P13, 1 bit to each other, 2 bits to each other, 3 bits to each other, 4 bits to each other, 5 bits to each other, 6 bits to each other, 7 bits to each other, 8 bits to each other, 9 bits to each other , that is, all bits match. That is, the number of matches is nine.

As shown in FIG. 6, the magnitude relationship between voltage value "I", voltage value "II", and voltage value "III" is voltage value "III" < voltage value "II" < voltage value "I". Here, as shown in FIG. 6, when the threshold value T is set, the voltage values exceeding the threshold value T become the voltage value "II" and the voltage value "I". When a Y signal with a voltage value exceeding the threshold T is output from the terminal Y of the semiconductor circuit 40, the determination circuit 41 of FIG. > is determined to match the correct pattern. On the other hand, the determination circuit 41 in FIG. :8> is determined not to match the normal pattern.

That is, in the examples of FIGS. 5 and 6, the determination circuit 41 determines that the input patterns P5, P9, P13, P14, P15, and P17 match the correct pattern. On the other hand, the determination circuit 41 determines that the input patterns P1, P2, P3, P4, P6, P7, P8, P10, P11, P12, and P16 do not match the normal pattern.

Here, among the input patterns P5, P9, P13, P14, P15, and P17 that are determined by the determination circuit 41 to match the correct pattern, only the input patterns P13 and P17 accurately match. On the other hand, the number of matches for input patterns P5, P9, P14, and P15 with the normal pattern is "6", "7", "7", and "7", respectively. That is, as described above, even if all the bits of the input pattern P and the input pattern P do not match, the semiconductor circuit 40 determines that the input pattern P matches the input pattern if the number of matches exceeds a certain percentage. Note that in the above example, the certain ratio is 5/9.

In this way, the semiconductor circuit 40 can perform pattern matching in an ambiguous manner.

In the above description, it is assumed that the basic circuit 30 of FIG. 3 uses the memory elements ME31 and ME33 and the capacitor elements CE31 and CE33, and the basic circuit 30 of FIG. It was decided not to do so. Furthermore, the capacitance values of the capacitors C201 of the capacitor elements CE31 and CE33 were the same.

However, the first embodiment is not limited to this. For example, the memory elements ME32 and ME34 and the capacitor elements CE32 and CE34 may be used, but the memory elements ME31 and ME33 and the capacitor elements CE31 and CE33 may not be used. Furthermore, the memory elements ME31 to ME34 and the capacitor elements CE31 to CE34 may be used, or the memory elements ME31 to ME34 and the capacitor elements CE31 to CE34 may not be used. Furthermore, in each of the above examples, the capacitance values of the capacitors C201 of the capacitor elements CE31 to CE33 may be different from each other.

[Embodiment 2]
Embodiment 2 of the present invention will be described below with reference to the drawings. For convenience of explanation, members having the same functions as those described in Embodiment 1 will be denoted by the same reference numerals, and the description thereof will not be repeated.

FIG. 7 is a schematic configuration diagram of a basic circuit 70 according to the second embodiment. As shown in FIG. 7, the basic circuit 70 includes memory elements B11, B21, B31, and B41, memory elements B12 to B14, B22 to B24, B32 to B34, and B42 to B44 (first memory elements), and n-type MOS transistors. N11-1, N11-2, N21-1, N21-2, N31-1, N31-2, N41-1, N41-2, and n-type MOS transistors N12 to N14, N22 to N24, N32 to N34, N42 ~N44 (first transistor), and capacitors C11~C13, C21~C23, C31~C33, and C41~C43 (first capacitors).

Further, in FIG. 7, BL, XBL, WLS, WL2, WL1, WL0, and Y represent terminal names, respectively. Below, the input signal from the terminal BL is the BL signal, the input signal from the terminal XBL is the XBL signal, the input signal from the terminal WLS is the WLS signal, the input signal from the terminal WL2 is the WL2 signal, and the input signal from the terminal WL1 is the WL1 signal. The input signal from the terminal WL0 is called the WL0 signal, and the output signal from the terminal Y is called the Y signal.

FIG. 8 is a schematic configuration diagram of the memory element B according to the second embodiment. As shown in FIG. 8, the memory element B includes n-type MOS transistors N101 and N102 and CMOS inverters IN102 and IN102.

Further, in FIG. 8, BL, XBL, WLS, WL2, WL1, WL0, IB, and XB represent terminal names, respectively. Below, the input signal from the terminal BL is the BL signal, the input signal from the terminal XBL is the XBL signal, the input signal from the terminal WLS is the WLS signal, the input signal from the terminal WL2 is the WL2 signal, and the input signal from the terminal WL1 is the WL1 signal. The input signal from the terminal WL0 is called the WL0 signal, the output signal from the terminal IB is called the IB signal, and the output signal from the terminal XB is called the XB signal.

Note that the configurations of memory elements B11 to B14, B21 to B24, B31 to B34, and B41 to B44 in FIG. 7 are the same as the configuration of memory element B in FIG. 8.

The semiconductor circuit according to the second embodiment has a configuration in which each of the basic circuits 401 to 408 in the semiconductor circuit 40 of the first embodiment is replaced with the basic circuit 70 of FIG. 7. The memory element B in FIG. 8 and the basic circuit 70 in FIG. 7 will be described below in this order.

(Configuration of memory element)
In FIG. 8, the output of COMS inverter IN101 is connected to terminal IB. The output of CMS inverter IN102 is connected to terminal XB. The output of CMOS inverter IN101 is connected to the input of CMOS inverter IN102. Further, the output of the CMOS inverter IN102 is connected to the input of the CMOS inverter IN101. CMOS inverter IN101 and CMOS inverter IN102 constitute a so-called latch circuit.

The source of the n-type MOS transistor N101 is connected to the terminal XBL, and the drain thereof is connected to the input of the CMOS inverter IN101. Further, the source of the n-type MOS transistor N102 is connected to the terminal BL, and the drain thereof is connected to the input of the CMOS inverter IN102. Each gate of the n-type MOS transistor N101 and the n-type MOS transistor N102 is connected to the terminal WLS, the terminal WL2, the terminal WL1, or the terminal WL0.

Normally, the BL signal input from the terminal BL and the XBL signal input from the terminal XBL are inverses of each other, that is, complementary, when their potentials are viewed as logical signals. Further, the logic signal levels of the output of the CMOS inverter IN101 and the output of the CMOS inverter IN102 are also complementary in the steady state. That is, if one is at high level, the other is at low level. For example, when the output of CMOS inverter IN101 is low level and the output of CMOS inverter IN102 is high level, it is assumed that logic "1" is stored, and vice versa, logic "0" is stored. has been decided.

The n-type MOS transistor N101 and the n-type MOS transistor N102 are used as write control transistors when writing the BL signal and the XBL signal to the storage element B.

Note that n-type MOS transistor N101 and n-type MOS transistor N102 in FIG. 8 correspond to n-type MOS transistor N101 and n-type MOS transistor N102 in FIG. 1, respectively. Further, CMOS inverter IN101 and CMOS inverter IN102 in FIG. 8 correspond to CMOS inverter IN1 and CMOS inverter IN2 in FIG. 1, respectively. However, in FIG. 8, the output of CMOS inverter IN101 is connected to terminal IB, and the output of CMOS inverter IN102 is connected to terminal XB.

(Operation of memory element)
First, the operations of memory elements B11, B21, B31, and B41 in FIG. 7 will be described. Note that when the memory elements B11, B21, B31, and B41 are collectively referred to as the memory element B1.

First, when the memory element B1 writes a high level to the memory element B1, a high level is input to the terminal BL, and the BL signal becomes a high level. On the other hand, a low level is input to the terminal XBL, and the XBL signal becomes low level.

When the WLS signal input to the terminal WLS becomes high level, both the n-type MOS transistor N101 and the n-type MOS transistor N102 are turned on. By turning on the n-type MOS transistor N101, the XBL signal is input to the CMOS inverter IN101. By turning on the n-type MOS transistor N102, the BL signal is input to the CMOS inverter IN102.

The CMOS inverter IN101 inverts the low level of the input XBL signal to a high level, and inputs the high level to the CMOS inverter IN102. On the other hand, the CMOS inverter IN102 inverts the high level of the input XBL signal to a low level, and inputs the low level to the CMOS inverter IN101.

The output of the CMOS inverter IN101 maintains a high level, while the output of the CMOS inverter IN102 maintains a low level. Terminal IB is connected to the output of CMOS inverter IN101. The IB signal output from the terminal IB becomes high level. Terminal XB is connected to the output of CMOS inverter IN102. The XB signal output from the terminal XB becomes low level.

On the other hand, when the memory element B1 writes a low level to the memory element B1, the low level is input to the terminal BL, and the BL signal becomes low level. On the other hand, a high level is input to the terminal XBL, and the XBL signal becomes high level.

When the WLS signal input to the terminal WLS becomes high level, both the n-type MOS transistor N101 and the n-type MOS transistor N102 are turned on. By turning on the n-type MOS transistor N101, the XBL signal is input to the CMOS inverter IN101. By turning on the n-type MOS transistor N102, the BL signal is input to the CMOS inverter IN102.

The CMOS inverter IN101 inverts the high level of the input XBL signal to a low level, and inputs the low level to the CMOS inverter IN102. On the other hand, the CMOS inverter IN102 inverts the low level of the input XBL signal to a high level, and inputs the high level to the CMOS inverter IN101.

The output of the CMOS inverter IN101 maintains a low level, while the output of the CMOS inverter IN102 maintains a high level. The IB signal output from the terminal IB becomes low level. The XB signal output from the terminal XB becomes high level.

When the WLS signal input to the terminal WLS becomes low level, both the n-type MOS transistor N101 and the n-type MOS transistor N102 are turned off. Therefore, the memory element B1 retains the written high level or low level. The IB signal, which is the output of the inverter IN101, is output from the terminal IB. The IB signal becomes the high level or low level written in the storage element B1. On the other hand, the XB signal, which is the output of the inverter IN102, is output from the terminal XB. The XB signal becomes a low level or high level, which is the inversion of the high level or low level written in the storage element B1.

Next, the operations of the memory elements B12 to B14, B22 to B24, B32 to B34, and B42 to B44 in FIG. 7 will be explained. When the memory elements B12 to B14, B22 to B24, B32 to B34, and B42 to B44 are collectively referred to as memory element B2.

The operation of memory element B2 differs from the operation of memory element B1 in that (i) only a high level (first signal) is written to memory element B2, and (ii) the XB signal is transmitted from terminal XB. This is the point where it is not output. Other than the above two points, there is no difference between the operation of the memory element B2 and the operation of the memory element B1, so a detailed explanation of the operation of the memory element B2 will be omitted.

Note that in the above explanation regarding the operation of the memory element B1, if the terminal WLS is read as the terminal WL2 and the WLS signal is read as the WL2 signal, the explanation will be on the operations of the memory elements B12, B22, B32, and B42. Furthermore, in the above explanation regarding the operation of the memory element B1, if the terminal WLS is read as the terminal WL1 and the WLS signal is read as the WL1 signal, the explanation will be made on the operations of the memory elements B13, B23, B33, and B43. Furthermore, in the above explanation regarding the operation of the memory element B1, if the terminal WLS is read as the terminal WL0 and the WLS signal is read as the WL0 signal, the explanation will be on the operations of the memory elements B14, B24, B34, and B44.

(Basic circuit configuration)
First, the connection configuration of memory elements B11 to B14, n-type MOS transistors N11-1, N11-2, N12 to N14, and capacitors C11 to C13 will be described. Hereinafter, this connection configuration will be referred to as connection configuration 1.

The drain of the n-type MOS transistor N11-1 is connected to the terminal XBL, and the drain of the n-type MOS transistor N11-2 is connected to the terminal BL. The upper electrodes of capacitors C11, C12, and C13 are connected to the source of n-type MOS transistor N11-1, and the upper electrodes of capacitors C11, C12, and C13 are connected to the source of n-type MOS transistor N11-2. The lower electrodes of capacitors C11, C12, and C13 are connected to the drains of n-type MOS transistors N12, N13, and N14, respectively. Each source of n-type MOS transistors N12, N13, and N14 is connected to terminal Y.

If the IB signal output from the storage element B11 is at a high level and the XB signal is at a low level, the n-type MOS transistor N11-1 is turned on and the n-type MOS transistor N11-2 is turned off. In this case, each upper electrode of capacitors C11, C12, and C13 is connected to terminal XBL via an n-type MOS transistor N11-1. On the other hand, if the IB signal output from the storage element B11 is at a low level and the XB signal is at a high level, the n-type MOS transistor N11-1 is turned off and the n-type MOS transistor N11-2 is turned on. In this case, each upper electrode of capacitors C11, C12, and C13 is connected to terminal BL via an n-type MOS transistor N11-2.

If each IB signal output from the storage elements B12 to B14 is at a high level, the n-type MOS transistors N12 to N14 are turned on. In this case, the lower electrodes of capacitors C11, C12, and C13 are connected to terminal Y via respective n-type MOS transistors N12 to N14.

The connection configuration of memory elements B21 to B24, n-type MOS transistors N21-1, N21-2, N22 to N24, and capacitors C21 to C23 is the same as that of memory elements B11 to B14, n-type MOS transistor N11 in connection configuration 1 described above. -1, N11-2, N12 to N14, and capacitors C11 to C13, respectively, to the corresponding memory elements B21 to B24, n-type MOS transistors N21-1, N21-2, N22 to N24, and capacitors C21 to C23, respectively. This is the replaced configuration. Furthermore, the connection configuration of the storage elements B31 to B34, the n-type MOS transistors N31-1, N31-2, N32 to N34, and the capacitors C31 to C33 is the same as that of the storage elements B11 to B14, the n-type MOS transistors Transistors N11-1, N11-2, N12 to N14 and capacitors C11 to C13 are connected to corresponding memory elements B31 to B34, n-type MOS transistors N31-1, N31-2, N32 to N34, and capacitors C31 to C33, respectively. This is a configuration in which each has been replaced. Furthermore, the connection configuration of the storage elements B41 to B44, the n-type MOS transistors N41-1, N41-2, N42 to N44, and the capacitors C41 to C43 is the same as that of the storage elements B11 to B14, the n-type MOS transistors Transistors N11-1, N11-2, N12 to N14, and capacitors C11 to C13 are connected to corresponding storage elements B41 to B44, n-type MOS transistors N41-1, N41-2, N42 to N44, and capacitors C41 to C43, respectively. This is a configuration in which each has been replaced.

(Basic circuit operation)
The operation of the basic circuit 70 will be explained focusing on the above-mentioned connection configuration 1. Note that the operation of the basic circuit 70 when paying attention to the other connection configurations described above is as follows. This is an operation in which ~N14 is replaced with a corresponding memory element, capacitor, and n-type MOS transistor.

When the XB signal output from the storage element B11 is at a high level and the IB signal is at a low level, the upper electrodes of the capacitors C11 to C13 are connected via the n-type MOS transistor N11-1. On the other hand, when the XB signal output from the storage element B11 is at a low level and the IB signal is at a high level, the upper electrodes of the capacitors C11 to C13 are connected via the n-type MOS transistor N11-2.

Further, the lower electrodes of the capacitors C11 to C13 are connected to the terminal Y by turning on the n-type MOS transistors N12 to N14 whose drains are connected to the respective lower electrodes. When a high level is written in the memory elements B12 to B14 and the IB signal becomes high level, each of the n-type MOS transistors N12 to N14 is turned on.

As described above, the basic circuit 70 connects each upper electrode of the capacitors C11 to C13 to the terminal BL when a high level is written to the memory element B11. On the other hand, when a low level is written to the memory element B11, the basic circuit 70 connects each upper electrode of the capacitors C11 to C13 to the terminal XBL.

Then, the basic circuit 70 connects the lower electrode of the capacitor C11 to the terminal Y when a high level is written to the memory element B12. The basic circuit 70 connects the lower electrode of the capacitor C12 to the terminal Y when a high level is written to the memory element B13. The basic circuit 70 connects the lower electrode of the capacitor C13 to the terminal Y when a high level is written to the memory element B14. That is, the basic circuit 70 connects the capacitor in which a high level is written in the corresponding storage element to the terminal BL or the terminal XBL.

Here, in the case where the upper electrodes of the capacitors C11 to C13 are connected to the terminal BL, the combinations of capacitors connected to the terminal BL are as follows.
・Capacitors C11, C12 and C13,
・Capacitors C11 and C12,
・Capacitors C11 and C13,
・Capacitors C12 and C13,
・Capacitor C11 only,
・Capacitor C12 only,
・Capacitor C13 only,
·none.

Here, if the capacitance ratio of the capacitors C11 to C13 is 4:2:1, when the BL signal input to the terminal BL is at a high level, the voltage value ratio of the Y signal output at the terminal Y is 7: 6:5:4:3:2:1:0. That is, when the BL signal input to the terminal BL is at a high level, there are nine voltage values of the Y signal output from the terminal Y. In addition, the relationship between each of the above-mentioned voltage value ratios and each of the above-mentioned combinations is as follows.
・Capacitors C11, C12 and C13:7,
・Capacitors C11 and C12:6,
・Capacitors C11 and C13:5,
・Capacitors C12 and C13: 4,
・Capacitor C11 only: 3,
・Capacitor C12 only: 2,
・Capacitor C13 only: 1,
・None: 0.

Similarly, even if the upper electrodes of capacitors C11 to C13 are connected to terminal XBL, if the capacitance ratio of capacitors C11 to C13 is 4:2:1, the XBL signal input to terminal XBL will be at high level. In this case, there are eight voltage values of the Y signal output at the terminal Y.

[Effects of the present invention]
The present invention is a circuit configuration method for ambiguous pattern matching, which is a basic operation of AI technology. The present invention is a technology that achieves both the degree of calculation precision necessary for AI technology and miniaturization. The present invention is characterized in that it can be made smaller and more power efficient than a completely digital circuit, and weight control is more stable and easier than a completely analog circuit.

The present invention is not limited to the embodiments described above, and can be modified in various ways within the scope of the claims, and can be implemented by appropriately combining technical means disclosed in different embodiments. The form is also included within the technical scope of the present invention.

10, ME31, ME32, ME33, ME34, B, B11 to B14, B21 to B24, B31 to B34, B41 to B44 Memory element 20, CE31, CE32, CE33, CE34 Capacitor element 30, 401, 402, 403, 404, 405, 406, 407, 408, 409, 70 Basic circuit 40 Semiconductor circuit 41 Judgment circuit C201, C11 to C13, C21 to C23, C31 to C33, C41 to C43 Capacitor

Claims (7)

A pair of terminals BL and terminals XBL,
Terminal Y and
a first capacitor whose upper electrode is connected to the terminal BL;
a second capacitor whose upper electrode is connected to the terminal XBL;
a first transistor connected between the lower electrode of the first capacitor and the terminal Y;
a second transistor connected between the lower electrode of the second capacitor and the terminal Y;
a first storage element capable of storing a first signal for turning on the first transistor;
a second storage element capable of storing a second signal for turning on the second transistor;
When the first storage element stores the first signal, if the BL signal input from the terminal BL is at a predetermined level, the terminal Y receives a Y signal with a voltage value corresponding to the capacitance value of the first capacitor. Outputs
When the second storage element stores the second signal, if the XBL signal input from the terminal A semiconductor circuit characterized by outputting. a plurality of the first capacitors;
a plurality of the first transistors;
and a plurality of the first memory elements,
2. The semiconductor circuit according to claim 1, wherein the plurality of first capacitors are connected in parallel between the terminal BL and the terminal Y. a plurality of the second capacitors;
a plurality of the second transistors;
and a plurality of the second memory elements,
3. The semiconductor circuit according to claim 1, wherein the plurality of second capacitors are connected in parallel between the terminal XBL and the terminal Y. Each capacitance value of the plurality of first capacitors is different from each other,
4. The semiconductor circuit according to claim 3, wherein each of the plurality of second capacitors has a different capacitance value. A pair of terminals BL and terminals XBL,
Terminal Y and
a first capacitor whose upper electrode can be connected to the terminal BL or the terminal XBL;
a first transistor connected between the lower electrode of the first capacitor and the terminal Y;
a first storage element capable of storing a first signal for turning on the first transistor;
When the first storage element stores the first signal, if the signal input from the terminal BL or XBL to which the upper electrode of the first capacitor is connected is at a predetermined level, A semiconductor circuit characterized in that the terminal Y outputs a Y signal having a voltage value corresponding to a capacitance value of the first capacitor. a plurality of the first capacitors;
a plurality of the first transistors;
and a plurality of the first memory elements,
The plurality of first capacitors are connected in parallel between one of the terminals BL or XBL to which the upper electrode of the first capacitor is connected and the terminal Y. The semiconductor circuit according to claim 5. 7. The semiconductor circuit according to claim 6, wherein each of the plurality of first capacitors has a different capacitance value.

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