JP4101781B2 - Semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device suitable for application to devices and devices that require low power consumption, and particularly to a semiconductor integrated circuit device that operates at a low voltage.

  In recent years, static RAM (Random Access Memory) used for IC (Integrated Circuit) cards and portable devices is required to operate at a low voltage in terms of low power consumption and reliability. As a technique for operating a static RAM at a low voltage, a circuit using a P-type MOS (Metal Oxide Semiconductor) type field effect transistor (hereinafter referred to as “MOSFET”) as a load element in each memory cell constituting the static RAM. It has been proposed (see, for example, Non-Patent Document 1). Since the P-type MOSFET is either conductive or non-conductive, the P-type MOSFET is not easily affected by noise and voltage fluctuation. Since an N-type MOSFET is used as a driving transistor for the memory cell, the memory cell is formed by a CMOS (Complementary MOS) transistor structure together with the P-type MOSFET (hereinafter referred to as “complete CMOS memory cell”). .

  The structure of the memory cell described in Non-Patent Document 1 is shown in FIG. The storage unit for storing information includes P-type MOSFETs (hereinafter referred to as “load PMOS”) 1 and 2 as load elements, and N-type MOSFETs (hereinafter referred to as “drive NMOS”) 3 and 4 as drive elements. The bit line 18 and the bit line 19 having the opposite polarity are connected to each other through N-type MOSFETs (hereinafter referred to as “transfer NMOSs”) 5 and 6 serving as transfer elements. The gate electrodes of the transfer NMOSs 5 and 6 are connected by a word line 22. Further, the substrate electrodes (wafers) 11 to 14 of the transfer NMOSs 5 and 6 and the drive NMOSs 3 and 4 are connected to the ground terminal 9 (potential VSS), and the substrate electrodes 15 and 16 of the load PMOSs 1 and 2 are power supply terminals. 8 (voltage VDD). Further, the thresholds of all the MOSFETs 1 to 6 are set to be relatively high, for example, about 0.7 V so that leakage current does not flow during inactive and standby (hereinafter, such a threshold voltage is set to “high”. Called threshold voltage).

  The static RAM is constituted by a memory array in which such a large number of memory cells are arranged in a matrix. Note that when a power supply voltage is supplied to the memory array and writing and reading are performed in some memory cells, writing and reading are not performed in other memory cells. The active state means that the power supply voltage is supplied but the entire memory array is not written and read, and is called a standby state.

  In reading data from the memory cell, the pair of bit lines 18 and 19 (signal lines to which data of opposite polarities are supplied) are once precharged to the power supply voltage VDD, and the word line 22 is set to the power supply voltage VDD. By making the transfer NMOSs 5 and 6 conductive, the precharged bit lines 18 and 19 are discharged through either the drive NMOS 3 and the transfer NMOS 5 or the drive NMOS 4 and the transfer NMOS 6. Is called. Data writing is performed by setting the word line 22 to the power supply voltage VDD, turning on the transfer NMOSs 5 and 6, and setting the state of the storage unit according to the data of the bit lines 18 and 19.

  However, when the power supply voltage VDD is set to a low voltage of about 1 V, for example, the drive capability of the drive NMOSs 3 and 4 and the transfer NMOSs 5 and 6 having a high threshold voltage is drastically reduced and the drain-source resistance is increased. There is a problem that the reading speed is remarkably lowered.

  As a countermeasure against the above problem, a circuit for applying a negative voltage to the source electrodes of the driving NMOSs 3 and 4 at the time of reading has been proposed (for example, see Non-Patent Document 2).

  The structure of the memory cell described in Non-Patent Document 2 is shown in FIG. The circuit configuration of the memory cell is almost the same as the configuration shown in FIG. 14 except that the source electrodes of the driving NMOSs 3 and 4 are connected to the source line 23 without being connected to the ground terminal 9. The source electrode is driven independently. The source line 23 is individually provided for each row. Also in this circuit, all the MOSFETs 1 to 6 of the memory cell have a high threshold voltage so that a leak current does not flow during inactive and standby.

  Reading of data from the memory cell is performed by applying a negative voltage (for example, −0.5 V) to the source line 23 of the driving NMOSs 3 and 4 simultaneously with the word lines 18 and 19 being set to the power supply voltage VDD. As a result, the driving capabilities of the driving NMOSs 3 and 4 and the transfer NMOSs 5 and 6 are increased, and the charge of the bit line precharged to the power supply voltage VDD is quickly discharged, enabling high-speed operation. That is, high-speed reading can be realized by using a low voltage power supply of about 1V.

  However, in such a conventional circuit, a negative power source is separately required, and a higher voltage than the power source voltage is applied to the driving NMOSs 3 and 4. Therefore, a low-voltage high-speed operation MOSFET element with a thin gate oxide film is employed. However, there was a problem that it was difficult in terms of reliability.

US literature “1990 Symposium on VLSI Circuits”, pages 53-54

1995 US Symposium on VLSI Circuits, pp. 25-26

  In order to operate the MOSFET at a high speed with a low voltage, a method of lowering the threshold voltage to around 0.2V, for example, can be considered. However, since the leakage current increases by an order of magnitude when the threshold voltage is lowered by 0.1 V, there is a problem in that power consumption increases due to the leakage current when applied to a memory array having a large number of transistors.

  SUMMARY OF THE INVENTION The main object of the present invention is to provide a novel semiconductor integrated circuit device comprising a static RAM capable of solving the above-mentioned problems of the prior art and ensuring a high reading speed using a low voltage power supply. .

  Another object of the present invention is to provide a novel semiconductor integrated circuit device comprising a logic circuit that can ensure high-speed operation using a low-voltage power supply.

  The object of the present invention is to maintain the source line at the ground potential when the memory cells in the same row are selected to perform reading, and to the same source line during inactive and standby when reading / writing is not selected. It is possible to effectively solve the problem by providing a switch circuit for keeping the voltage at the intermediate potential between the power supply potential and the ground potential for each source line. By adopting such means, the leakage current can be kept low by biasing the MOSFET's gate-source voltage to be lowered by the voltage due to the intermediate potential during inactive and standby.

  Therefore, a low threshold voltage whose threshold voltage is less than 1/2 of the power supply voltage (hereinafter referred to as “low threshold voltage”), for example, a MOSFET having a threshold voltage in the vicinity of 0.2 V can be used for driving and transferring. A low voltage power supply of about 1V can be used. In addition, since the source electrode is grounded at the time of reading, a power supply voltage is applied between the drain and the source, and high driving capability can be maintained. Therefore, it is possible to avoid a decrease in reading speed. Further, as an intermediate potential, for example, a resistor can be connected between the source line and the ground terminal during inactive and standby, and a voltage generated by a current flowing through the resistor can be used. Therefore, a new power supply is provided. Inconvenience is avoided.

  At the time of writing, it is desirable to keep the source line at the same intermediate potential as that at the time of inactivation and standby. Since the memory state is reached at a low current as the operating current of the MOSFET decreases, the writing speed is improved.

  Note that one of the driving NMOSs of the memory cell storage unit and the load PMOS connected thereto form a CMOS inverter, and the two inverters form a positive feedback loop.

  The inverter is a logic circuit having the simplest logic function. The N-type MOSFET portion is composed of a plurality of N-type MOSFETs, and the P-type MOSFET portions are the same as the N-type P-type MOSFETs. If these are configured so as to have complementary logic functions, other general CMOS logic circuits can be formed.

  In the logic circuit, a single N-type MOSFET (in the case of an inverter) or a plurality of N-type MOSFETs forms a ground-side current path, and a single P-type MOSFET (in the case of an inverter) or a plurality of P-type MOSFETs A power source side current path is formed. One terminal of the ground-side current path is connected to the output terminal, and the other terminal is connected to the ground terminal. One terminal of the power supply side current path is connected to the output terminal, and the other terminal is connected to the power supply terminal. The logic circuit operates such that when one current path is turned on by an input signal, the other current path is turned off. Further, several logic circuits are connected to each other or a single logic circuit forms a semiconductor integrated circuit device having a desired logic.

  Another feature of the present invention resides in that a circuit similar to the switch circuit is applied to a semiconductor integrated circuit device including at least one logic circuit. That is, in the semiconductor integrated circuit device of the present invention, the other terminal of the ground-side current path (first current path) is connected not by the ground terminal but by the ground-side source line (first source line). A logic circuit in which the other terminal of the path (second current path) is connected to the power source side source line (second source line) instead of the power source terminal, and the ground side and the power source side source line are respectively connected to the ground side. A switch circuit (first switch circuit) and a power supply side switch circuit (second switch circuit) are connected. When the logic circuit is selected to operate, the ground-side and power-side switch circuits maintain the ground-side and power-side source lines at the ground potential and the power-supply potential, respectively, and when they are not selected, The power source side source line is operated to maintain a separate intermediate potential between the power source potential and the ground potential.

  Due to such a characteristic point, as in the case of the static RAM, the leakage current is suppressed low by biasing the gate-source voltage of the MOSFET by a voltage corresponding to the intermediate potential during standby. Therefore, it is possible to use a MOSFET with a low threshold voltage, and it is possible to employ a low voltage power supply of about 1V.

  In addition, since the source electrode is grounded during operation, a power supply voltage is applied between the drain and the source, and high drive capability can be maintained. Therefore, it is possible to avoid a decrease in operating speed. In addition, as an intermediate potential, for example, a resistor can be connected between each source line and the ground terminal during standby, and a voltage generated by a current flowing through the resistor can be used. Avoided.

  According to the present invention, in the static RAM, the ground potential is applied to the source electrode of the driving NMOS at the time of reading, and the intermediate potential between the power supply potential and the ground potential is applied at the time of inactivation and standby. In addition, the leakage current during standby can be reduced, and a low threshold voltage MOSFET and a low voltage power supply can be employed. Also, in the logic circuit, the ground potential and the power supply potential are applied to the source electrodes of the N-type and P-type MOSFETs, respectively, during operation, and the respective intermediate potentials of the power supply potential and the ground potential are applied during standby. Leakage current can be reduced, and a low threshold voltage MOSFET and a low voltage power supply can be employed. As a result, a large-scale semiconductor integrated circuit device with high speed and low power consumption can be realized.

  In addition, since only a ground potential or an intermediate potential is applied to the substrate electrode and the source electrode, a voltage higher than the power supply voltage is not applied to the gate oxide film of the MOSFET. Can be adopted.

  Note that variations in threshold voltage cannot be avoided due to variations in the manufacturing process, but the allowable range of the threshold voltage is expanded by reducing the leakage current. Therefore, the present invention is further effective in an integrated circuit having variations in threshold voltage. It becomes the target.

  Hereinafter, a semiconductor integrated circuit device according to the present invention will be described in more detail with reference to some embodiments shown in the drawings. In addition, the same symbol in FIGS. 1-15 shall represent the same thing or a similar thing.

<Example 1>
The present invention is applied to a static RAM comprising a complete CMOS type memory cell. In FIG. 1, 17 is a memory array of complete CMOS memory cells arranged in n rows and m columns, 7 is a memory cell in the first row and first column in the memory array 17, and 33 is a source line in the first row. Reference numeral 30 denotes a switch circuit connected to 23, and 30 denotes a resistor connected between the switch circuit 33 and the ground terminal 9.

  Although not explicitly shown in FIG. 1, the word line 22, the bit lines 18, 19 and the source line 23 are arranged as follows. The word line 22 is provided for each row, extends in the row direction of the memory array 17, and is commonly connected to the gate electrodes of the transfer NMOSs 5 and 6 of the memory cells 7 in the same row. The bit lines 18 and 19 are provided for each column and extend in the column direction, and are commonly connected to the transfer NMOSs 5 and 6 of the memory cells in the same column. The source line 23 is provided for each row. Therefore, the switch circuit 33 is provided for each row. By providing the word line 22 and the source line 23 for each row, the read / write operation and inactivation of the memory cell 7 are selected in units of rows. On the other hand, all the switch circuits in each row are connected to the resistor 30 in common.

  Next, in FIG. 1, connection points between the driving NMOS 3 and the load PMOS 1 and connection points between the driving NMOS 4 and the load PMOS 2 are shown as storage nodes 20 and 21, respectively. The storage nodes 20 and 21 store high level (almost power supply potential, hereinafter referred to as “H”) or low level information (approximately ground potential, hereinafter referred to as “L”). The

  In each memory cell having such a structure, a low threshold voltage N-type MOSFET is used for the driving NMOSs 3 and 4 and the transfer NMOSs 5 and 6, and a high threshold voltage P-type MOSFET is used for the load PMOS. The voltage VDD was 1.0V.

  The switch circuit 33 will be described in detail later. The switch circuit 33 connects the source line 23 to the ground terminal 9 when the bank is in an operating state, and when the switch circuit 33 is in an inactive state and the entire state is in a standby state. It operates so as to connect the source line 23 to the resistor 30. When connected to the resistor 30, a leakage current of all the memory cells in the memory array 17 that is inactive or standby is flowing through the resistor 30.

  In the present invention, the potential of the source line 23 caused by the leakage current flowing through the resistor 30 becomes an intermediate potential VMD between the power supply voltage VDD and the ground potential VSS. In this example, the intermediate potential VMD was set to 0.5V. As will be described later, the resistor 30 can be a voltage source circuit or a current source circuit. In either case, a predetermined intermediate potential VMD can be obtained.

  FIG. 2 shows operation waveforms at the time of reading data, inactive and in standby according to this embodiment. In FIG. 2a, at the time of reading, the word line 22 is set to 'H' when the power supply voltage VDD is applied, and the source line 23 is set to the ground potential. At the time of reading, the bit lines 18 and 19 are once precharged to “H” in advance, and then discharge of one of the bit lines starts, and the potential drops from 1.0V. Further, at the time of inactivation and standby, the word line 22 becomes the ground potential VSS and becomes “L”, and at the same time, the source line 23 becomes the intermediate potential VMD (0.5 V).

  Under such potential setting, the substrate electrodes of the driving NMOSs 3 and 4 and the transfer NMOSs 5 and 6 are fixed to the ground potential as described above. Now, when the storage node 20 stores, for example, “H” information, and therefore the storage node 21 stores “L” information, the driving NMOS 4 is in a conductive state in the inactive state and in the standby state. Therefore, the storage node 21 is equal to the intermediate potential VMD and becomes 0.5V. At this time, since the word line 22 in the inactive state and the standby state is at the ground potential VSS, in the transfer NMOS 6, the potential between the source and the substrate electrode 12 becomes negative (−0.5 V) and the threshold voltage increases. At the same time, the source-gate voltage of the MOSFET becomes negative (−0.5 V). By these two effects, the leakage current of the transfer NMOS 6 is reduced, and the leakage current flowing from the bit line 19 precharged to ‘H’ into the source line 23 is reduced. Further, since the driving NMOS 3 also has a negative voltage between the source and the substrate electrode 13 and the threshold voltage of the driving NMOS 3 is increased, the leakage current flowing from the storage node 20 at the high level to the source line 23 is reduced.

  When the intermediate potential VMD is set to 0.5 V due to the effect of reducing the leakage current described above, the total leakage current of the memory cell 7 is the same as that of the conventional example in the case where the N-type MOSFET having the same threshold voltage as that of this embodiment is adopted. Compared to about an order of magnitude. This is the same as the decrease in leakage current when the threshold voltage of the N-type MOSFET in the memory cell 7 is increased by about 0.1 V in the conventional example. That is, in this embodiment, even if the threshold voltages of the drive NMOSs 3 and 4 and the transfer NMOSs 5 and 6 are designed to be about 0.1 V lower than the conventional example, the leakage current of the memory cell 7 is almost the same as the conventional example. It can be.

  In this embodiment, since the threshold voltages of the driving NMOSs 3 and 4 and the transfer NMOSs 5 and 6 can be lowered as compared with the conventional example, the driving capability of the MOSFET can be increased, and the low voltage and high speed information can be obtained. Reading can be achieved. Specifically, a sense amplifier (not shown) that amplifies the potential difference between the bit line 18 and the bit line 19 by rapidly changing the potential of the bit lines 18 and 19 precharged to “H”. The time to start up can be shortened. FIG. 2a shows how the potential of the bit lines 18 and 19 drops during reading. The potential drops from 1.0V. For comparison, FIG. 2b shows operation waveforms in the case of the conventional example shown in FIG. The power supply voltage is 1.0 V, the threshold voltage of the N-type MOSFET is set to 0.1 V higher than that in the present embodiment, and the leakage current during inactive and standby is the same as in this embodiment. Since the driving capability of the MOSFET decreases as the threshold voltage increases, it is shown that the potential decrease during reading is more gradual than in the present embodiment. Therefore, the time until the sense amplifier is activated is delayed and the reading speed is reduced.

  Next, FIG. 3 shows operation waveforms at the time of data writing in this embodiment. When the storage nodes 20 and 21 of the memory cell 7 are, for example, “H” and “L”, respectively, before writing, the potential difference between the bit lines 18 and 19 is 0.0 V as the ground potential and 1 as the power supply voltage, respectively. The voltage is expanded to 0.0 V and the word line 22 is set to “H” to write “L” and “H” to the storage nodes 20 and 21 in the memory cell, respectively. At this time, the source line 23 is set to an intermediate potential VMD (0.5 V) between the power supply voltage VDD and the ground potential VSS as in the inactive state and the standby state. As a result, the drain-source voltage of the driving NMOS 4 in the conductive state decreases (becomes 0.5 V), and the source-gate voltage becomes negative (-0.5 V), the threshold voltage increases, and the drive Since the conduction current of the NMOS 4 is low, the storage state is reached with a low current, and the storage node 21 changes from 'L' to 'H' at high speed. Accordingly, high-speed writing is possible. Note that as in the case of reading, data can be written with the source line 23 set to the ground potential VSS.

  Next, a circuit for controlling the potentials of the word line 22 and the source line 23 will be described with reference to FIG. For the sake of simplicity, the connection of the substrate electrodes of the MOSFETs is omitted in the figure, but the substrate electrodes of the P-type MOSFETs 1 and 2 are connected to the power supply terminal 8 and the substrate electrodes of the N-type MOSFETs 3 to 6 are grounded as in FIG. Connected to terminal 9. Also, for the sake of simplicity, only one memory cell 7 is shown, but it is arranged in a matrix like FIG. In FIG. 4, 51 is a word / source line driver circuit that controls the source line 23 and controls the potential of the word line 22 including the switch circuit 33, 52 and 53 are inverters that drive the word line 22, and 60 is Nodes 56 and 57, which are connection points of the switch circuit 33 and the resistor 30 and exhibit the intermediate potential VMD, are connected between the node 60 and the source line 23 and operate as switch elements, respectively. , 58 are N-type MOSFETs connected between the source line 23 and the ground terminal 9 and operating as switch elements, 55 is an inverter for driving the P-type MOSFET 57 and the N-type MOSFET 58, and 54 is an N-type MOSFET 56 and an inverter 55. A NAND circuit 66 for driving the word source line driver circuit 51 Address signals to, 67 denotes a write / read control signal.

  The word / source line driver circuit 51 is provided for each row of the memory array 17, and the source lines 23 of all rows are connected to the node 60 via the respective switch circuits 33. The resistor 30 is not limited to this, and can be replaced with the current source circuit shown in FIG. 5a or the voltage source circuit shown in FIG. 5b. In any case, the potential presented by the node 60 is the intermediate potential VMD. The circuit constants are set so that

  In such a word / source line driver circuit 51, when the address signal 66 becomes "H" and the write / control signal 67 becomes "H" for reading selection, the N-type MOSFET 58 becomes conductive, and at the same time, the N-type The MOSFET 56 and the P-type MOSFET 57 are turned off, and the ground potential VSS is supplied to the source line 23. Further, when the address signal 66 becomes “H” and the write / control signal 67 becomes “L” for write selection, the N-type MOSFET 58 becomes non-conductive, and at the same time, the N-type MOSFET 56 and the P-type MOSFET 57 become conductive. The intermediate potential VMD is supplied to the source line 23.

  The intermediate potential VMD of the node 60 is a potential generated by leakage current from all memory cells flowing into the resistor 30. On the other hand, the intermediate potential VMD of the node 60 increases the threshold voltage of the N-type MOSFET in the memory cell 7 and decreases the leakage current. The intermediate potential VMD of the node 60 is determined by a balance between these two phenomena (a phenomenon in which the intermediate potential VMD is generated by the leak current and a phenomenon in which the leak current decreases as the intermediate potential VMD increases). When the resistance 30 is constant, the intermediate potential VMD increases as the threshold voltage of the N-type MOSFET in the memory cell 7 is reduced. As the intermediate potential VMD increases, the potential between the source of the N-type MOSFET and the substrate electrode increases in the negative direction, the substrate bias effect increases, and the reduction rate of the leakage current increases. However, if the intermediate potential VMD becomes too large, the current of the MOSFET in the conductive state decreases and the information stored in the memory cell 7 disappears.

  FIG. 6 shows a simulation result of the average current consumption and the read delay time during the read operation when the threshold voltage of the N-type MOSFET of the memory cell 7 is changed. In the figure, in addition to the case of the present embodiment, the case of the conventional example is shown for comparison.

  FIG. 6A shows that the address signal 66 for starting the word / source line driver circuit 51 is set to the selected state “H”, and then the bit lines 18 and 19 precharged to “H” correspond to the information in the memory cell 7. The average current consumption during read operation (operating frequency is 200 MHz) obtained from the current flowing through the source line 23 of the entire memory array 17 during the time from “H” (1.0 V) to 100 mV drop of the memory cell 7 The simulation is performed by changing the threshold voltage of the N-type MOSFET. It is assumed that only one row is read in one cycle, and the leakage current of the inactive memory cells 7 in the other rows that are not read is included in the consumption current during the read average operation. The 100 mV is a voltage at which the sense amplifier detects a change in potential difference between the bit lines 18 and 19 and starts reading. When the potential difference reaches 100 mV, the sense amplifier operates.

  FIG. 6B shows the time from when the address signal 66 is set to the selected state “H” until the potential difference between the bit lines 18 and 19 precharged to “H” reaches 100 mV according to the information in the memory cell (hereinafter “ The delay time is simulated by changing the threshold voltage of the N-type MOSFET of the memory cell 7.

  As shown in FIG. 6A, in the conventional example, the average current consumption during the read operation starts from around 0.225 V (denoted as 100 in the figure) when the threshold voltage of the N-type MOSFET of the memory cell 7 is decreased. Increases rapidly. This is because when the threshold voltage is lowered, the consumption current 105 due to the leakage current of the memory cell 7 in an inactive state when the threshold voltage is near 0.225 V (if the threshold voltage is reduced by 0.1 V as described above). This is because it has become a magnitude that cannot be ignored with respect to the intrinsic current consumption 104 (which is a constant value regardless of the threshold voltage) consumed by the memory cell 7 that has been read. .

That is, in the conventional example, when the threshold voltage is 0.225 V or less, the average current consumption during the read operation is determined by the power consumption 105 due to the leakage current, and when the threshold voltage is 0.225 V or more, it is required for reading. It depends only on the intrinsic power consumption 104 to be performed. Generally, the lower limit of the allowable threshold voltage is 0.225 V before the operating power consumption suddenly increases. If the threshold voltage variation due to fluctuations in the MOSFET manufacturing process is ± 0.1V, the threshold voltage design target value is 0.325V. Further, the upper limit due to variation in threshold voltage is 0.425V. That is, in the conventional example, the range of the threshold voltage that can be taken due to process variation is 0.225V to 0.425V108. The maximum delay time at this time is 3.5 ns103.
On the other hand, in this embodiment, the threshold voltage varies by ± 0.1 V due to process variations, and the design target of the value of the resistor 30 and the threshold voltage is set so that the maximum average operating current consumption becomes the same value Pmax101 as in the conventional example. Determine the value. In this embodiment, the target value of the threshold voltage design is 0.2V. This is 0.125 V lower than the conventional example, and the high-speed operation of the MOSFET is possible. The range of the threshold voltage that can be taken due to process variation is 0.1V to 0.3V109. As described above, the intermediate potential VMD also fluctuates due to variations in threshold voltage, but the resistor 30 and the threshold voltage are determined so that the maximum value of the intermediate potential VMD does not exceed 0.6V. The reason why the maximum value of the intermediate potential VMD does not exceed 0.6 V is that the power supply voltage is set to 1.0 V, so that the conduction currents of the NMOSs 3 and 4 are reduced and the information stored in the memory cell 7 disappears. This is to prevent it from happening. From the simulation results, the maximum read time 110 is 2.9 ns. Compared to the conventional example, the maximum reading time is improved by about 17% 106.

  In this embodiment, when the threshold voltage becomes a minimum of 0.1V112 due to variations due to process fluctuations, the leak current becomes maximum, so that the intermediate potential VMD becomes the maximum of 0.6V, which is inactive and in standby. The threshold voltage of the N-type MOSFET increases by 0.1 V due to the substrate bias effect. As a result, the maximum leakage current is reduced by about one digit. In addition, since the intermediate potential VMD is maximized, it is conceivable that the discharge time for setting the potential to the ground potential at the time of reading becomes long and the reading time becomes slow (in this embodiment, such a tendency is not seen). Such a tendency appears when the power supply voltage is 1.5V, etc.), but it has been found that this increase in reading time does not pose a problem because the driving capability of the MOSFET is increased by lowering the threshold voltage. .

  On the other hand, when the threshold voltage reaches a maximum of 0.3V111 due to variations due to process variations, the leakage current decreases and the intermediate potential VMD becomes almost 0V. In that case, the driving capability of the MOSFET is lowered and the reading speed is reduced by increasing the threshold voltage. However, since the intermediate potential VMD is almost 0 V, the discharge time for setting the potential to the ground potential at the time of reading is ignored. As a result, it has been found that a decrease in reading speed is not a problem in this method.

  In the general case where the intermediate potential VMD is not applied, the worst value of the operation speed due to the decrease in the driving capability is determined by the upper limit of the threshold voltage variation, while the maximum leakage current is the lower limit of the threshold voltage variation. Determined. In this method, when the threshold voltage varies to the upper limit, the intermediate potential VMD becomes almost 0V, so that the discharge of the intermediate potential hardly affects the worst value of the operation speed. Further, when the threshold voltage varies to the lower limit, the intermediate potential VMD becomes maximum, and this maximum leakage current is greatly reduced. At this time, the time required for discharging the intermediate potential VMD is added to affect the operating speed, but the operating speed that has been reduced does not become worse than the worst operating speed. Therefore, when considering threshold voltage variation, the intermediate potential VMD when the threshold voltage is lowered to the lower limit can be increased until just before the memory cell information is lost without worrying about the operation speed. Therefore, the worst value of the operation speed can be further improved. As is clear from the above description, the present invention is more effective when the variation in the threshold voltage due to the process variation is taken into consideration.

  Next, in the present invention, since a negative voltage is avoided from being applied to the substrate electrode and the source electrode, the gate oxide film is not applied with a voltage higher than the power supply voltage, and the gate oxide film is thinly operated. The high-speed MOSFET can be employed.

  Next, the overall structure of the static RAM to which the present invention is applied is shown in FIG. Memory cells 7 are arranged in n rows and m columns (7-11 to 7-mn), and word / source line driver circuits 51 are arranged in m columns for each row (51-1 to 51-m). Each word / source line driver circuit 51 is supplied with a write / read control signal 67 and a resistor 30 is connected in common. In the figure, reference numerals 150-1 to 150-n denote sense amplifiers that amplify the potential difference between a pair of bit lines (18-1 to 18-n, 19-1 to 19-n). Although not particularly limited, a sense amplifier is provided corresponding to each bit line pair. A sense amplifier control signal 172 for controlling the active state of each sense amplifier is supplied. Reference numerals 155-1 to 155-n denote write driver circuits, which are supplied with a write / read control number 67 and a data signal (not shown) for transmitting data to be written. Reference numerals 160-1 to 160-n are equalizer circuits for precharging each bit line to a predetermined potential, and are controlled by a signal 171. Reference numeral 170 denotes a predecoder, which starts decoding an address in response to the input address control signal 173, and outputs an address signal 66 for each row (66-1 to 66-m). A control circuit 180 receives a write enable signal WE and a clock signal from the outside, and generates control signals 67, 171, 172, and 173.

  FIG. 8 shows operation waveforms of the static RAM shown in FIG. FIG. 8a shows operation waveforms during reading. After the address is input, the read operation is controlled by the clock, and the sense amplifier 150 outputs data during the clock period. That is, the address is decoded by the predecoder 170 at the rising edge of the clock, and becomes the address signal 66. The word / source line driver circuit 51 receives the same address signal and further decodes the signal to set the selected word line 22 to the power supply potential VDD and similarly select the selected source line 23 to the ground potential VSS. Further, the unselected word line 22 is set to the ground potential VSS, and the unselected source line 23 is kept connected to the node 60. By this operation, a potential difference is generated between the pair of bit lines 18 and 19, and the sense amplifier 150 amplifies the potential difference and outputs data. Note that the write enable signal WE is not input at the time of reading and remains at the ground potential VSS.

  FIG. 8b shows operation waveforms at the time of writing. The address, input data, and write enable signal WE are input, and the write operation is controlled by the rising edge of the clock. The address is input to the predecoder 170 and then decoded at the rising edge of the clock to become an address signal 66. The word / source line driver circuit 51 receives the same address signal and further decodes the signal to set the selected word line 22 to the power supply potential VDD and the unselected word line 22 to the ground potential VSS. The source line 23 is always connected to the node 60. By this operation, the data of the bit lines 18 and 19 driven by the write driver circuit 155 is written into the memory cell 7.

  In the above-described embodiment, 1.0 V is adopted as the power supply voltage. However, the present invention is not limited to this, and a voltage value in the vicinity thereof can be adopted. Further, although the P-type MOSFET is used as the load element of the driving NMOSs 3 and 4, it can be configured by replacing it with a resistor.

<Example 2>
The present invention is applied to a static RAM in which the source line 23 is shared by two rows of memory cells 7. FIG. 9 shows the configuration of the static RAM. In FIG. 9, the connection of the substrate electrodes of the MOSFETs is omitted for simplicity, but the substrate electrodes of the P-type MOSFETs 1 and 2 are connected to the power supply terminal 8 and the substrate electrodes of the N-type MOSFETs 3 to 6 are grounded as in FIG. Connected to terminal 9. For the sake of simplicity, only two memory cells are shown, but they are arranged in a matrix as in FIG. In FIG. 9, reference numeral 77 denotes two rows of memory cells having a common source line, 80 denotes a word / source line driver circuit for controlling the potential of the source line 23 common to the word line 22, and 81 and 82 denote word lines 22. -1, an inverter for driving the word line 22-2, an inverter for driving the P-type MOSFET 57 and the N-type MOSFET 58, and an NOR for driving the N-type MOSFET 56 and the inverter 86. The circuit is shown.

  The word / source line driver circuit 80 is used individually for every two rows of the memory array 17, and the source lines 23 of all rows are connected to the node 60 via the word / source line driver circuit 80. A resistor 30 is connected to the node 60.

  Thus, when either the address signal 66-1 or 66-2 becomes “H” in the selected state, the N-type MOSFET 58 becomes conductive, the MOSFETs 56 and 57 become non-conductive, and the source line 23 is connected to the ground terminal 9. When both address signals 66-1 and 66-2 are in the non-selected state “L”, the N-type MOSFET 58 becomes non-conductive, the MOSFETs 56 and 57 become conductive, and the source line 23 An intermediate potential VMD is supplied.

  In this embodiment, since one switch circuit 30 is used for two rows of memory cells, the area occupied by all the switch circuits can be reduced.

<Example 3>
The present invention is applied to CMOS logic circuits having various logic functions. An embodiment of the CMOS logic circuit is shown in FIG. In FIG. 10, 301 is an inverter, 302 is a NOR circuit, 303 is a NAND circuit, 308 is a power source side source line, 309 is a ground side source line, 312 is a power source side switch circuit connected to the power source side source line 308, 313 , A ground side switch circuit connected to the ground side source line 309; 306, a P-type MOSFET for power source side switch circuit connected between the power source terminal 8 and the power source side source line 308; and 307, ground terminal 9 and the ground side source An N-type MOSFET for ground side switch circuit 310 connected between the lines 309, a resistor connected between the power supply terminal 8 and the power source side source line 308, and 311 between the ground terminal 9 and the ground side source line 309. A resistor connected between them, CE is a chip enable signal for controlling the operation of the N-type MOSFET 307, and CE * is the resistance of the P-type MOSFET 307. It shows a chip enable signal for controlling the work. The symbol * of the signal CE * is used to indicate that the polarity is opposite to that of the signal CE.

  In FIG. 10, although the symbol notation of the current path is omitted, in the inverter 301, the ground-side current path is composed of one N-type MOSFET and the power-source-side current path is composed of one P-type MOSFET. The NOR circuit 302 includes two N-type MOSFETs in which ground-side current paths are connected in parallel and two P-type MOSFETs in which power-source-side current paths are connected in series. The NAND circuit 303 includes two N-type MOSFETs in which ground-side current paths are connected in series, and two P-type MOSFETs in which power-source-side current paths are connected in parallel. Also, one terminal of each ground side current path is connected to the output terminal (not shown in FIG. 10) and the other terminal is connected to the ground side source line 309, and one terminal of each power source side current path is connected to the output terminal and the other side. Are connected to the power source side source line 308. Further, the substrate electrode of each N-type MOSFET is connected to the ground terminal 9, and the substrate electrode of each P-type MOSFET is connected to the power supply terminal 8.

  In FIG. 10, these three types of logic circuits are shown for the sake of simplicity. However, a larger number of N-type and P-type MOSFETs are used, and the logic circuits are connected in series, parallel, or series-parallel, respectively. Of course, it is possible to obtain complex desired logic functions.

  In this embodiment, low threshold voltage MOSFETs are used as the MOSFETs of the logic circuits 301 to 303.

  When the signal CE is “H” that makes each logic circuit in an operating state (the signal CE * becomes “L”), the N-type MOSFET 307 and the P-type MOSFET 306 are in a conductive state, and the ground-side source line 309 is connected to the ground terminal. 9 and the power source side source line 308 is connected to the power terminal 8. On the other hand, when the signal CE is “L” that puts each logic circuit in a standby state (the signal CE * becomes “H”), the N-type MOSFET 307 and the P-type MOSFET 306 are turned off, and the ground side source line 309 is turned on. Is connected to the resistor 311, and the power source side source line 308 is connected to the resistor 310. The resistors 310 and 311 each have a MOSFET leakage current in each logic circuit, and can obtain a predetermined intermediate potential between the power supply potential and the ground potential.

  The resistors 310 and 311 are not limited to this, and can be replaced with the current source circuits shown in FIGS. 11a and 11b, respectively, and further replaced with the voltage source circuits shown in FIGS. 12a and 12b, respectively. Is also possible. In either case, the same potential as that when the resistors 310 and 311 are used can be applied to each source line.

  Symbols 308 and 309 in FIGS. 11 and 12 indicate the connection positions in FIG. In FIG. 12, reference numeral 400 denotes a differential amplifier, and 401 and 402 denote additional power supplies having an intermediate potential between the power supply potential and the ground potential. The additional power supply 401 in FIG. 12a has a voltage value of VrefH, and the additional power supply 402 in FIG. 12b has a voltage value of VrefL. Each of the additional power supplies has a structure that divides the power supply voltage. The differential amplifier 400 is subjected to 100% negative feedback, and therefore outputs substantially the same voltage values VrefH and VrefL. The voltage value VrefH is a value that defines the potential applied to the power source side source line 308 during standby, and VrefL is a value that defines the potential applied to the ground side source line 309 during standby.

  In this embodiment, the power supply voltage VDD is set to 1.0V. FIG. 13 shows operation waveforms of the logic circuit in that case. In operation, the power supply voltage is supplied to the source electrode of the P-type MOSFET of each logic circuit and the source electrode of the N-type MOSFET is set to the ground potential, so that the operation speed of the logic circuit is not affected. Furthermore, since the threshold voltage of each MOSFET is a low threshold, high-speed operation can be realized.

  During standby, an intermediate potential VMP lower than the power supply voltage is supplied to the source electrode of the P-type MOSFET of each logic circuit, and an intermediate potential VMN higher than the ground potential is supplied to the source electrode of the N-type MOSFET. For this reason, in the P-type MOSFET in which the power supply voltage is supplied to the substrate electrode, the threshold voltage rises when a positive potential is biased between the source electrode and the substrate electrode, and the substrate electrode becomes the ground potential. In the N-type MOSFET, the threshold voltage rises when a negative voltage is biased between the source electrode and the substrate electrode. That is, since the threshold voltages of all the MOSFETs in each logic circuit are increased, the leakage current can be reduced. As described above, the intermediate potentials VMP and VMN are generated when the leakage current of each logic circuit flows into the resistor 310 and the resistor 311, respectively. When the constant current source circuit of FIGS. 12a and 12b is employed, the intermediate potentials VMP and VMN are given by the voltage values VrefH and VrefL. In this embodiment, the intermediate potentials VMP and VMN are set to 0.75 V and 0.25 V, respectively, and therefore the voltage values VrefH and VrefL are set to the same 0.75 V and 0.25 V, respectively.

1 is a circuit diagram for explaining a first embodiment of a semiconductor integrated circuit device according to the present invention; FIG. 2 is a waveform diagram for explaining an operation at the time of reading of the circuit shown in FIG. 1. FIG. 2 is a waveform diagram for explaining an operation at the time of writing of the circuit shown in FIG. 1. 1 is a circuit diagram for explaining a word / source line driver circuit including a switch circuit according to a first embodiment of the present invention; The circuit diagram for demonstrating the current source circuit and voltage source circuit which are connected to the switch circuit of the 1st Example of this invention. FIG. 6 is a curve diagram for explaining the relationship between the reading speed and the operating power consumption with respect to the threshold voltage of the MOSFET. 1 is a circuit block diagram for explaining an overall configuration of a first embodiment of the present invention. FIG. 9 is a waveform diagram for explaining read and write operations of the overall configuration shown in FIG. 8. . The circuit diagram for demonstrating the 2nd Example of this invention. The circuit diagram for demonstrating the 3rd Example of this invention. The circuit diagram for demonstrating the current source circuit connected to the switch circuit of the 3rd Example of this invention. The circuit diagram for demonstrating the voltage source circuit connected to the switch circuit of the 3rd Example of this invention. FIG. 11 is a waveform diagram for explaining the operation of the circuit shown in FIG. 10. FIG. 6 is a circuit diagram for explaining an example of a conventional semiconductor integrated circuit device. FIG. 6 is a circuit diagram for explaining another example of a conventional semiconductor integrated circuit device.

Explanation of symbols

1, 2, 306 ... P-type MOSFET, 3-6, 307 ... N-type MOSFET, 7, 77 ... Memory cell, 8 ... Power supply terminal, 9 ... Ground terminal, 18, 19 ... Bit line, 22 ... Word line, 23 , 308, 309... Source line, 30, 310, 311... Resistor, 33, 312, 313... Switch circuit, 51, 80... Word / source line driver circuit including switch circuit, 301. ... NAND circuit, 308 ... power source side source line, 309 ... ground side source line, VDD ... power source potential, VSS ... ground potential, VMD, VMP, VMN ... intermediate potential.

Claims (2)

A plurality of word lines, a plurality of bit line pairs, a plurality of static memory cells arranged in a matrix,
A plurality of switch circuits for controlling operating potentials of the plurality of static memory cells;
An intermediate potential generation circuit that is provided in common to a plurality of static memory cells provided corresponding to the plurality of word lines and generates a potential between a power supply potential and a ground potential;
Each of the plurality of static memory cells includes first and second load P-type MOSFETs, first and second drive N-type MOSFETs, and first and second transfer N-type MOSFETs,
Among the plurality of static memory cells, the operating potential of the memory cell selected in the read operation is larger than the operating potential of the memory cell in the standby state,
Among the plurality of static memory cells, the operation potential of the memory cell selected by the write operation is smaller than the operation potential of the memory cell selected by the read operation,
The plurality of switch circuits are controlled according to signals for controlling a plurality of word lines, and the source potentials of the first and second driving N-type MOSFETs are connected to the power supply potential generated by the intermediate potential generation circuit and the ground A semiconductor integrated circuit characterized by switching to a potential between a potential and a ground potential.   2. The semiconductor integrated circuit according to claim 1, wherein substrate electrodes of the first and second driving N-type MOSFETs are connected to a ground terminal.

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