JP4851711B2 - Static random access memory with reduced leakage current during active mode and method of operation thereof - Google Patents

Description

  The present invention relates generally to memory devices, and more particularly to a static random access memory (SRAM) having reduced leakage current during active mode and a method of operating the same.

  Memory devices are well known in the art and are used, inter alia, for practically any microprocessor and digital signal processor (DSP) application. One type of memory suitable for many applications is static random access memory (SRAM). SRAM devices are faster and easier to use than many other types of memory devices. Furthermore, SRAM devices using MOS technology exhibit relatively low standby power and do not require a refresh cycle to maintain stored information. These characteristics make SRAM devices particularly desirable for battery power supplies, such as laptop computers and personal digital assistance.

Miniaturization of SRAM devices is another feature that makes SRAM devices desirable for such battery power supplies. However, the desired miniaturization may involve undesirable operating problems for smaller SRAM devices. For example, current leakage increases as the size of the SRAM device decreases. Current leakage is also a problem during sleep mode, standby mode and active mode. In fact, current leakage, which can be expressed as I _DDQ , became more important during active mode as the size of the SRAM device continued to decrease.

Several options (options) already exist to reduce current leakage during active mode. In one option, the high operating voltage supplied to the SRAM device, for example, to reduce the voltage across the SRAM array is reduced. However, the reduced high operating voltage V _DD reduces the static noise margin (SNM) and write trip voltage (so-called “V _trip ”) below acceptable levels. Instead, the low operating voltage V _SS supplied to the SRAM device can be raised while in standby mode and lowered when in active mode. Unfortunately, this alternative requires a lot of switching power and does not support the write trip voltage V _trip .

High V _trip and SNM are desired cell characteristics of SRAM devices. A high SNM is required for circuit stability. If SNM is too low, the READ operation is disturbed. A high V _trip is required for proper data writing speed. If V _trip is too low, the WRITE operation is disturbed. _{Unfortunately} , the requirement for acceptable SNM and write trip voltage V _trip generally limits the tolerance for acceptable SRAM yield during manufacturing, as one increases and the other decreases.

A typical six-transistor SRAM memory cell (the basic unit of SRAM) consists of two p-channel “pull-up” transistors, two n-channel “pull-down” transistors, and two access transistors, which are typically n-channel transistors. It is made up. The strength of the p-doped and n-doped channels of the transistor affects the overall performance of the SRAM memory. For example, in the case of a strong n-channel, especially with a weak p-channel, the SNM becomes inappropriately low. In order to obtain a satisfactory SNM, we would like to try weakening the n-channel and / or strengthening the p-channel. However, in the case of a weak n-channel, especially with a strong p-channel, V _trip is undesirably low.

Thus, existing SRAM devices provide a weak n-channel (and / or strong p-channel) to obtain an acceptable SNM, and a strong n-channel (and / or weak p-channel) to obtain an acceptable V _trip. Challenged by competing and conflicting objectives of creating channels. In addition, the trade-off between this SNM and V _trip (and therefore reliable READ and WRITE) is increasingly constrained with continuous miniaturization and low operating voltage as these expand the effects of normal manufacturing changes. The

Even if SNM and V _trip is deteriorated when a high operating voltage V _DD is reduced, reduction in high operating voltage V _DD for low power operation, and often desirable for some test conditions. Although SNM and V _trip is deteriorated, the deterioration of the V _trip is particularly strong with a decrease in the high operating voltage V _DD. Therefore, V _trip tends to limit the low range of high operating voltage V _DD for operation. Therefore, a solution to reduce current leakage during active mode should have minimal adverse impact on SNM and V _trip .

Thus, what is needed in this field is an improved SRAM device that has reduced current leakage during active mode. In addition, improved SRAM devices with reduced current leakage require a strong SNM and write trip voltage V _trip .

In order to solve the above-mentioned drawbacks of the prior art, the present invention provides an SRAM device and a method for operating the same. In one embodiment, an SRAM device is between (1) SRAM coupled to a row peripheral by a word line and coupled to a column peripheral by a bit line, and (2) at least a portion of active mode. An array low voltage control circuit is provided that provides the enhanced low operating voltage V _ESS to the SRAM.

Thus, the present invention provides greater power savings and better SNM and write trip voltage V _trip tradeoffs than existing SRAM devices, allowing a wide process margin. Providing the enhanced low operating voltage V _ESS is because the enhanced low operating voltage V _ESS is greater than the substrate voltage (generally, the low operating voltage V _SS ), so the voltage across the memory cell is lowered and the threshold due to the back bias effect. By increasing the voltage V _tn , the current leakage I _DDQ is reduced. The SNM is improved by a high V _tn from the back bias effect that appropriately compensates for the SNM drop by the reduced cell voltage. When SNM is improved, cells are subject to minimal disturbance when the associated wordline voltage is raised for access as in READ or for a column not addressed in a row accessed for WRITE. . Similarly, the improved SNM allows WRITE operation without disturbing the cells of the unaddressed column.

Although weakness of enhanced low operating voltage is decreased read current I _read, however, I _read during the READ operation, a low operating voltage V _ESS augmented at lower value for the addressed column Recovered by giving. The present invention can also provide a low operating voltage V _ESS that is enhanced at a lower value for a WRITE operation than for a READ operation. In addition, the enhanced low operating voltage V _ESS can be used in the event of a SNM and write trip voltage failure, for example by providing an enhanced low operating voltage V _ESS at a higher voltage for critical processes. Can be set to compensate for process changes. When the write trip voltage is the worst case, the enhanced low operating voltage V _ESS can also be applied to a high value. Furthermore, for example, a low operating voltage V _ESS enhanced against a low voltage operation during the test can be given a high value.

Thus, the enhanced low operating voltage V _ESS can be defined to individual values based on certain factors, such as transistor parameters or mode of operation. For example, one enhanced low operating voltage V _ESS can be established for the test operation. Furthermore, various enhanced low operating voltage V _ESS values can be established for READ or WRITE operations. In some embodiments, a single enhanced low operating voltage V _ESS value can be established for more than one factor. Thus, a single enhanced low operating voltage V _ESS value can be provided for TEST, WRITE, and READ operations.

In other features, the present invention includes the steps of (1) using an SRAM array in an integrated circuit coupled to a row peripheral circuit by a word line and coupled to a column peripheral circuit by a bit line, and (2) an active mode. A method of operating an SRAM device having the step of providing an enhanced low operating voltage V _ESS to the SRAM array during at least a portion of the method is provided.

The preferred and alternative features of the present invention have been summarized above so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should recognize that the disclosed concepts and specific embodiments can be readily understood as a basis for designing or modifying other structures to accomplish the same objectives of the present invention. It is. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the invention. For a more complete understanding of the present invention, the following detailed description is referred to in conjunction with the accompanying drawings. To emphasize, the various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion. The following description is referenced in conjunction with the accompanying drawings.

Referring first to FIG. 1, there is shown a circuit diagram of an embodiment of an SRAM device, generally designated 100, in accordance with the principles of the present invention. The SRAM 100 includes an SRAM array 110, a row peripheral circuit 120, a column peripheral circuit 130, and an array low voltage control circuit 140. In general, the SRAM array 110 has multi-memory cells organized in a matrix of columns and rows having a corresponding number of wordlines and bitlines. For example, the SRAM device array 110 has 256 columns and 256 rows of memory cells. However, for ease of explanation, only a single row having the first, second, and third columns 112, 114, 116 of the SRAM array 110 is shown.

  In addition, a single word line, bit line pair, row peripheral circuit 120 and column peripheral circuit 130 associated with the first column 112 are shown and described. However, those skilled in the art will recognize that the word line, bit line pair, row peripheral circuit 120 and column peripheral circuit 130 shown and described in connection with the first column 112 are the second and third columns 114, It will be understood that not only 116 but also represents similar circuitry associated with additional columns and rows not shown.

The SRAM device 100 is a memory element for an associated microprocessor, digital signal processor (DSP), application specific integrated circuit (ASIC) or large electronic device. In some embodiments, one or more SRAM devices 100 have memory elements. An integrated circuit (IC) associated with the SRAM device 100 supplies the SRAM device with a high operating voltage V _DD and a low operating voltage V _SS . The high operating voltage V _DD and the low operating voltage V _SS can be chip supply voltages. In general, the signal path and data interface of the associated device is coupled to the SRAM device 100 to send address information and to retrieve / write data for reading / writing data to specific memory cells of the SRAM array 110. Those skilled in the art will understand the coupling of SRAM device 100 to associated equipment.

  Each of the first, second and third columns 112, 114, 116 includes a memory cell in a multi-row having a specific address for writing and reading data. Each memory cell stores data as 1 or 0 using MOSFETs and flip-flops. Reading and writing data in the first column 112 can be controlled by the row peripheral circuit 120 and the column peripheral circuit 130.

  The row peripheral circuit 120 controls the operation of the word line associated with one of the rows. The row peripheral circuit 120 includes, for example, a row predecoder, a row decoder, a word line driver, and a keeper. The word line driver can activate a word line for reading or writing based on the address signal received via the row signal path and decoded by the row predecoder and the row decoder.

  A column peripheral circuit 130 controls the selection of columns for the read and write SRAM arrays. The column peripheral circuit 130 may include, for example, a precharge circuit, a write circuit, a column multiplexer, and a sense amplifier. Further, the peripheral circuit of the column has an address decoder for determining the position of the memory cell in the SRAM array 110 and a control circuit for determining between data writing and reading. The precharge circuit, write circuit, column multiplexer and sense amplifier facilitate reading and writing of data to the correct decoded column address. Similar to row peripheral circuit 120, column peripheral circuit 130 may also include additional elements that facilitate writing and reading of data not shown or described herein.

The array low voltage control circuit 140 is configured to provide an enhanced low operating voltage V _ESS to the SRAM array during at least a portion of the active mode of the SRAM array 110. Of course, an enhanced low operating voltage V _ESS can be applied during all active modes. The array low voltage control circuit 140 can provide an enhanced low operating voltage V _ESS using active elements. For example, the array low voltage control circuit 140 may have a diode bridged footer to increase the low operating voltage V _SS and provide an enhanced low operating voltage V _ESS . The footer is a transistor disposed between the low operating voltage V _SS and the SRAM device 100. Generally, the footer is an n-channel MOSFET.

The array low voltage control circuit is an element that provides a voltage drop between the array and the low operating voltage supply bus. For example, the array low voltage control circuit 140 is a transistor that is turned on when the width of the transistor that is turned on determines the voltage drop. The array low voltage control circuit 140 may also use fuses to provide an enhanced low operating voltage V _ESS or to select a particular value for the enhanced low operating voltage V _ESS . These fuses can be used to select a specific enhanced low operating voltage V _ESS for the mode of operation, high operating voltage V _DD or transistor parameters. Of course, the fuse can also be used to select other enhanced low operating voltage V _ESS based on various factors.

In addition, the array low voltage control circuit 140 may use other elements, such as a ROM or a voltage regulator, to provide an enhanced low operating voltage V _ESS . The array low voltage control circuit 140 also provides logic circuitry to selectively provide the enhanced low operating voltage V _ESS to the SRAM 110 based on, for example, a WRITE operation, a READ operation, a test mode, or a process corner. Can also have. The ethics circuit can use fuses or transistors to make these selections. The logic circuit is an associated microprocessor that directs the selection of the array's low voltage control circuit 140.

In some embodiments, the array low voltage control circuit 140 can provide an enhanced low operating voltage V _ESS only during a WRITE operation. In other embodiments, the array low voltage control circuit 140 may provide the enhanced low operating voltage V _ESS to a lower value during the READ operation than during the WRITE operation. The array low voltage control circuit 140 can only provide this low value for the addressed column of the SRAM array 110.

For example, row peripheral circuit 120 and column peripheral circuit 130 exhibit a READ operation on the selected word line of first column 112. Thus, the array low voltage control circuit 140 provides a low value of the enhanced low operating voltage V _ESS to the first column 112 to improve the read current during the READ operation. In one embodiment, a low value of the enhanced low operating voltage V _ESS is provided to the appropriate block of the SRAM array 110 instead of the column.

In another embodiment, the array low voltage control circuit 140 provides an enhanced low operating voltage V _ESS during all of the active modes. The array low voltage control circuit 140 may also provide an enhanced low operating voltage V _ESS during all modes. For example, the array low voltage control circuit 140 can provide an enhanced low operating voltage V _ESS for standby and sleep modes.

The enhanced low operating voltage V _ESS is provided based on the characteristics of the SRAM device 100 transistor. For example, the array low voltage control circuit 140 may provide an enhanced low operating voltage V _ESS based on the processor corner. The array low voltage control circuit 140 provides a high value of the enhanced low operating voltage V _ESS when based on strong n process corners. In other embodiments, the array low voltage control circuit 140 provides an enhanced low operating voltage V _ESS based on factors such as the mode of operation or the value of the high operating voltage V _DD .

Referring to FIG. 2, an embodiment of a method for operating an SRAM device (generally indicated at 200) implemented in accordance with the principles of the present invention is shown. SRAM devices have SRAM that varies in size. For example, an SRAM device array has 256 columns and 256 rows of memory cells. SRAM devices are used in integrated circuits (ICs) that can include more than one SRAM array. In general, a low operating voltage V _SS and a high operating voltage V _DD are respectively applied to the SRAM array. The low operating voltage V _SS and the high operating voltage V _DD are chip supply voltages. The method 200 begins with a request to operate the SRAM device at step 205.

The enhanced low operating voltage V _ESS is then established at step 210. The enhanced low operating voltage V _ESS is established based on the general characteristics of the SRAM device transistor. In one embodiment, the established and enhanced low operating voltage V _ESS is changed based on the process corner. For example, the established and enhanced low operating voltage V _ESS is given a high value when the process corner is a strong n corner. The established and enhanced low operating voltage V _ESS is changed based on the high operating voltage V _DD or the temperature of the SRAM device. However, in some embodiments, the enhanced low operating voltage V _ESS is independent of the high operating voltage V _DD or temperature. Thus, the value of the enhanced low operating voltage V _ESS varies based on, for example, process corner, high operating voltage V _DD or temperature.

If the transistor has a strong n process corner, the value of the enhanced low operating voltage V _ESS is given a higher value compared to a transistor not in the strong n process corner. In one embodiment, the enhanced low operating voltage V _ESS is given a high value based on other transistor characteristics, eg, the weak p-characteristics of the SRAM array transistors. For example, the enhanced low operating voltage V _ESS is applied to a high 0.1 volt based on transistor characteristics. In some embodiments, if enhanced low value of low operating voltage V _ESS was given in the column which is between the address of the READ operation, the enhanced low operating voltage V _ESS is given a uniform high value.

Accordingly, different values of the enhanced low operating voltage V _ESS are established for different operations. For example, one enhanced low operating voltage V _ESS value is established for the test operation. Other enhanced low operating voltage V _ESS values are established for READ or WRITE operations. In certain embodiments, a single enhanced low operating voltage V _ESS value can be used for more than one type of operation.

After establishing the enhanced low operating voltage V _ESS , a determination is made whether the SRAM device is in active mode in a first decision step 220. The SRAM device is in active mode during WRITE or READ operations. A logic circuit, eg, a microprocessor associated with the IC, determines when a WRITE or READ operation occurs. In addition, column and row peripheral circuits indicate a READ or WRITE operation.

If the SRAM device is not in active mode, at step 225, an inactive bias is applied to the SRAM array. If not in active mode, the SRAM device is in standby mode or sleep mode. The inactive bias is designed to lower the high operating voltage V _DD or increase the low operating voltage V _SS to help maintain data during the inactive mode. Optionally, an enhanced low operating voltage V _ESS is applied to the SRAM array during the inactive state. In one embodiment, the array low voltage control circuit provides an inactive bias or an enhanced low operating voltage V _ESS . After applying the inactive bias, the method 200 proceeds to step 270.

Referring to the first decision step 220, if the SRAM device is in the active mode, a determination is made as to whether the SRAM device is in the test mode of the second decision step 230. A logic circuit associated with the IC determines whether the SRAM device is in a test mode. If the SRAM device is in test mode, the test mode value of the enhanced low operating voltage V _ESS is provided to the SRAM device at step 235. The test mode value of the enhanced low operating voltage V _ESS is provided by the array low voltage control circuit. In some embodiments, the test mode for the enhanced low operating voltage V _ESS is established, it is equivalent to a low operating voltage V _ESS augmented. After providing the increased low operating voltage V _ESS test mode value, the method proceeds to step 270.

If the SRAM device is not in test mode, a determination is made as to whether the SRAM device is in READ mode in a third decision step 240. The related logic circuit determines whether or not the SRAM device is performing a READ operation. If it is a READ operation, the enhanced low operating voltage V _ESS READ mode value is provided to the SRAM array at step 245. The READ mode value is provided by the array low voltage control circuit. In some embodiments, the READ mode value is only provided to a portion of the SRAM array.

For example, the addressed column of the SRAM array is the only part of the SRAM array that is given the READ mode. In another embodiment, the SRAM array block is given a READ mode value during a READ operation. The READ mode value of the enhanced low operating voltage V _ESS is approximately the value of the low operating voltage V _SS . After providing the enhanced low operating voltage _VESS READ mode value, the method proceeds to step 270.

If the SRAM device is not in READ mode, a determination is made as to whether the SRAM device is in WRITE mode in a fourth decision step 250. The associated logic circuit determines whether the SRAM device is performing a WRITE operation. If in WRITE mode, the enhanced low operating voltage V _ESS WRITE mode value is applied to the SRAM array at step 255. The WRITE mode value is provided by the array low voltage control circuit. After providing the enhanced low operating voltage _VESS WRITE mode value, the method 200 proceeds to step 270.

If the SRAM device is not in WRITE mode, the enhanced low operating voltage V _ESS is applied to the SRAM array at step 260. The enhanced low operating voltage V _ESS is provided by the array low voltage control circuit. The enhanced low operating voltage V _ESS provides a low voltage across the SRAM array during active mode to reduce leakage current while maintaining proper SNM and V _trip . The enhanced low operating voltage V _ESS is provided by increasing the low operating voltage V _SS using an array low voltage control circuit.

The enhanced low operating voltage V _ESS is provided by using an active device, such as a diode bridged footer. Of course, those skilled in the art will also appreciate that the enhanced low operating voltage V _ESS can be provided by using other active or passive elements. For example, the enhanced low operating voltage V _ESS is provided by resistors, transistors, diodes, low dropout regulators, or combinations thereof. In one embodiment, the enhanced low operating voltage V _ESS is about 0.2 volts. In other embodiments, the enhanced low operating voltage V _ESS is approximately the low operating voltage V _SS .

After providing the enhanced low operating voltage V _ESS , a fifth decision step 270 determines whether to continue the operation of the SRAM device. If the operation of the SRAM device continues, the method proceeds to step 210 and continues as described above. One skilled in the art will also appreciate that the high operating voltage V _DD is maintained in the SRAM array during operation. In one embodiment, the high operating voltage V _DD is about 1.2 volts and the low operating voltage V _SS is about 0.0 volts. If the operation of the SRAM device does not continue, the method ends at step 280.

  Although the method has been described herein with reference to particular steps performed in particular instructions, these steps can be combined and subdivided to form an equivalent method without departing from the teachings of the invention. It will be understood that it is converted to or rearranged. Thus, unless otherwise specified herein, the order and / or grouping of steps is not a limitation of the present invention.

Although the invention has been described in detail, it should be understood by those skilled in the art that various changes, substitutions, and alternatives can be made in the broadest form without departing from the spirit and scope of the invention. For example, the SRAM array can be at an enhanced low operating voltage V _ESS during all modes, eg, standby and sleep modes. Furthermore, the SRAM array is provided with an enhanced low operating voltage V _ESS only during WRITE operations. In another embodiment, an enhanced low operating voltage V _ESS is applied to the SRAM array during all active modes.

1 shows a circuit diagram of an embodiment of an SRAM device constructed in accordance with the principles of the present invention. 2 illustrates an embodiment of a method of operating an SRAM device implemented in accordance with the principles of the present invention.

Claims (11)

An SRAM array connected to a high operating voltage node, each having a plurality of SRAM cells connected to a peripheral circuit of a row by a word line, connected to a peripheral circuit of a column by a bit line, and connected to a low operating voltage node. When,
An array low voltage control circuit that selectively generates an enhanced low operating voltage (V _ESS ) at the low operating voltage node of the SRAM cell of the SRAM array, at least during READ and WRITE operations. And
The enhanced low operating voltage has a higher voltage value than a low operating voltage (V _SS ) that is a chip supply voltage, and the enhanced low operating voltage is lower during READ operation than during WRITE operation. ,
SRAM device.   The SRAM device of claim 1, wherein the enhanced low operating voltage is also generated during a standby mode or a sleep mode.   The SRAM device of claim 1 or claim 2, wherein the enhanced low operating voltage is also generated during a test mode. An SRAM array connected to a high operating voltage node, each having a plurality of SRAM cells connected to a peripheral circuit of a row by a word line, connected to a peripheral circuit of a column by a bit line, and connected to a low operating voltage node. When,
An array low voltage control circuit that selectively generates an enhanced low operating voltage (V _ESS ) at the low operating voltage node of the SRAM cell of the SRAM array during at least READ operation ;
The enhanced low operating voltage has a voltage value higher than a low operating voltage (V _SS ) , which is a chip supply voltage, and the enhanced low voltage provided to the cells of the addressed column during the READ operation . A low operating voltage is lower than the enhanced low operating voltage applied to the cells of the unaddressed column;
SRAM device.   The SRAM device of claim 4, wherein the enhanced low operating voltage is also generated during standby mode or sleep mode. The SRAM device according to claim 4 or 5 , wherein the enhanced low operating voltage is also generated during WRITE operation. The high operating values to choose a high operating voltage supplied to the voltage node, SRAM device according to any one of claims 1 to claim 6. The array low voltage control circuit is configured to provide the enhanced low operating voltage based on a factor selected from the group consisting of process corners, transistor parameters, operating modes, and high supply voltage values. The SRAM device according to any one of claims 1 to 7 . The low voltage control circuit of the array using an active element, SRAM device according to any one of claims 1 to claim 8. Low voltage control circuit of said array, a diode, a transistor, a fuse, ROM, voltage regulators, and is selected from the group consisting of a logic circuit, SRAM device according to any one of claims 1 to claim 8. A microprocessor comprising the SRAM device according to any one of claims 1 to 10 .

Images