JP2003123479A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which needless power consumption caused by the sub-threshold leak current of transistors constituting a memory cell can be reduced and the whole power consumption can be reduced further. SOLUTION: A leak current in standby of a transistor being non-operative as a circuit is reduced by dynamically varying voltage applied to a transistor so that voltage lower than original power source voltage required for operation is applied to a cell being not operated and voltage boosted to the original power source voltage is applied to the cell in operation, as voltage applied to transistors constituting a memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a static semiconductor memory device suitable for low power consumption operation.

[0002]

2. Description of the Related Art In recent years, static random access memory (hereinafter abbreviated as SRAM) has been developed as a main memory of portable equipment and is also used as a cache of a low power microcomputer. Both of them are used as key devices for portable information devices, and high power consumption and low power consumption have been strongly demanded.

In particular, since the power consumption of the CMOS circuit is proportional to the square of the power supply voltage (VDD), it is possible to effectively reduce the power by lowering the voltage. From this, SR
A technique for operating an AM at a low voltage has been actively studied.

The conventional static semiconductor memory device as described above will be described below with reference to the drawings. FIG. 6 is a circuit diagram showing a memory cell configuration in a conventional static type semiconductor memory device. In FIG. 6, 61 is a memory cell arranged in a matrix by rows and columns (only one set of memory cells is shown in the figure for convenience), and 62 is provided corresponding to each row of the memory cells 61. A plurality of word lines 63, and a plurality of bit line pairs (B
L, / BL), 64, and 65 have their gates connected together to one of the plurality of word lines 62, and connect the first and second bit lines 63 to the first and second internal nodes, respectively. The first and second access transistors 66 are connected between a power supply node supplied with a deactivation potential (GND) and a first internal node, and have a gate connected to the second internal node. , A second driver transistor 67 connected between the power supply node to which the deactivation potential (GND) is applied and the second internal node, and the gate of which is connected to the first internal node, 68 is connected between a power supply node to which an activation potential (power supply voltage VDD) is applied and a first internal node, and has a second gate.
A first load transistor connected to the internal node of
A second load transistor 69 is connected between a power supply node supplied with an activation potential (power supply voltage VDD) and a second internal node, and has a gate connected to the first internal node.

In the above structure, the load transistor 6
8. A positive feedback loop is formed by the first inverter including the driver transistor 66 and the second inverter including the load transistor 69 and the driver transistor 67, and forms a memory element. For this memory element, by driving the word line 62 to the positive power supply V _DD , the bit line pair (BL, / B is passed through the access transistor 64 and the access transistor 65.
L) 63 can read and write necessary data.

[0006]

However, in the conventional semiconductor memory device as described above, the threshold voltage is, for example, 0.
When a memory cell is composed of MOS transistors of 2 V or less, there is a serious problem that the subthreshold leakage current of the transistor composing such a memory cell increases.

Therefore, there is a problem in that wasteful power consumption occurs due to the above leak current, which hinders reduction of the total power consumption. The present invention solves the above-mentioned conventional problems, and wasteful power consumption due to a subthreshold leakage current of a transistor forming a memory cell can be reduced, and total power consumption can be further reduced. Provide a device.

[0008]

In order to solve the above problems, a semiconductor memory device of the present invention is a static type semiconductor memory device having a memory cell formed of a transistor formed on a main surface of a semiconductor substrate. A first power supply line for applying a lower voltage than the original power supply voltage for activating the memory cell, and a second power supply line for applying the power supply voltage.
Power source line, and a first P-type switching transistor having a source connected to the first power source line and a drain connected to a power source node for providing an activation potential of the plurality of memory cells arranged in a matrix. A second P-type switching transistor having a source connected to the second power supply line and a drain connected to a power supply node for providing an activation potential of the plurality of memory cells arranged in a matrix. , The first P-type switching transistor,
The gate receives the signal of the same phase as the signal of the word line at the first
The connection between the power supply line and the power supply node that supplies the activation potential of the memory cell is turned on / off, and the second P-type switching transistor receives a signal of a phase opposite to the signal of the word line at the gate. The connection between the second power supply line and the power supply node which supplies the activation potential of the memory cell is O
It is characterized in that it is configured to be N / OFF.

As described above, a voltage lower than the original power supply voltage required for operating a non-operating cell is applied to the transistor constituting the memory cell, and the voltage is applied when operating the cell. It is possible to dynamically change the voltage applied to the transistor so as to increase the voltage to the original power supply voltage and apply the voltage to the cell, and reduce the leak current in the transistor that is in a circuit standby state.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to claim 1 of the present invention is a static semiconductor memory device having a memory cell formed of a transistor formed on a main surface of a semiconductor substrate. As the power supply applied to the transistor constituting the memory cell, an original power supply voltage for activating the memory cell and a voltage lower than the power supply voltage are switched according to the active or inactive operating state of the memory cell. It is configured to include a means for supplying to the memory cell.

According to another aspect of the present invention, there is provided a semiconductor memory device, which is a static type semiconductor memory device having a memory cell formed of a transistor formed on a main surface of a semiconductor substrate. A plurality of first power supply lines that give a lower voltage than the power supply voltage, second power supply lines that give the power supply voltage, sources connected to the first power supply line, and drains arranged in a matrix. A first P-type switching transistor connected to a power supply node for providing an activation potential of the memory cell, a plurality of memories in which a source is connected to the second power supply line and a drain is arranged in the matrix. A second P-type switching transistor connected to a power supply node for providing an activation potential of the cell, The gate receives a signal of the same phase as the signal of the power line to turn on / off the connection between the first power line and a power node which supplies the activation potential of the memory cell, and the second P-type switching transistor Thus, the signal of the opposite phase to the signal of the word line is received by the gate, and the connection between the second power supply line and the power supply node which supplies the activation potential of the memory cell is turned on / off.

According to a third aspect of the semiconductor memory device, the first and second P-type switching transistors according to the second aspect are installed for each of a plurality of memory cells on the same word line.

According to another aspect of the semiconductor memory device of the present invention, instead of the first P-type switching transistor of claim 2, an N-type MOSFET is arranged and connected to form a first N-type switching transistor. The first N-type switching transistor turns on / off the connection between the first power supply line and the power supply node which supplies the activation potential of the memory cell by receiving the signal of the opposite phase of the signal of the word line at the gate. Constitute.

A semiconductor memory device according to a fifth aspect is a static type semiconductor memory device having a memory cell formed of a transistor formed on a main surface of a semiconductor substrate, and is an original device for activating the memory cell. A first power supply line for supplying a power supply voltage, a source connected to the first power supply line, and a drain connected to a power supply node for supplying an activation potential of the plurality of memory cells arranged in a matrix. A P-type switching transistor, and a diode having a P-type region connected to the first power supply line and an N-type region connected to a power supply node for providing an activation potential of the plurality of memory cells arranged in a matrix. And the first P
Type switching transistor is configured to turn on / off the connection between the first power supply line and a power supply node which supplies the activation potential of the memory cell by receiving a signal of a phase opposite to that of the word line at its gate. .

According to another aspect of the semiconductor memory device of the present invention, a signal having a phase opposite to that of the global word line signal is supplied to the first P-type switching transistor of the fifth aspect.

According to a seventh aspect of the present invention, there is provided a semiconductor memory device including the first P-type switching transistor according to the fifth aspect.
A plurality of memory cell blocks on the same global word line are installed and configured.

According to another aspect of the present invention, there is provided a semiconductor memory device, which is a static type semiconductor memory device having a memory cell composed of a transistor formed on a main surface of a semiconductor substrate. A first power supply line for supplying a voltage lower than the power supply voltage, and a power supply node for supplying an activation potential of the plurality of memory cells, the source of which is connected to the first power supply line and the drains of which are arranged in a matrix. A first P-type switching transistor connected to the first P-type switching transistor, and the first P-type switching transistor receives the signal of the word line at its gate to receive the activation potential of the first power line and the memory cell. It is configured to turn ON / OFF the connection between the power supply node and the power supply node.

According to these structures, a voltage lower than the original power supply voltage (VDD) necessary for operating the non-operating cells is applied to the transistors forming the memory cells, When operating, the voltage applied to the transistor is dynamically changed so that the original power supply voltage (VDD) is applied to the cell to increase the leakage current in the transistor that is in a circuit standby state. Reduce.

A semiconductor memory device according to a ninth aspect uses a silicon-on-insulator (hereinafter abbreviated as SOI) substrate as the semiconductor substrate according to any one of the first to eighth aspects, A circuit structure is formed over the substrate.

According to this structure, when the circuit structure is formed on the SOI substrate, the leak current in the transistor in standby is also due to the effect of SOI that drain leak is reduced when the voltage applied to the transistor is lowered. Reduce.

A semiconductor memory device according to an embodiment of the present invention will be specifically described below with reference to the drawings. Here, a static semiconductor memory device including a plurality of transistors formed on the main surface of a semiconductor substrate and having a plurality of memory cells arranged in a matrix by rows and columns and suitable for low power consumption operation Will be described as an example. (First Embodiment) A semiconductor memory device according to the first embodiment of the present invention will be described.

FIG. 1 is a circuit diagram showing the structure of the semiconductor memory device according to the first embodiment. In FIG. 1, 11 denotes memory cells arranged in a matrix by rows and columns (only one set of memory cells is shown in the figure for convenience), 12
Is a voltage applied to a load transistor (see FIG. 6 showing a conventional example) which is a constituent element of the memory cell 11 in order to activate the memory cell 11 when performing a normal read / write operation on the memory cell 11. Is a power supply line that gives a potential lower than the power supply voltage (VDD) as the original power supply voltage (VDD), 13 is a word line, and 14 is a power supply line that receives a signal in phase with the signal on the word line 13 at its gate 1
2 is a P-type switching transistor that turns ON / OFF the connection between the power supply node that supplies the activation potential of the memory cell 11, 15 is a power supply line that supplies the power supply voltage (VDD), and 16 is on the word line 13. It is a P-type switching transistor which receives a signal having a phase opposite to that of the signal at its gate and turns ON / OFF the connection between the power supply line 15 and the power supply node which supplies the activation potential of the memory cell 11. The configuration of the plurality of transistors in the memory cell 11 is the same as that of the memory cell 61 of FIG. 6 showing the conventional example.

Further, the P-type switching transistor 14
Is a plurality of memory cells 1 whose drains are arranged in a matrix.
A power supply line 1 that is connected to a power supply node that supplies an activation potential of 1 and supplies a source with a voltage lower than the power supply voltage (VDD)
2 and the gate receives a signal in the same phase as the signal on the word line 13 to turn on / off the connection between the power supply line 12 and a power supply node that supplies the activation potential of the memory cell 11, and perform P-type switching. The transistor 16 has a drain connected to a power supply node for supplying the activation potential of the memory cell 11, a source connected to a power supply line 15 for supplying a power supply voltage (VDD), and a gate having a phase opposite to that of the signal on the word line 13. Upon receiving the signal, the connection between the power supply line 15 and the power supply node that supplies the activation potential of the memory cell 11 is turned on / off.

The operation of the static type semiconductor memory device configured as described above will be described below.
First, when the word line 13 connected to the memory cell 11 in FIG. 1 is selected, an H-level potential is input to the word line 13 and is turned on / off by a signal in phase with the signal on the word line 13 14 is turned off, and the P-type switching transistor 16 which is turned on / off by a signal having a phase opposite to the signal on the word line 13 is turned on and the memory cell 11 is turned on.
Is supplied with the power supply voltage (VDD) from the power supply line 15,
Normal read / write operations for the memory cell 11 are performed.

On the other hand, the word line 1 connected to the memory cell 11
When 3 is not selected, an L level potential is input to the word line 13 and the word line 13 is turned on / off by a signal having a phase opposite to the signal on the word line 13.
The P-type switching transistor 16 which is turned off is turned off
However, the P-type switching transistor 14 that is turned on / off by a signal having the same phase as the signal on the word line 13 is turned on, and the memory cell 11 has a voltage that can hold the data in the memory cell 11 and is higher than the power supply voltage (VDD). A low voltage is applied, and the memory cell 11 holds the written data and enters the standby state.

As described above, according to the present embodiment, the voltage applied to the memory cell 11 is lower than the power supply voltage (VDD) in the non-operating memory cell and rises to the power supply voltage (VDD) during the operation. With the configuration, the leak current (power consumption) during standby can be reduced.

Further, when the above circuit configuration is formed on the SOI substrate, the leak current during standby can be reduced also from the effect of SOI that drain leakage is reduced when the applied voltage is lowered. (Second Embodiment) A semiconductor memory device according to the second embodiment of the present invention will be described.

FIG. 2 is a circuit diagram showing the structure of the semiconductor memory device according to the second embodiment. In FIG. 2, 21 is a memory cell, 22 is a power supply line that gives a voltage lower than the power supply voltage (VDD), 23 is a word line, 25 is a power supply line that gives a power supply voltage (VDD), and 26 is a signal on the word line 23. The gate receives the signal of the opposite phase to the ON / O connection between the power supply line 25 and the power supply node which supplies the activation potential of the memory cell 21.
This is a P-type switching transistor that performs FF, and the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 1 is that the gate receives a signal having a phase opposite to that of the signal on the word line 23, and the connection between the power supply line 22 and the power supply node which supplies the activation potential of the memory cell 21 is made. The point is that an N-type switching transistor 24 that turns ON / OFF is provided.

The operation of the static type semiconductor memory device configured as described above will be described below.
First, when the word line 23 connected to the memory cell 21 of FIG. 2 is selected, an H-level potential is input to the word line 23, and the N-type switching is turned on / off by a signal having a phase opposite to the signal on the word line 23. The transistor 24 is turned off, and the P-type switching transistor 26 which is turned on / off by a signal having a phase opposite to that of the signal on the word line 23 is turned on and the memory cell 21 is turned on.
Is supplied with a power supply voltage (VDD) from the power supply line 25, and normal read / write operations are performed on the memory cell 21.

On the other hand, the word line 2 connected to the memory cell 21
When 3 is not selected, the L-level potential is input to the word line 23, and the word line 23 is turned on / off by a signal having a phase opposite to that of the signal on the word line 23.
The P-type switching transistor 26 that is turned off is turned off
Then, the N-type switching transistor 24 which is turned on / off by a signal having a phase opposite to the signal of the word line 23 is turned on, and the memory cell 21 has a voltage that can hold the data in the memory cell 21 and is higher than the power supply voltage (VDD). Is applied to the memory cell 21, and the memory cell 21 holds the written data and enters the standby state.

As described above, according to the present embodiment, the voltage applied to the memory cell is lower than the power supply voltage (VDD) in the non-operating memory cell, and the power supply voltage (VD
By configuring so as to rise to D), it is possible to reduce the leak current (power consumption) during standby.

Further, when it is provided on the SOI substrate,
S that drain drain decreases when the applied voltage is lowered
The effect of OI can also reduce the leakage during standby. (Third Embodiment) A semiconductor memory device according to a third embodiment of the present invention will be described.

FIG. 3 is a circuit diagram showing the structure of the semiconductor memory device according to the third embodiment. In FIG. 3, 31 is a memory cell, 32 is a word line, 33 is a P-type switching transistor which is turned on / off by a signal having a phase opposite to that of the signal on the word line 32, and 34 is a power supply line for supplying a power supply voltage (VDD). Yes, the above is the same as the configuration of FIG.

The difference from the configuration of FIG. 1 is that the power supply voltage (VD
The point is that the diode 35 that steps down to a voltage lower than that of D) is provided in parallel with the P-type switching transistor 33.

The operation of the static type semiconductor memory device configured as described above will be described below.
First, when the word line 32 connected to the memory cell 31 in FIG. 3 is selected, an H-level potential is input to the word line 32, and the P-type switching is turned on / off by a signal having a phase opposite to the signal on the word line 32. The transistor 33 is turned on, the power supply voltage (VDD) from the power supply line 34 is applied to the memory cell 31, and normal read / write operation is performed on the memory cell 31.

On the other hand, the word line 3 connected to the memory cell 31
When 2 is not selected, the potential of L level is input to the word line 32, and the signal of the phase opposite to the signal of the word line 32 turns ON / OFF.
The P-type switching transistor 33 which is turned off is turned off
Then, the diode 35 provided in parallel with the P-type switching transistor 33 steps down the power supply voltage (VDD) of the power supply line 34 to a voltage lower than the power supply voltage (VDD). Is supplied with a voltage lower than the power supply voltage (VDD), the memory cell 31 holds the written data and enters the standby state.

As described above, the diode 35 for stepping down to a voltage lower than the power supply voltage (VDD) is connected in parallel with the P-type switching transistor 33 which is turned on / off by a signal having a phase opposite to the signal on the word line 32. Since the voltage applied to the memory cell 31 is lower than the power supply voltage (VDD) in the non-operating memory cell and increased to the power supply voltage (VDD) in the operating state by providing the memory cells 31,
Leakage current (power consumption) during standby can be reduced.

Further, when it is provided on the SOI substrate,
S that drain drain decreases when the applied voltage is lowered
The effect of OI can also reduce the leak during standby. (Embodiment 4) A semiconductor memory device according to Embodiment 4 of the present invention will be described.

FIG. 4 is a circuit diagram showing the structure of the semiconductor memory device according to the fourth embodiment. 4, 41 is a memory cell, 42 is a word line, 44 is a power supply line for supplying a power supply voltage (VDD), 45 is a diode for stepping down the power supply voltage (VDD) to a lower voltage, and the above is the configuration of FIG. Is similar to.

A difference from the configuration of FIG. 3 is that a global word line 46 for controlling selection or non-selection of the word line 42 is provided over a plurality of lines, and the P-type switching transistor 43 has a phase opposite to the signal of the global word line 46. It is configured so that it is turned on / off by the signal of.

The operation of the static type semiconductor memory device configured as described above will be described below.
First, when the global word line 46 that controls a plurality of word lines 42 connected to the memory cell 41 of FIG. 4 is selected, the global word line 46 and the word line 42 are selected.
H level potential is input to the global word line 4
The P-type switching transistor 43 which is turned on / off by the signal of the opposite phase to the signal of 6 is turned on, and the memory cell 41 is
A power supply voltage (VDD) is applied from the power supply line 44, and normal read / write operations are performed on the memory cell 41.

On the other hand, when the global word line 46 is not selected, the L level potential is input to the global word line 46 and the word line 42, and the global word line 46 is input.
The P-type switching transistor 43 which is turned on / off by a signal opposite in phase to the signal of is turned off, and the diode 4 provided in parallel with the P-type switching transistor 43 is provided.
5 lowers the power supply voltage (VDD) of the power supply line 44 to a voltage lower than the power supply voltage (VDD),
Is supplied with a voltage that can hold the data in the memory cell 41 and lower than the power supply voltage (VDD), and the memory cell 41 holds the written data and enters a standby state.

As described above, the P-type which turns ON / OFF the diode 45 for stepping down from the power supply voltage (VDD) to a voltage lower than the power supply voltage (VDD) by a signal having a phase opposite to the signal on the global word line 46. By providing the switching transistor 43 in parallel with the switching transistor 43, the voltage applied to the memory cell 41 can be configured to be lower than the power supply voltage (VDD) in the non-operating memory cell 41 and increase to the power supply voltage (VDD) in operation. The leakage current (power consumption) during standby can be reduced.

Further, when it is provided on the SOI substrate,
S that drain drain decreases when the applied voltage is lowered
The effect of OI can also reduce the leakage during standby. (Fifth Embodiment) A semiconductor memory device according to a fifth embodiment of the present invention will be described.

FIG. 5 is a circuit diagram showing the structure of the semiconductor memory device according to the fifth embodiment. In FIG. 5, 51 is a memory cell, 52 is a word line, 53 is a P-type switching transistor which is turned on / off by a signal in phase with the signal on the word line 52, and the above is the same as the configuration of FIG. is there.

The difference from the configuration of FIG. 1 is that the memory cell 51
The point is that only the power supply line 54 that supplies a voltage lower than the power supply voltage (VDD) is provided as a power supply line for supplying power to the. The operation of the static semiconductor memory device configured as described above will be described below.

First, when the word line 52 connected to the memory cell 51 of FIG. 5 is selected, an H-level potential is input to the word line 52, and an O signal is generated by a signal in phase with the signal on the word line 52.
N-OFF P-type switching transistor 53 is O
FF. Here, the bit line (BL) 5 of the memory cell 51
When the potential of 5 is raised from 0 V to 1.8 V, for example, the internal node N1 becomes 1.3 due to the effect of capacitive coupling.
The driver transistor 514 is pulled up to about V
Turns on and lowers the internal node N2 to 0V. Then, the load transistor 515 is turned on, and H data is stored in the flip-flop forming the memory cell 51.

On the other hand, the word line 5 connected to the memory cell 51
When 2 is not selected, the L-level potential is input to the word line 52, and the signal of the same phase as the signal of the word line 52 turns ON / OFF.
P-type switching transistor 53 that turns off turns on
Then, the memory cell 51 is supplied with a voltage that can hold the data in the memory cell 51 and lower than the power supply voltage (VDD), and the memory cell 51 holds the written data and enters a standby state.

As described above, according to the present embodiment, a normal read / write operation can be performed without supplying extra power to the memory cell even when active, and a voltage lower than the power supply voltage (VDD) can be used during sleep. Data can be retained.

In each of the first to fifth embodiments, the memory cell has a CMOS configuration.
However, the memory cell may be composed of five CMOS transistors.

Needless to say, the memory cell may be constituted by an NMOS load type cell or a resistance load type cell.

[0053]

As described above, according to the present invention, a voltage lower than the original power supply voltage necessary for operating a non-operating cell is applied as a voltage applied to a transistor forming a memory cell. When applying and operating, the voltage applied to the transistor is dynamically changed so that the applied voltage is raised to the original power supply voltage and applied to the cell, and the leak current in the transistor in the circuit standby state is reduced. Can be reduced.

Further, when the circuit structure is formed on the silicon-on-insulator substrate, the effect of the silicon-on-insulator that the drain leakage is reduced when the voltage applied to the transistor is lowered is also due to the effect of waiting. The leak current in the transistor can be reduced.

As described above, useless power consumption due to the subthreshold leakage current of the transistors forming the memory cell can be reduced, and the total power consumption can be further reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a conventional semiconductor memory device.

[Explanation of symbols]

11 memory cell 12 power supply line 13 that supplies a voltage lower than the power supply voltage (VDD) 13 word line 14 P-type switching transistor 15 power supply line 16 that supplies a power supply voltage (VDD) 21 P-type switching transistor 21 memory cell 22 lower than the power supply voltage (VDD) Power supply line 23 for supplying voltage Word line 24 N-type switching transistor 25 Power supply line for supplying power supply voltage (VDD) 26 P-type switching transistor 31 Memory cell 32 Word line 33 P-type switching transistor 34 Power supply line 35 for supplying power supply voltage (VDD) Diode 41 Memory cell 42 Word line 43 P-type switching transistor 44 Power supply line 45 for supplying power supply voltage (VDD) Diode 46 Global word line 51 Memory cell 52 Word line 53 P-type switching transistor 54 Power supply lines N1 and N2 that give a voltage lower than the source voltage (VDD) Internal node 511 Access transistor 512 Access transistor 513 Driver transistor 514 Driver transistor 515 Load transistor 516 Load transistor 61 Memory cell 62 Word line 63 Bit line (BL, / BL) 64 access transistor 65 access transistor 66 driver transistor 67 driver transistor 68 load transistor 69 load transistor

Continued front page    (72) Inventor Akio Hirata             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5B015 HH04 JJ05 JJ07 KA06 KA28                       KB72 KB74 QQ01                 5F083 BS26 BS27 BS29 BS37 BS50                       GA06 HA02 LA10

Claims (9)

[Claims] 1. A static type semiconductor memory device having a memory cell composed of a transistor formed on a main surface of a semiconductor substrate, wherein the memory cell is activated as an applied power supply to a transistor forming the memory cell. And a voltage lower than the power supply voltage according to the active or inactive operating state of the memory cell. Storage device. 2. A static type semiconductor memory device having a memory cell composed of a transistor formed on a main surface of a semiconductor substrate, wherein a voltage lower than an original power supply voltage for activating the memory cell is set. A first power supply line for applying the power supply voltage, a second power supply line for supplying the power supply voltage, a source are connected to the first power supply line, and drains have activation potentials of the plurality of memory cells arranged in a matrix. A first P-type switching transistor connected to a power supply node for supplying, a power supply node for supplying an activation potential of the plurality of memory cells, the source of which is connected to the second power supply line and the drain of which is arranged in the matrix. And a second P-type switching transistor connected to the first P-type switching transistor. The connection between the first power supply line and the power supply node that supplies the activation potential of the memory cell is turned on / off by the second P-type switching transistor, and the signal of the opposite phase to the signal of the word line is received. The semiconductor memory device is configured such that the connection between the second power supply line and the power supply node that supplies the activation potential of the memory cell is turned on / off by receiving the gate at the gate. 3. The semiconductor memory device according to claim 2, wherein the first and second P-type switching transistors are arranged for each of a plurality of memory cells on the same word line. 4. A first N-type MOSFET is arranged and connected instead of the first P-type switching transistor to form a first N-type MOSFET.
Type switching transistor, and the first N type switching transistor connects the first power supply line and a power supply node for applying an activation potential of the memory cell by receiving a signal of a phase opposite to the signal of the word line at the gate. ON / OFF
3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is configured to. 5. A static type semiconductor memory device having a memory cell formed of a transistor formed on a main surface of a semiconductor substrate, wherein a first power supply line for applying an original power supply voltage for activating the memory cell. A first P-type switching transistor having a source connected to the first power supply line and a drain connected to a power supply node for providing an activation potential of the plurality of memory cells arranged in a matrix; A diode for connecting a region to the first power supply line and connecting an N-type region to a power supply node for providing an activation potential of the plurality of memory cells arranged in a matrix, wherein the first P Connection between the first power supply line and the power supply node for applying the activation potential of the memory cell, the gate of which receives the signal of the opposite phase of the signal of the word line by the switching transistor A semiconductor memory device characterized in that it is configured to turn ON / OFF. 6. The signal supplied to the first P-type switching transistor is supplied with a signal having a phase opposite to that of the signal on the global word line.
The semiconductor memory device according to 1. 7. The first P-type switching transistor is arranged for each of a plurality of memory cell blocks on the same global word line, and is configured.
The semiconductor memory device according to 1. 8. A static semiconductor memory device having a memory cell composed of a transistor formed on a main surface of a semiconductor substrate, wherein a voltage lower than an original power supply voltage for activating the memory cell is set. A first P-type which is connected to a first power supply line to be applied, a source is connected to the first power supply line, and a drain is connected to a power supply node which supplies activation potentials of the plurality of memory cells arranged in a matrix. A switching transistor, and the first P-type switching transistor connects the first power supply line receiving a signal of a word line at its gate and a power supply node supplying an activation potential of the memory cell. A semiconductor memory device characterized by being configured to turn on / off. 9. The silicon-on-insulator substrate is used as a semiconductor substrate, and a circuit structure is formed on the silicon-on-insulator substrate. Semiconductor memory device.