US7358520B2 - Semiconductor memory cell, method for fabricating it and semiconductor memory device - Google Patents

Semiconductor memory cell, method for fabricating it and semiconductor memory device Download PDF

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US7358520B2
US7358520B2 US11/075,481 US7548105A US7358520B2 US 7358520 B2 US7358520 B2 US 7358520B2 US 7548105 A US7548105 A US 7548105A US 7358520 B2 US7358520 B2 US 7358520B2
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region
storage element
semiconductor memory
electrode
memory cell
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US20050212037A1 (en
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Cay-Uwe Pinnow
Klaus-Dieter Ufert
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Infineon Technologies AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/068—Shaping switching materials by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

Definitions

  • the invention relates to a semiconductor memory cell, to a method for fabricating a semiconductor memory cell and to a semiconductor memory device.
  • a material region of the memory cell the material of which can adopt a plurality of phases which correspond to different values of a physical variable of the material of the material region of the memory cell and which are or can be assigned to different storage states of the semiconductor memory cell, is or has been provided as the storage element of the semiconductor memory cell, between a first electrode device and a second electrode device and in electrical contact with these electrode devices.
  • the phase state of the storage element is programmed or erased in a suitable way, for example by corresponding heating, when writing and/or erasing the semiconductor memory cell with a phase change storage mechanism, and the storage state and the associated information content are read by determining the value of the physical variable and the corresponding association when reading the semiconductor memory cell.
  • a problem of known semiconductor memory cells having a phase change storage mechanism is that the electric currents for heating required to program or erase the states of the respective storage elements adopt relatively high levels which cannot readily be delivered by conventional semiconductor circuit arrangements on which they are based and which are customarily used in semiconductor memory devices. This is because firstly the programming or erasing of the respective states of the storage material of the storage elements is effected thermally by a corresponding flow of current through the storage material of the memory cell, and this flow of current is imparted by contact-connection with the first and second electrode devices.
  • the overall result is a restriction on the integration density both with regard to the geometric extent of the memory cell itself and with regard to the extent of the semiconductor circuit arrangement on which it is based and which has to realize the programming or erasing processes.
  • the present invention provides a semiconductor memory cell, a semiconductor memory employing the memory cell, and a method of making the semiconductor memory.
  • the invention provides a semiconductor phase change memory cell having a first electrode device and a second electrode device, an insulation region between the first electrode device and the second electrode device, and a contact recess having a wall region, passing all the way through the insulation region between the first electrode device and the second electrode device.
  • a storage element is provided in electrical contact with the first electrode and the second electrode, the storage element having a material region made of phase change material, wherein the material region of the storage element is formed as a lining region of the wall region of the contact recess, wherein a region of the contact recess which is not taken up by the material region of the storage element is of substantially electrically insulating configuration.
  • FIGS. 1-9 are lateral cross-sectional views illustrate one embodiment of intermediate states which can be reached during fabrication of a semiconductor memory cell with a phase change storage mechanism according to the invention, in accordance with a preferred embodiment of the fabrication method according to the invention.
  • FIG. 10 illustrates a diagrammatic plan view of a part of the arrangement illustrated in FIG. 9 .
  • the invention provides a semiconductor memory cell with a phase change storage mechanism, a method for fabricating a semiconductor memory cell with a phase change mechanism and a corresponding semiconductor memory device, in which programming or erasing of the storage element of the memory cell can be realized in a particularly simple yet reliable way with a high integration density.
  • a material region of the memory cell is provided as the storage element of the semiconductor memory cell, between a first electrode device and a second electrode device and in electrical contact with these electrode devices.
  • the semiconductor memory cell with a phase change storage mechanism is distinguished in that the material region of the storage element is formed as a lining region of a wall region of a contact recess which passes all the way through an insulation region between the first electrode device and the second electrode device, and wherein the space or region of the contact recess which is not taken up by the material region of the storage element is of substantially electrically insulating design.
  • the contact recess is provided in an insulation region between the first electrode device and the second electrode device and runs all the way through this insulation region. Furthermore, it is provided that the space or region of the contact recess which is not taken up by the material region of the storage element is electrically insulating or has an electrically insulating action. Consequently, the lateral or physical extent of the material region of the storage element is not determined by the contact recess, but rather exclusively by the thickness with which the material region that lines the wall region can be formed.
  • the physical extent of the material region of the storage element can be restricted to a greater extent than in the prior art, and consequently a smaller volume of material has to be subjected to a corresponding phase change during programming.
  • the electric currents which are required for programming can be reduced to a greater extent than in the prior art.
  • the underlying circuit arrangements which have to perform the programming operations can also be designed with smaller dimensions. Consequently, the measure according to the invention makes it possible to achieve a higher integration density of semiconductor memory cells with a phase change mechanism.
  • the contact recess is designed as a contact hole.
  • the contact recess is designed with a quadrilateral, rectangular, square, round or circular lateral cross section.
  • the contact recess may also be designed as a trench structure, or a trench as it is known.
  • this space or region may be formed completely or partially as a cavity.
  • the space or region of the contact recess which is not taken up by the material region of the storage element to be completely or partially filled with an insulation material.
  • the wall region of the contact recess to be completely or only partially lined with the material of the material region of the storage element.
  • the material region of the storage element is designed as a spacer element or as a plurality of spacer elements.
  • the material region of the storage element in each case to be designed with a contact surface, which is of sublithographic extent or dimensions, with the first electrode device and/or with the second electrode device.
  • the material for the material region of the storage element is a material of which phases correspond to different nonreactive resistances.
  • a further embodiment of the invention consists in forming a semiconductor memory device in which a plurality of semiconductor memory cells according to the present invention are provided.
  • a further embodiment of the invention consists in providing a method for fabricating a semiconductor memory cell with a phase change mechanism.
  • a method of fabricating a semiconductor memory cell with a phase change storage mechanism provides that a material region of the memory cell, the material of which can adopt a plurality of phases which correspond to different values of a physical variable of the material of the material region of the memory cell and which are or can be assigned to different storage states of the semiconductor memory cell, is provided as the storage element of the semiconductor memory cell, between a first electrode device and a second electrode device and in electrical contact with these electrode devices.
  • a method according to the invention for fabricating a semiconductor memory cell with a phase change storage mechanism is distinguished in that the material region of the storage element is formed as a lining region of a wall region of a contact recess which passes all the way through an insulation region between the first electrode device and the second electrode device, and wherein the space or region of the contact recess which is not taken up by the material region of the storage element is of substantially electrically insulating design.
  • the contact recess is designed as a contact hole.
  • the contact recess is designed with a quadrilateral, rectangular, square, round or circular lateral cross section.
  • the contact recess is designed as a trench structure or trench.
  • the space or region of the contact recess which is not taken up by the material region of the storage element is completely or partially filled with an insulation material.
  • the wall region of the contact recess prefferably be completely lined by the material region of the storage element.
  • the material region of the storage element may be designed as a spacer element or as a plurality of spacer elements.
  • the material region of the storage element is in each case designed with a contact surface, which is of sublithographic extent or dimensions, with the first electrode device and/or with the second electrode device.
  • the material for the material region of the storage element can be formed or selected as a material of which phases correspond to different nonreactive resistances.
  • a carrier having a first electrode device in its surface region is provided and/or formed, that the insulation region having a surface region is then formed on the surface region of the carrier, that the contact recess is then formed at a defined location in or at the insulation region in such a manner that this contact recess extends through the insulation region from the surface region of the insulation region at least to part of the first electrode device and has a wall region, that the wall region of the contact recess or part of it is then lined with the material region of the storage element in such a manner that this material region is in direct or indirect electrical contact with the first electrode device and ends flush with the surface region of the insulation region, and that the second electrode device is then formed in such a manner that this second electrode device is in direct or indirect electrical contact with the material region of the storage element at the surface region of the insulation region.
  • the material region of the storage element is formed by conformal production, over the entire surface, of a layer of the material of the material region of the storage element, in such a manner that the surface region of the insulation region, the wall regions of the contact recess and the base region of the contact recess are covered, and by subsequent, in particular anisotropic etchback of the layer of the material of the material region of the storage element, in such a manner that the material of the material region of the storage element remains in place only at wall regions of the contact recess but is otherwise removed.
  • the carrier used is a semiconductor material region in which a CMOS circuit arrangement which forms the basis of the semiconductor memory cell is or has been formed, with in particular the first electrode device being designed to be in electrical contact with source/drain regions of selection transistor devices of the underlying CMOS circuit arrangement.
  • PCRAM Phase Change RAM
  • amorphous-crystalline phase change of a vitreous material typically Ge—Sb—Te or Ag—In—Sb—Te compounds
  • amorphous phase and the crystalline phase of these compounds have clear differences in electrical conductivity, these differences typically amounting to two to three orders of magnitude. This difference is exploited in order to determine and read the total resistance of the cell.
  • the programming to convert a cell which is in the amorphous state into the low-resistance, crystalline phase is effected by using a heating pulse to heat the material to above the crystallization temperature and thereby enabling the material to crystallize.
  • the reverse process, i.e., that of erasing the cell is realized by heating the material to even above the melting point and then quenching it by rapid cooling into the amorphous, high-resistance state.
  • the PCRAM concept loses the possibility of realizing a compact cell array, comprising individual cells which each have one transistor and one resistively switching element (1T1R), in a cell architecture with a cell area of 5-8F 2 , where F denotes the minimum feature size which can be achieved with a given lithography technology.
  • the maximum current is approximately 100 ⁇ A, and a further reduction would be useful from technological aspects, since the energy consumption is reduced and parallel programming of the cells is made possible, which considerably increases the overall programming speed and therefore the data throughput.
  • Examples include structures which can be produced by a spacer process and allow contact surface areas reduced to sublithographic dimensions.
  • a further example is what is known as an edge cell, in which the electrode-glass interface is horizontal in form and the heating currents can be reduced by using a low layer thickness of the electrode, cf. for example G. Wicker, Nonvolatile, High Density, High Performance Phase Change Memory, SPIE Conference on Electronics and Structures for MEMS, Vol. 3891, Queensland, 2 (1999), or also Y. H. Ha, An edge contact cell for Phase Change RAM featuring very low power consumption, Symposia on VLSI technology and VLSI circuits, Conference proceedings (2003), 12B4.
  • the drawback of the first of the two solutions outlined consists in the fact that the overall current cannot be reduced to a sufficient extent, since the geometric reduction with current lithography generations leads to contact surface areas which require an erase current of typically 1 mA.
  • the present invention provides, inter alia, a process sequence which is CMOS-compatible and is not limited by the resolution of the corresponding lithography. Despite this, it has a considerably better potential for reducing the write and erase currents than the alternatives that have been proposed hitherto, since a considerable reduction in the currents appears possible.
  • the contact surface area can be reduced to an area which is not determined by the lithography, but rather is at a sublithographic level.
  • phase change material into an etched contact hole.
  • Any desired process which effects sidewall coverage of the contact hole can be selected for this deposition.
  • an anisotropic (dry) etching step is used in order to etch back the phase change material.
  • the material which is present on the dielectric and in the contact hole base is removed, and only the material which has been deposited at the edge of the contact hole is left in place.
  • the interior of the contact hole is filled with a dielectric material.
  • the top electrode production and contact-connection can then be carried out after the dielectric has been planarized. This can be done by application and etching of a metal layer or in another variant by means of a Damascene process—e.g., W, Cu or the like.
  • a Damascene process e.g., W, Cu or the like.
  • first of all a carrier 20 having a surface region 20 a is provided or produced, with the first or lower electrode devices 14 or the electrode regions 14 provided—e.g., as MO Metallination—in the region of the surface 20 a , the surface region 14 a of which electrode devices or regions 14 ends flush with the surface region 20 a of the carrier 20 .
  • the first or lower electrode devices 14 or the electrode regions 14 provided—e.g., as MO Metallination—in the region of the surface 20 a , the surface region 14 a of which electrode devices or regions 14 ends flush with the surface region 20 a of the carrier 20 .
  • the carrier 20 may consist of a semiconductor material region in which a corresponding semiconductor circuit arrangement forming the basis of the switching of the semiconductor memory cells 10 that are to be formed in the semiconductor memory device 100 is included or formed.
  • this underlying semiconductor circuit arrangement is not specifically illustrated in the sequence of FIGS. 1 to 8 , but is indicated in pure exemplary and diagrammatic form in FIG. 9 , and should also be imagined as being included in FIGS. 1 to 8 .
  • a dielectric region 30 having a surface region 30 a is formed on the surface region 20 a of the carrier 20 .
  • the dielectric region 30 may also comprise a sequence of one or more layers, for example, a first layer of silicon dioxide and a second layer of silicon nitride above it.
  • a contact recess 32 is formed into the dielectric region 30 or insulation region 30 , starting from the surface region 30 a thereof, at each of the predefined locations X.
  • the predefined locations X approximately correspond to the positions at which the first electrode devices 14 below are located in the surface region 20 a of the carrier 20 .
  • the recesses 32 or contact recesses 32 which may also be or have been formed as contact holes, extend from the surface region 30 a of the insulation region 30 or dielectric region 30 as far as the surface region 14 a of the first electrode devices 14 below and therefore completely pass through the whole of the insulation region 30 .
  • the recesses 32 have wall regions 32 w and a base region 32 b , which at least partially corresponds to the surface region 14 a of the first electrode device 14 .
  • a layer 16 ′ for the material region 16 for the semiconductor memory cells 10 of the semiconductor memory device 100 that is to be produced is formed conformally on the arrangement shown in FIG. 3 , for example by deposition.
  • the material of the layer 16 ′ is a phase change material, for example Ge—Sb—Te.
  • the conformal production of the layer 16 ′ causes the surface regions 30 a of the insulation region 30 , the wall regions 32 w of the recesses or contact recesses 32 and the base regions 32 b of the contact recesses 32 to be covered with the material of the layer 16 ′.
  • an anisotropic etchback process is carried out, which removes the material of the layer 16 ′ on the laterally extending surfaces, i.e., in the example illustrated in FIG. 5 from the surface regions 30 a of the insulation region 30 and from the base region 32 b of the respective contact recess 32 , so that only wall regions 32 w of the contact recesses 32 comprising the material of the layer 16 ′ remain in place, with the result that in this way the material regions 16 for the semiconductor memory cells 10 that are to be formed are produced as storage elements 11 , offering reduced, relatively small upper and lower contact surfaces 16 a and 16 b , respectively.
  • a further insulation material 40 ′ or a further dielectric region 40 ′ having a surface region 40 a ′ is deposited two-dimensionally, specifically such that the free spaces which remain in the contact recesses 32 are completely filled, with the result that dielectric plugs 40 with surface region 40 a are formed there.
  • the additional insulation material 40 ′ is caused to recede, for example by chemical-mechanical polishing, stopping at the surface region 30 a of the insulation region 30 , so that the contact recesses 32 remain filled with the dielectric plugs 40 .
  • the second or upper electrode devices 18 or electrode regions 18 are formed, which in this case are in direct electrical contact, via the upper contact surfaces 16 a , with the material regions 16 of the semiconductor memory cells 10 , i.e., with the storage elements 11 of the semiconductor memory cells 10 .
  • FIG. 9 illustrates one embodiment of a more detailed view of the completed semiconductor memory device 100 according to the invention, in this case with two semiconductor memory cells 10 with a phase change storage mechanism according to the invention.
  • the carrier 20 is designed as a semiconductor material region with a CMOS structure or circuit forming the basic switching arrangement.
  • Selection transistors T are formed by means of word lines WL, which serve as gate electrodes G, and by means of source/drain regions S and D, respectively, which are provided.
  • the drain regions are each electrically conductively connected to structures of a 0-metallization level by means of plugs P, these structures forming or including the first or lower electrode devices 14 , which may, for example, consist of tungsten.
  • FIG. 10 illustrates a plan view of the structure illustrated in FIG. 9 , specifically in sectional form.

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US11/075,481 2004-03-09 2005-03-09 Semiconductor memory cell, method for fabricating it and semiconductor memory device Active 2026-02-23 US7358520B2 (en)

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Cited By (4)

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US20060139989A1 (en) * 2004-12-21 2006-06-29 Infineon Technologies Ag Integration of 1T1R CBRAM memory cells
US20080253166A1 (en) * 2007-04-16 2008-10-16 Wolfgang Raberg Integrated Circuit, Method for Manufacturing an Integrated Circuit, Memory Cell Array, Memory Module, and Device
US20140166965A1 (en) * 2012-12-14 2014-06-19 SK Hynix Inc. Resistive memory device and fabrication method thereof
US20180358409A1 (en) * 2017-06-08 2018-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and method for fabricating the same

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US20060273297A1 (en) * 2005-06-07 2006-12-07 Thomas Happ Phase change memory cell having ring contacts
EP1966841B1 (de) * 2005-12-20 2010-09-08 Nxp B.V. Vertikale phasenwechsel-speicherzelle und herstellungsverfahren dafür
US7812334B2 (en) * 2006-04-04 2010-10-12 Micron Technology, Inc. Phase change memory elements using self-aligned phase change material layers and methods of making and using same
US9178141B2 (en) 2006-04-04 2015-11-03 Micron Technology, Inc. Memory elements using self-aligned phase change material layers and methods of manufacturing same
TWI347670B (en) * 2007-02-01 2011-08-21 Promos Technologies Inc Phase-change memory and fabrication method thereof
US20080278988A1 (en) * 2007-05-09 2008-11-13 Klaus Ufert Resistive switching element
DE102007035858A1 (de) * 2007-07-31 2009-02-05 Qimonda Ag Integrierte Schaltung, Verfahren zum Herstellen einer integrierten Schaltung, Speicherzellenarray, Speichermodul sowie Vorrichtung
KR20090097362A (ko) * 2008-03-11 2009-09-16 삼성전자주식회사 저항 메모리 소자 및 그 형성 방법
KR101490429B1 (ko) * 2008-03-11 2015-02-11 삼성전자주식회사 저항 메모리 소자 및 그 형성 방법
CN101981720B (zh) 2008-04-01 2013-10-23 Nxp股份有限公司 垂直相变存储单元
US9183928B2 (en) * 2009-12-29 2015-11-10 Micron Technology, Inc. Descending set verify for phase change memory
CN104966717B (zh) * 2014-01-24 2018-04-13 旺宏电子股份有限公司 一种存储器装置及提供该存储器装置的方法
US11158788B2 (en) * 2018-10-30 2021-10-26 International Business Machines Corporation Atomic layer deposition and physical vapor deposition bilayer for additive patterning

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US20060139989A1 (en) * 2004-12-21 2006-06-29 Infineon Technologies Ag Integration of 1T1R CBRAM memory cells
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US7732888B2 (en) 2007-04-16 2010-06-08 Qimonda Ag Integrated circuit, method for manufacturing an integrated circuit, memory cell array, memory module, and device
US20140166965A1 (en) * 2012-12-14 2014-06-19 SK Hynix Inc. Resistive memory device and fabrication method thereof
US20180358409A1 (en) * 2017-06-08 2018-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Memory device and method for fabricating the same
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US20050212037A1 (en) 2005-09-29
DE102004011430B4 (de) 2008-06-19

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