US6906569B2 - Digital signal delay device - Google Patents

Digital signal delay device Download PDF

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US6906569B2
US6906569B2 US10/658,742 US65874203A US6906569B2 US 6906569 B2 US6906569 B2 US 6906569B2 US 65874203 A US65874203 A US 65874203A US 6906569 B2 US6906569 B2 US 6906569B2
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signal
signal delay
delay element
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gate
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US20040124900A1 (en
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Martin Brox
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Qimonda AG
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Infineon Technologies AG
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00156—Layout of the delay element using opamps, comparators, voltage multipliers or other analog building blocks

Definitions

  • the invention relates to a digital signal delay device in accordance with the preamble of claim 1 .
  • delay lock loops are often used for generating the internal clock. These consist e.g. of many delay members that are connected in series.
  • a delay member serves to apply a delay to a digital signal available at the input of the delay member, so that a digital output signal may be tapped at the output of the delay member, said output signal being delayed vis-à-vis the input signal, but corresponding to it otherwise.
  • a delay member may e.g. consist of two inverters connected in series, in particular CMOS inverters.
  • the input of the first inverter forms the input
  • the output of the second inverter forms the output of the delay member, the output of the first inverter being connected to the input of the second inverter.
  • the signal at the output of the first inverter changes—after a predetermined delay time t a —its state from “logically high” to “logically low” (—or vice versa from “logically low” to “logically high”—).
  • the signal at the output of the second inverter or at the output of the delay member, respectively changes—again after a predetermined delay time t b —its state from “logically low” to “logically high” (—or vice versa from “logically high” to “logically low”—).
  • a plurality of delay members of the above-mentioned type may be connected in series.
  • the signal at the output of the n-th delay member is delayed by n ⁇ T vis-à-vis the signal at the input of such a signal delay device.
  • the outputs of the delay members may—except with the respectively following delay member—additionally be connected with the (total) output of the signal delay device, e.g. by means of corresponding transfer gates.
  • That delay member may be selected, the output signal of which is to be connected through to the output of the signal delay device.
  • the delay of the (total) output signal can be adjusted with respect to the signal available at the input of the signal delay device or at its first delay member, respectively.
  • the total signal delay which is applied to the input signal is, however, adjustable with relatively coarse exactness only.
  • a digital signal delay device for converting a signal (IN) to a delayed signal (OUT) corresponding thereto, said device comprising a plurality of signal delay elements connected in series, wherein, depending on the desired delay of the delayed signal (OUT), the output signal of a particular signal delay element is respectively used for generating the delayed signal (OUT), and wherein each of the signal delay elements comprises one single inverter only.
  • the output signal of the respective signal delay element used for generating the delayed signal (OUT) may then be inverted or not inverted vis-à-vis the signal (IN).
  • the switching device connected with the respective signal delay element is correspondingly designed such that—on activation—it advances the output signal in a non-inverted or in an inverted manner.
  • the respectively advanced, delayed signal corresponds to the signal (IN)—which is e.g. available at the input of the signal delay device—(i.e. is identical, or alternatively complementary thereto), and has an—adjustable—delay vis-à-vis to it (namely a delay which substantially corresponds to the delay time of the output signal of that signal delay element whose output signal is—possibly in inverted form—advanced via the corresponding switching device.
  • the signal (IN) which is e.g. available at the input of the signal delay device—(i.e. is identical, or alternatively complementary thereto)
  • an—adjustable—delay vis-à-vis to it namely a delay which substantially corresponds to the delay time of the output signal of that signal delay element whose output signal is—possibly in inverted form—advanced via the corresponding switching device.
  • the respectively desired delay time can be adjusted substantially more accurately or precisely than with conventional digital signal delay devices.
  • FIG. 1 a schematic representation of a circuit arrangement of a digital signal delay device according to prior art
  • FIG. 2 a schematic representation of a circuit arrangement of a digital signal delay device in accordance with an embodiment of the present invention
  • FIG. 3 a schematic representation of an inverter circuit arrangement used as a gate of the first kind with the digital signal delay device illustrated in FIG. 2 ;
  • FIG. 4 a schematic representation of a transfer gate circuit arrangement used as a gate of the second kind with the digital signal delay device illustrated in FIG. 2 ;
  • FIG. 5 a a schematic representation of a gate of the first kind used with an alternative embodiment of a signal delay device, and of a tristate inverter additionally connected behind the respective gate of the first kind.
  • FIG. 5 b a schematic representation of a gate of the second kind used with the alternative embodiment of a signal delay device, and of a tristate inverter additionally connected behind the gate;
  • FIG. 6 a a schematic representation of a gate of the first kind used with a modification of the alternative embodiment, and of a transfer gate connected therebehind, and of a tristate inverter;
  • FIG. 6 b a schematic representation of a gate of the first kind used with the modification of the alternative embodiment, which is used instead of the gate of the second kind as illustrated in FIG. 5 b , and of two tristate converters connected therebehind.
  • FIG. 1 shows a schematic representation of a circuit arrangement of a digital signal delay device 1 in accordance with prior art.
  • the signal delay device 1 serves to apply an—adjustably high—delay to a digital signal IN available at an input 2 a of the signal delay device 1 , so that a digital signal OUT—which is delayed vis-à-vis the input signal IN—can be tapped at the output 2 b of the signal delay device 1 .
  • the signal delay device 1 comprises a plurality of signal delay elements 3 a , 3 b , 3 c , 3 d , 3 e connected in series.
  • the number n of signal delay elements 3 a , 3 b , 3 c , 3 d , 3 e is—as will be explained in detail below—chosen as a function of that signal delay that is to be obtained maximally with the signal delay device 1 .
  • the first signal delay element 3 a is connected with the input 2 a of the signal delay device 1 via a line 4 a , and—via a line 4 b —with the input of the second signal delay element 3 b .
  • the output of the second signal delay element 3 b is connected to the input of the third signal delay element 3 c via a line 4 c .
  • the output of the third signal delay element 3 c is connected with the input of a further (not illustrated) signal delay element via a line 4 d , etc.
  • the input of the signal delay element 3 d is connected to the output of a preceding (not illustrated, either) signal delay element via a line 4 e
  • the input of the signal delay element 3 e is connected to the output of the signal delay element 3 d via a line 4 f.
  • Each signal delay element 3 a , 3 b , 3 c , 3 d , 3 e comprises two inverters 5 a , 5 b , or 6 a , 6 b , or 7 a , 7 b , or 8 a , 8 b , or 9 a , 9 b , connected in series.
  • the input of the respectively first inverter 5 a , 6 a , 7 a , 8 a , 9 a of each signal delay element 3 a , 3 b , 3 c , 3 d , 3 e forms the respective input of the corresponding signal delay element 3 a , 3 b , 3 c , 3 d , 3 e (i.e.
  • each signal delay element 3 a , 3 b , 3 c , 3 d , 3 e forms the respective output of the corresponding signal delay element 3 a , 3 b , 3 c , 3 d , 3 e (i.e. is connected with the corresponding line 4 b , 4 c , 4 d , 4 f ).
  • the signal at the output of the first signal delay element inverter 5 a changes—after a certain delay time t a —its state from “logically high” to “logically low” (—or vice versa from “logically low” to “logically high”—).
  • the signal at the output of the second signal delay element inverter 5 b or at the output of the first signal delay element 3 a changes—again after a certain delay time t b —its state from “logically low” to “logically high” (—or vice versa from “logically high” to “logically low”—).
  • the remaining signal delay elements 3 b , 3 c , 3 d , 3 e have a structure that is correspondingly identical to that of the first signal delay element 3 a.
  • the output of the first signal delay element 3 a is—except that it is connected via the line 4 b with the input of the second signal delay element 3 b —additionally connected via a line 15 a with the input of a first gate, e.g. a transfer gate 16 a.
  • a first gate e.g. a transfer gate 16 a.
  • the outputs of the remaining signal delay elements 3 b , 3 c , 3 d , 3 e each are also connected with the input of corresponding further gates, in particular transfer gates 16 b , 16 d , 16 e , via corresponding lines 15 b , 15 d , 15 e.
  • the outputs of the transfer gates 16 a , 16 b , 16 d , 16 e are connected via corresponding lines 17 a , 17 b , 17 d , 17 e to a line 18 which is connected with the output 2 b of the signal delay device 1 .
  • Corresponding control signals C 1 , C 2 , . . . , C n ⁇ 1 , C n are applied to the control inputs 19 a , 19 b , 19 d , 19 e of the transfer gates 16 a , 16 b , 16 d , 16 e , as will be explained in detail further below.
  • a “logically low” control signal C 1 , C 2 , . . . , C n ⁇ 1 , C n the respective transfer gate 16 a , 16 b , 16 d , 16 e is in a “locked” state, and in the case of a “logically high” control signal C 1 , C 2 , . . .
  • the signal OUT that is output at the output 2 b of the signal delay device 1 is thus applied with a delay vis-à-vis the signal at the input 2 a of the signal delay device 1 , said delay corresponding to the delay time of the output signal of that signal delay element 3 a , 3 b , 3 c , 3 d , 3 e whose output is just being connected through to the output 2 b of the signal delay device 1 via the corresponding transfer gate 16 a , 16 b , 16 d , 16 e (plus the delay time of the respective transfer gate 16 a , 16 b , 16 d , 16 e connected through).
  • FIG. 2 shows a schematic representation of a circuit arrangement of a digital signal delay device 101 in accordance with an embodiment of the present invention.
  • the signal delay device 101 may e.g. be installed in a DRAM memory element based e.g. on CMOS technology (or in any other element). It serves to apply an—adjustably high—delay to a digital signal IN available at an input 102 a of the signal delay device 101 , so that a digital signal OUT—delayed vis-à-vis the input signal IN—can be tapped at the output 102 b of the signal delay device 101 .
  • the signal delay device 101 comprises a plurality of signal delay elements 103 a , 103 b , 103 c , 103 d , 103 e that are connected in series.
  • the number n of signal delay elements 103 a , 103 b , 103 c , 103 d , 103 e is as will be explained more exactly further below—selected as a function of that signal delay that is to be achieved maximally with the signal delay device 101 .
  • the first signal delay element 103 a is connected via a line 104 a with the input 102 a of the signal delay device 101 and—via a line 104 b —with the input of the second signal delay element 103 b .
  • the output of the second signal delay element 103 b is connected to the input of the third signal delay element 103 c via a line 104 c .
  • the output of the third signal delay element 103 is connected via a line 104 d with the input of a further (not illustrated) signal delay element, etc.
  • the input of the signal delay element 103 d is connected via a line 104 e to the output of a preceding (not illustrated, either) signal delay element, and the input of the signal delay element 103 e is connected via a line 104 f to the output of the signal delay element 103 d.
  • Each signal delay element 103 a , 103 b , 103 c , 103 d , 103 e comprises—different from the signal delay device illustrated in FIG. 1 —only one single inverter 105 , 106 , 107 , 108 , 109 (instead of two inverters connected in series), wherein the input of the respective inverter 105 , 106 , 107 , 108 , 109 forms the respective input of the corresponding signal delay element 103 a , 103 b , 103 c , 103 d , 103 e (i.e.
  • the signal at the output of the first signal delay element 103 a or of the inverter 105 , respectively changes—after a certain delay time t—its state from “logically high” to “logically low” (—or vice versa from “logically low” to “logically high”—).
  • the signal at the output of the first signal delay element 103 a (or of the inverter 105 , respectively) and accordingly also the signal at the input of the second signal delay element 103 b (or of the inverter 106 , respectively) changes its state from “logically high” to “logically low” (—or vice versa from “logically low” to “logically high”—)
  • the signal at the output of the second signal delay element 103 b or of the inverter 106 changes—again after a certain delay time t—its state from “logically low” to “logically high” (—or vice versa from “logically high” to “logically low”—).
  • the signal at the output of the second signal delay element 103 b or of the inverter 106 , respectively, thus corresponds to the signal IN at the input of the first signal delay element 103 a or of the inverter 105 , respectively, with the exception that it is delayed vis-à-vis thereto—in total—by a delay time of t+t 2t.
  • the remaining signal delay elements 103 c , 103 d , 103 e are of a structure that is correspondingly identical to that of the first two signal delay elements 103 a , 103 b.
  • the signal at the output of the n-th signal delay element 103 c , 103 d , 103 e thus corresponds, generally speaking, to the signal IN at the input 102 a of the signal delay device 101 , with the exception that it is
  • the output of the first signal delay element 103 a or of the inverter 105 is—except that it is connected via the line 104 b with the input of the second signal delay element 103 b or of the inverter 106 , respectively—additionally connected via a line 115 a with the input of a gate 116 a “of the first kind”, as will be explained more exactly in the following.
  • the outputs of the remaining signal delay elements 103 c , 103 d , 103 e each are connected via corresponding lines 115 d , 115 e with the respective input of corresponding further gates 116 d , 116 e , namely, generally speaking, the respective outputs of those signal delay elements 103 c , 103 d in which n is an odd number are connected with the input of a corresponding gate 116 d “of the first kind”, and the outputs of those signal delay elements 103 c , 103 d in which n is an even number are connected with the input of a corresponding gate 116 e “of the second kind”.
  • the inverter circuit arrangement (in particular a tristate inverter circuit arrangement) illustrated in detail in FIG. 3 is e.g. used as a gate 116 a , 116 d “of the first kind”
  • the transfer gate circuit arrangement illustrated in detail in FIG. 4 is e.g. used as a gate 116 b , 116 e “of the second kind”.
  • the transfer gate circuit arrangement of the gates 116 b , 116 e “of the second kind” comprises an n-channel field effect transistor 120 a and a p-channel field effect transistor 120 b.
  • the control signal C 2 available at a control input 119 b of the respective gate 116 b , 116 e is—via a control line 121 a —supplied to the gate of the n-channel field effect transistor 120 a.
  • control signal C 2 available at the control input 119 b of the respective gate 116 b , 116 e is additionally—via a line 121 b —supplied to the input of an inverter 122 , and the control signal /C 2 output at the output of the inverter 122 and complementary to the control signal C 2 is supplied to the gate of the p-channel field effect transistor 120 b.
  • the drains of the n- or p-channel field effect transistors 120 a , 120 b are connected via a line 123 with one another and additionally to the line 115 b (and thus form the input of the transfer gate circuit arrangement).
  • the sources of the n- or p-channel field effect transistors 120 a , 120 b are connected with one another via a line 124 , and additionally with a line 117 b that is connected to a line 118 (and thus form the output of the transfer gate circuit arrangement).
  • the signal available at the control input 119 b of the gate 116 b again changes its state from “logically high” to “logically low” (and thus the complementary control signal /C 2 changes its state again from “logically low” to “logically high”)
  • the signal available at the input of the transfer gate circuit arrangement or of the gate 116 b is again disconnected galvanically from the output of the transfer gate circuit arrangement or of the gate 116 b , respectively, i.e. from the line 117 b.
  • the gates 116 a , 116 d “of the first kind” have a structure that is different from that of the gate 116 b “of the second kind” illustrated in FIG. 4 .
  • they comprise each two n-channel field effect transistors 126 a , 126 b and two p-channel field effect transistors 125 a , 125 b.
  • the n-channel field effect transistor 126 a and the p-channel field effect transistor 125 a have a connection similar to a conventional, simple inverter, with the exception that the drain of the n-channel field effect transistor 126 a is not directly connected to the supply voltage, but by interconnection of the n-channel field effect transistor 126 b , and that the drain of the p-channel field effect transistor 125 a is not directly connected to the mass, but by interconnection of the p-channel field effect transistor 125 b.
  • the drain of the n-channel field effect transistor 126 a is—via a line 127 —connected to the source of the n-channel field effect transistor 126 b
  • the drain of the n-channel field effect transistor 126 b is—via a line 128 —connected to the supply voltage.
  • the drain of the p-channel field effect transistor 125 a is connected—via a line 129 —to the source of the p-channel field effect transistor 125 b
  • the drain of the p-channel field effect transistor 125 b is connected—via a line 130 —to the mass.
  • the gates of the n- or p-channel field effect transistors 125 a , 126 a are connected with one another via a line 132 , and are additionally connected to the line 115 a (and thus form the input of the (tristate) inverter circuit arrangement).
  • the sources of the n- or p-channel field effect transistors 125 a , 126 a are connected with one another via a line 131 , and are additionally connected with a line 117 —which is also connected to the line 118 (and thus form the output of the (tristate) inverter circuit arrangement).
  • the control signal C 1 available at a control input 119 a of the respective gate 116 a , 116 d is—via a control line 133 a —supplied to the gate of the n-channel field effect transistor 126 b.
  • control signal C 1 available at the control input 119 a of the respective gate 116 a , 116 c is additionally supplied to the input of an inverter 134 via a line 133 b
  • control signal /C 1 that is output at the output of the inverter 134 and that is complementary to the control signal C 1 is additionally supplied to the gate of the p-channel field effect transistor 125 b.
  • the control signal C 1 available at the control input 119 a of the gate 116 a then changes its state from “logically low” to “logically high” (and thus the complementary control signal /C 1 changes its state from “logically high” to “logically low”), the n- and the p-channel field effect transistors 125 b , 126 b are switched on (and thus the simple inverter formed by the n- and the p-channel field effect transistors 125 a , 126 a is connected with the supply voltage or the mass, respectively, i.e. is de-activated).
  • the signal available at the input of the gate 116 a i.e. at the line 115 a , is advanced in inverted form to the output of the gate 116 a , i.e. to the line 117 a , with the respectively one of the field effect transistors 125 a , 126 a constituting the load resistance for the respectively other field effect transistor 125 a , 126 a.
  • the corresponding outputs are (in a corresponding manner to the first and second gates 116 a , 116 b ), also with the remaining gates 116 d , 116 e , connected via corresponding lines 117 d , 117 e to the line 118 which is connected to the output of the signal delay device 101 .
  • control signals C 1 , C 2 , . . . , C n ⁇ 1 , C n are applied to the control inputs 119 a, 119 b, 119 d, 119 e of the gates 116 a, 116 b, 116 d, 116 e, namely such that respectively one of the control signals C 1 , C 2 , . . . , C n ⁇ 1 , C n is in a “logically high” state, and the respectively other control signals C 1 , C 2 , . . . , C n ⁇ 1 , C n are in a “logically low” state.
  • signal delay element 103 a, 103 b, 103 c, 103 d, 103 e may be selected whose output signal—possibly in inverted form (namely in the case of signal delay elements 103 c , 103 d where n is an odd number)—is to be connected through to the output 102 b of the signal delay device 101 .
  • the signal OUT that is output at the output 102 b of the signal delay device 101 corresponds to the signal IN at the input 102 a of the signal delay device 101 ; it is, however, applied with an—adjustable—delay vis-à-vis thereto (namely with a delay corresponding to the delay time of the output signal of that signal delay element 103 a , 103 b , 103 c , 103 d , 103 e whose output—possibly in inverted form—is just being connected through via the corresponding gate 116 a , 116 b , 116 d , 116 e to the output 102
  • an additional tristate inverter circuit arrangement 135 , 136 may be connected between the output of each gate 116 a , 116 b , 116 d , 116 e (irrespective of whether “of the first kind” or “of the second kind”) and the corresponding line 117 a , 117 b , 117 d , 117 e corrected with the line 118 .
  • the respectively interposed tristate inverter circuit arrangement 135 , 136 has a structure that corresponds to the structure of the tristate inverter circuit arrangement illustrated in FIG. 3 and acting as a gate 116 a “of the first kind” there.
  • the circuits driving the lines 118 (here: the tristate inverter circuit arrangements 135 , 136 )—irrespective of which one of the gates 116 a , 116 b , 116 d , 116 e is just activated by applying a corresponding “logically high” control signal C 1 , C 2 , . . . , C n ⁇ 1 , C n —all have an identical structure, and that thus—irrespective of which one of the gates 116 a , 116 b , 116 d , 116 e is activated—a respectively identical capacitive load results.
  • a transfer gate circuit arrangement 137 may, in accordance with FIG. 6 a , be connected between the output of each gate 116 a , 116 d “of the first kind” and the corresponding additional tristate inverter circuit arrangement 135 connected with the corresponding line 117 a , 117 d , wherein said transfer gate circuit arrangement 137 may have the same structure as the transfer gate circuit arrangement illustrated in FIG. 4 and acting as a gate 116 b “of the second kind” there.
  • the above-mentioned gates 116 b , 116 e “of the second kind” may be replaced by corresponding gates 139 “of the first kind” (which may have a structure corresponding to that of the tristate inverter circuit arrangement illustrated in FIG. 3 ), and a respectively further tristate inverter circuit arrangement 138 (which may also have a structure corresponding to that of the tristate inverter circuit arrangement illustrated in FIG. 3 and acting as a gate 116 a “of the first kind” there) may be connected between these gates 139 “of the first kind” and the corresponding additional tristate inverter circuit arrangement 136 connected with the respective line 117 b , 117 e.
  • The—interposed—transfer gate 137 illustrated in FIG. 6 a may be designed such that the signals are advanced in such a delayed manner by the transmission gate 137 that the—total—delay time occurring during the advancement of the corresponding signals by the gate 116 a , the transfer gate circuit arrangement 137 , and the tristate inverter circuit arrangement 135 illustrated in FIG. 6 a is as great as the—total—delay time occurring during the advancement of the corresponding signals by the gate 139 , and the two tristate inverter circuit arrangements 138 , 136 illustrated in FIG. 6 b.

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DE10241982A DE10241982B4 (de) 2002-09-11 2002-09-11 Digitale Signal-Verzögerungs-Einrichtung
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US20080068060A1 (en) * 2006-09-14 2008-03-20 Keven Hui Low-Power, Programmable Multi-Stage Delay Cell
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