US6839287B2 - Method of storing a quantity of data in a target memory location and storage system - Google Patents

Method of storing a quantity of data in a target memory location and storage system Download PDF

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Publication number
US6839287B2
US6839287B2 US10/653,536 US65353603A US6839287B2 US 6839287 B2 US6839287 B2 US 6839287B2 US 65353603 A US65353603 A US 65353603A US 6839287 B2 US6839287 B2 US 6839287B2
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Prior art keywords
memory location
buffer memory
volatile buffer
storing
data
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US20040076046A1 (en
Inventor
Franz-Josef Brücklmayr
Christian May
Wolfgang Pockrandt
Holger Sedlak
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Infineon Technologies AG
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Infineon Technologies AG
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
    • G11C16/105—Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Definitions

  • the present invention relates to the storing of information, and in particular to the secure storing of information in an environment subject to fault-liability.
  • non-volatile storing of information there may occur data losses or even arbitrary changes of data.
  • the storing operation usually consisting in clearing of the old information and writing of the new information, takes place over a relatively long period of time, disturbances may take place in particular, for example, in case of voltage dips in the supply of the memory chip, in the supply of bus lines or in the supply of the memory delivering the data to be stored.
  • the storage operation will not be performed correctly, and the result will be dependent on the manner in which the storage operations were carried out, or in other words, on the programming conditions and the type and time of the disturbances.
  • U.S. Pat. No. 4,922,456 relates to a method of reducing wearout in a non-volatile memory with double buffer.
  • information to be stored is written to a double buffer in order to be able in case of a disturbance to reconstruct the steps to be performed during the write operation.
  • a flag is set indicating that the double buffer is valid.
  • the data from the double buffer are then written to the appropriate locations of a non-volatile memory. Finally, the flag is cleared so that the memory management system knows that it is no longer the data in the double buffer that are valid, but the data in the non-volatile memory.
  • Such methods make use of parallel memory locations in which the information is stored in alternating manner so that the initial state is retained at all times during the storing operation.
  • the progress of the programming operation is maintained by means of flags. These flags always designate the memory location with the currently valid information.
  • the setting on non-volatile flags in turn necessitates non-volatile programming operations that have to be secured against disturbances.
  • the entire sequence thus is composed of quite a number of non-volatile storing operations necessitating considerable expenditure in time.
  • the point is reached relatively late at which the new information is present in such a form that it may be used, after elimination of a disturbance, as starting basis for a correction operation.
  • the operation largely follows steps that have the sole function in case of a disturbance to rescue the old information. In addition thereto, the expenditure for programming the flags etc. must not be overlooked either.
  • EP 0 489 204 B1 discloses a data storage device, such as a disk drive or a tape drive, adapted to be reprogrammed with a new program code. At least part of the non-volatile memory of the data storage device is a flash memory, with the data management system being designed to first program a new program code in a RAM data buffer. Thereafter, it is determined whether the entire new program code has been received and stored in the data buffer. The flash memory is then cleared, whereupon the new program code is transferred from the data buffer to the flash memory.
  • the RAM buffer is a volatile memory so that, within the period of time in which the data are kept in the RAM buffer, a data loss may occur due to voltage variations or voltage dips at the RAM buffer.
  • EP 0 489 204 B1 it is necessary according to EP 0 489 204 B1 before the step of transferring the new program code from the data buffer to the flash memory to carry out an additional examination step in order to find out whether or not the data have been corrupted during their time in the RAM buffer.
  • This examination step or these examination steps in turn lead to increased expenditure and thus to an increased demand of time in storing information or, alternatively, to a RAM memory with particularly secured voltage supply, which in turn involves much time, is expensive and often is difficult to integrate in an overall system. In addition thereto, it is necessary to prepare examination algorithms for the data.
  • this object is achieved by a method of storing a quantity of data in a target memory location, comprising the steps of:
  • a storage system comprising:
  • the present invention is based on the realization that the buffer does not have to be implemented as a non-volatile buffer to make sure that the data stored in the buffer are not corrupted during the “intermediate storage” thereof.
  • the quantity of data to be transferred is stored first in a non-volatile buffer memory location. Thereafter, it is examined whether the data have been stored successfully in the non-volatile buffer memory location. Only if the examination step produces a positive result will the target memory location for storing the predetermined quantity of data be cleared. This means that the old data are cleared only after it has been ensured that the new data have arrived in the non-volatile buffer without corruption thereof. Power failure will at no place cause total data loss, since both the old data, which are stored in the target memory location, and the new data, which are stored in the buffer, are secured against power failures. The old data are cleared only after the new data have arrived in the buffer.
  • the data are then transferred from the non-volatile buffer memory location to the target memory location.
  • the new data then are available in the target memory location, and are available for a party interested therein. According to the invention, however, the non-volatile buffer memory location is cleared now at the end of the cycle.
  • non-volatile buffer memories With non-volatile buffer memories, clearing of the data takes a considerable amount of time. Due to the fact that, according to the invention, such clearing is carried out at the end of a storage cycle, the time necessary therefor does not make itself felt since the data to be stored are already present in the target memory location. On the other hand, clearing of the non-volatile buffer memory location may be utilized for obtaining quality control of the entire storage operation so to speak automatically and without additional expenditure. A completely cleared buffer memory location indicates successful termination of a storage operation, whereas a situation in which the buffer memory location is not completely cleared, indicates that problems have occurred and that, possibly, the storage operation will have to be repeated once more.
  • an examination preferably is made to the effect whether the buffer memory location is empty or whether the buffer memory location contains data that actually should not be there, so that no subsequent storage operations can be carried out if the preceding storage operation has not been concluded correctly with a completely cleared buffer memory location.
  • An advantage of the present invention consists in that the entire storage cycle may be reconstructed fully at any time.
  • the data in the target memory location are cleared only after the data have been stored in the buffer memory location that is non-volatile and thus is not vulnerable. If, in contrast thereto, storing in the non-volatile buffer memory location is not carried out successfully, this is recognized by the examination, and storing of the data in the non-volatile buffer memory location may simply be repeated.
  • quality control is carried out already at an early stage of the storage cycle, and this is the sole necessary quality control since, if the target memory location is a non-volatile memory as well, all data of interest, as of this time, are present in non-volatile memories only and thus are secured.
  • An additional advantage of the present invention consists in that, merely by sequentially performing the various operations, a storage operation is created which is secure on the one hand and on the other hand does not need non-volatile flags involving programming expenditure.
  • a storage operation is created which is secure on the one hand and on the other hand does not need non-volatile flags involving programming expenditure.
  • automatic quality control of the entire storage cycle is achieved that does not make itself felt in terms of time as the data are available in the target memory location already prior thereto.
  • the data stored in the target memory location are thus already available before the complete storage cycle is concluded by clearing of the non-volatile buffer memory location.
  • FIG. 1 shows a block diagram of a storage system according to the invention
  • FIG. 2 shows a flow chart of a method according to the invention for storing a quantity of data in a target memory location according to the present invention.
  • FIG. 1 illustrates a storage system according to the invention comprising a non-volatile buffer memory 10 , a target memory 12 and a control means 14 .
  • Non-volatile buffer memory 10 may be fed with data from a source memory via a data bus 16 .
  • a further data bus 18 present between non-volatile buffer memory 10 and target memory 12 .
  • data may also be transferred directly from source memory 20 to target memory 12 , for example in a fast storing mode involving compromises as to security.
  • Control means 14 is connected furthermore via control lines 22 , 24 and 26 to the source memory 20 , the non-volatile buffer memory 10 and the target memory 12 , respectively, e.g. for providing for the possibilities of performing addressing operations, carrying out examinations in the non-volatile buffer memory 10 or e.g. obtaining simple return information on specific operations.
  • FIG. 2 shows a flow chart performed by the control means 14 according to the present invention in order to transfer a quantity of data from source memory 20 to target memory 12 .
  • the data quantity is fed first to the non-volatile buffer memory 10 ( 40 ). Thereafter, it is examined in a decision block 50 whether or not storing was OK. If storing was not okay, i.e. if a problem occurred during storing or at any other point, the sequence follows a loop 55 in order to repeat the storing operation (block 40 ).
  • step 50 If in contrast thereto it is determined in block 50 that storing in the non-volatile buffer memory was OK, the sequence jumps to a block 60 in which control means 14 clears the target memory location into which the data to be stored are to be written, which data are meanwhile located in the non-volatile buffer memory 10 (FIG. 1 ). Thereafter, the data are transferred from the buffer memory to the target memory (block 70 ). In a block 80 , it may be determined optionally whether this transfer was OK. If this question is answered in the negative, step 70 is repeated by way of a loop 75 . If, in contrast thereto, it is determined that the transfer was OK, the sequence jumps to a block 90 in which the non-volatile buffer memory is cleared. As was already elucidated, it is possible alternatively to proceed from block 70 to block 90 directly, as indicated by an arrow 85 in broken lines, which is possible without great risk in so far as the buffer memory is a non-volatile memory.
  • one storage cycle is completed. Either subsequent to the storage cycle or before execution of a new storage cycle only, it may be examined in a block 100 whether or not the non-volatile buffer memory location ( 10 in FIG. 1 ) is cleared completely. If this question is answered in the affirmative, the sequence can jump via a loop 105 to start block 30 in order to begin storing of a new quantity of data since the “old” quantity of data has been stored successfully in the target memory which preferably is a non-volatile memory. If, in contrast thereto, the question in block 100 is answered in the negative, clearing of the non-volatile buffer memory may be repeated once more via a loop 95 . This procedure makes sense if the examination via block 80 has been carried out.
  • the information to be transferred is deposited in non-volatile buffer memory 10 (FIG. 1 ), with each item of information having a specific memory location associated therewith in target memory 12 .
  • This association can be stored in non-volatile buffer memory 10 directly by way of additional information associated with the data quantity, so that the control means 14 proper need not contain a table indicating where the data from source memory 20 are to be stored in target memory 12 .
  • a string fully characterizing the information to be stored thus is preferably stored in the non-volatile buffer memory in non-volatile manner.
  • CRC cyclic redundancy check
  • the step of examining whether the data have been successfully stored in the non-volatile buffer memory location may be carried out, if a CRC is stored as well, simply by calculating the check sum from the data stored in the buffer memory location and by comparing the same to check sum stored as well. If both check sums are identical, it may be presumed that the data have arrived correctly in the non-volatile buffer memory.
  • the target memory 12 is then cleared, whereupon the information of the buffer memory is written to the target memory.
  • the additional data may be written to the target memory as well in order to carry out a new examination.
  • this is not absolutely necessary as no data losses are to be expected in the buffer memory since the same is a non-volatile memory and, thus, secure conditions may be presumed once the data have arrived correctly in the non-volatile buffer memory.
  • the programming operations in this regard preferably take place sequentially, with each next programming operation being started only after the preceding one has been concluded completely and successfully.
  • the storing operation according to the invention thus consists in total of four operations to be programmed and an examination, as compared to the two operations that would be necessary for a storing operation without protective measures. However, the expenditure according to the invention still is considerably lower than if, for example, programming operations of flags are necessary.
  • the procedure according to the invention is advantageous in so far as the storage operation at all times may be reconstructed completely once just the first programming, i.e. the transfer of the data from the source memory to the non-volatile buffer memory, is successfully concluded. If the same cannot be successfully concluded, the old information definitely is available without the risk of impairment, as the target memory location 12 has not yet been touched upon.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Read Only Memory (AREA)
US10/653,536 2001-03-02 2003-09-02 Method of storing a quantity of data in a target memory location and storage system Expired - Lifetime US6839287B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10110153 2001-03-02
DE10110153.8 2001-03-02
PCT/EP2001/014348 WO2002071409A1 (de) 2001-03-02 2001-12-06 Verfahren zum einspeichern einer datenmenge in einen zielspeicherbereich und speichersystem

Related Parent Applications (1)

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PCT/EP2001/014348 Continuation WO2002071409A1 (de) 2001-03-02 2001-12-06 Verfahren zum einspeichern einer datenmenge in einen zielspeicherbereich und speichersystem

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US6839287B2 true US6839287B2 (en) 2005-01-04

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EP (1) EP1350252B1 (ja)
JP (1) JP2004519057A (ja)
CN (1) CN100380526C (ja)
AT (1) ATE269578T1 (ja)
CA (1) CA2420791A1 (ja)
DE (1) DE50102646D1 (ja)
TW (1) TW569091B (ja)
WO (1) WO2002071409A1 (ja)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040054851A1 (en) * 2002-09-18 2004-03-18 Acton John D. Method and system for dynamically adjusting storage system write cache based on the backup battery level
US20050071697A1 (en) * 2003-09-30 2005-03-31 Batchelor Gary William System,apparatus, and method for limiting non-volatile memory
KR100808948B1 (ko) * 2006-12-19 2008-03-04 삼성전자주식회사 비휘발성 메모리의 보안장치 ,보안방법 및 그 시스템
US20110087852A1 (en) * 2008-06-17 2011-04-14 Nxp B.V. Method of and system for controlling the programming of memory devices
US8788880B1 (en) 2012-08-22 2014-07-22 Western Digital Technologies, Inc. Efficient retry mechanism for solid-state memory failures
US10162558B2 (en) 2015-10-30 2018-12-25 Micron Technology, Inc. Data transfer techniques for multiple devices on a shared bus

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7896891B2 (en) * 2005-05-20 2011-03-01 Neotract, Inc. Apparatus and method for manipulating or retracting tissue and anatomical structure
KR101627322B1 (ko) * 2009-11-18 2016-06-03 삼성전자주식회사 비-휘발성 버퍼를 이용한 데이터 저장 장치 및 방법
US11197028B2 (en) * 2017-03-13 2021-12-07 Sling Media Pvt Ltd Recovery during video encoding

Citations (6)

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US4433395A (en) 1980-05-06 1984-02-21 Matsushita Electric Industrial Co., Ltd. Apparatus and method for refreshing non-volatile memory
US4922456A (en) 1988-04-29 1990-05-01 Scientific-Atlanta, Inc. Method of reducing wearout in a non-volatile memory with double buffer
EP0489204A1 (en) 1990-12-04 1992-06-10 Hewlett-Packard Limited Reprogrammable data storage device
US5226168A (en) * 1989-04-25 1993-07-06 Seiko Epson Corporation Semiconductor memory configured to emulate floppy and hard disk magnetic storage based upon a determined storage capacity of the semiconductor memory
US6035347A (en) 1997-12-19 2000-03-07 International Business Machines Corporation Secure store implementation on common platform storage subsystem (CPSS) by storing write data in non-volatile buffer
JP2000305862A (ja) 1999-02-19 2000-11-02 Mitsubishi Electric Corp データ記憶方法および情報処理装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4433395A (en) 1980-05-06 1984-02-21 Matsushita Electric Industrial Co., Ltd. Apparatus and method for refreshing non-volatile memory
US4922456A (en) 1988-04-29 1990-05-01 Scientific-Atlanta, Inc. Method of reducing wearout in a non-volatile memory with double buffer
US5226168A (en) * 1989-04-25 1993-07-06 Seiko Epson Corporation Semiconductor memory configured to emulate floppy and hard disk magnetic storage based upon a determined storage capacity of the semiconductor memory
EP0489204A1 (en) 1990-12-04 1992-06-10 Hewlett-Packard Limited Reprogrammable data storage device
US6035347A (en) 1997-12-19 2000-03-07 International Business Machines Corporation Secure store implementation on common platform storage subsystem (CPSS) by storing write data in non-volatile buffer
JP2000305862A (ja) 1999-02-19 2000-11-02 Mitsubishi Electric Corp データ記憶方法および情報処理装置

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040054851A1 (en) * 2002-09-18 2004-03-18 Acton John D. Method and system for dynamically adjusting storage system write cache based on the backup battery level
US6957355B2 (en) * 2002-09-18 2005-10-18 Sun Microsystems, Inc. Method and system for dynamically adjusting storage system write cache based on the backup battery level
US20050071697A1 (en) * 2003-09-30 2005-03-31 Batchelor Gary William System,apparatus, and method for limiting non-volatile memory
US7051223B2 (en) * 2003-09-30 2006-05-23 International Business Madnine Corporation System, apparatus, and method for limiting non-volatile memory
KR100808948B1 (ko) * 2006-12-19 2008-03-04 삼성전자주식회사 비휘발성 메모리의 보안장치 ,보안방법 및 그 시스템
US20110087852A1 (en) * 2008-06-17 2011-04-14 Nxp B.V. Method of and system for controlling the programming of memory devices
US8631218B2 (en) 2008-06-17 2014-01-14 Nxp, B.V. Method of and system for controlling the programming of memory devices
US8788880B1 (en) 2012-08-22 2014-07-22 Western Digital Technologies, Inc. Efficient retry mechanism for solid-state memory failures
US10162558B2 (en) 2015-10-30 2018-12-25 Micron Technology, Inc. Data transfer techniques for multiple devices on a shared bus
US10635342B2 (en) 2015-10-30 2020-04-28 Micron Technology, Inc. Data transfer techniques for multiple devices on a shared bus
US10671310B2 (en) 2015-10-30 2020-06-02 Micron Technology, Inc. Data transfer techniques for multiple devices on a shared bus
US11762570B2 (en) 2015-10-30 2023-09-19 Micron Technology, Inc. Data transfer techniques for multiple devices on a shared bus

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Publication number Publication date
ATE269578T1 (de) 2004-07-15
JP2004519057A (ja) 2004-06-24
CN1493078A (zh) 2004-04-28
EP1350252A1 (de) 2003-10-08
TW569091B (en) 2004-01-01
CA2420791A1 (en) 2003-02-05
DE50102646D1 (de) 2004-07-22
US20040076046A1 (en) 2004-04-22
EP1350252B1 (de) 2004-06-16
WO2002071409A1 (de) 2002-09-12
CN100380526C (zh) 2008-04-09

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