US6830980B2 - Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions - Google Patents
Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions Download PDFInfo
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- US6830980B2 US6830980B2 US10/393,419 US39341903A US6830980B2 US 6830980 B2 US6830980 B2 US 6830980B2 US 39341903 A US39341903 A US 39341903A US 6830980 B2 US6830980 B2 US 6830980B2
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
Definitions
- the present invention relates generally to semiconductor devices and more particularly to manufacturing semiconductor devices using carbon-containing regions formed in a wafer.
- MOS and other types of transistors are found in many modern semiconductor products where switching and/or amplification functions are needed.
- Many manufacturing processes and techniques have been developed for forming MOS transistors and other electrical components in semiconductor substrate materials such as silicon and the like to produce semiconductor devices.
- semiconductor substrate materials such as silicon and the like to produce semiconductor devices.
- the size of transistors and other components have steadily decreased to submicron levels in order to facilitate higher device densities in semiconductor products.
- many applications of such devices have created a need to operate the semiconductor devices at higher speeds and lower power and voltage levels.
- various regions of semiconductor material are selectively doped with impurities to create ‘p-type’ or ‘n-type’ regions, such as wells, source/drain regions, lightly-doped drain (LDD) regions, pocket or halo regions, etc., where the type (e.g., ‘p’ or ‘n’) depends upon the dopants employed.
- P-type regions are typically created using dopants such as boron, indium or others, whereas n-type regions are created using phosphorus, arsenic, antimony, etc.
- Such doping is generally accomplished through dopant diffusion techniques and/or through implantation processes, whereby dopants of a desired concentration are ideally provided to specific regions or areas of a semiconductor body. This selective doping allows semiconductor devices, such as transistors to be fabricated in a controlled and repeatable fashion to achieve desired operating performance specifications.
- dopants tend to relocate through thermal diffusion in a semiconductor material, causing difficulties in the manufacture of semiconductor devices, and potentially degrading device performance. For instance, dopant out-diffusion from shallow junction extension and pocket or halo implanted regions of MOS transistors during thermal processing can degrade the achievable transistor drive current capability by reducing mobility in the channel region underlying the transistor gate. Accordingly, the locations and concentrations of such dopants may be tailored according to the thermal processing that a semiconductor wafer experiences after the dopants are introduced. In this manner, desired dopant location and concentrations can be achieved when the fabrication process is completed. However, the ability to control exact concentrations and locations of dopants is made more difficult by the tendency of dopants to diffuse during thermal manufacturing processing steps.
- diffusion barriers or regions of diffusion inhibiting materials may be formed in certain regions of the semiconductor material.
- carbon-containing regions may be formed for inhibiting or mitigating dopant diffusion, such as layers of carbon-containing epitaxial silicon or regions of a semiconductor body implanted with carbon-containing species.
- the effectiveness of the carbon-containing region with respect to inhibiting dopant diffusion is dependent upon the location and concentration of carbon.
- the presence of carbon in certain regions or locations of a semiconductor body may adversely affect device performance or the ability to process a wafer during manufacturing.
- the following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention.
- This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof.
- the invention relates to semiconductor device fabrication methods in which a carbon-containing region is formed in a wafer to inhibit or mitigate diffusion of dopants during fabrication.
- the inventors have appreciated that the provision of carbon or carbon-containing species to a region of a semiconductor body (e.g., through implantation or other techniques) generally results in both substitutional carbon and interstitial carbon, where interstitial carbon in particular tends to out-diffuse from its original location during thermal processing.
- the out-diffusion/deactivation of carbon reduces the ability to inhibit thermal out-diffusion of dopants (e.g., boron, phosphorus, or others) during the manufacturing process.
- dopants e.g., boron, phosphorus, or others
- the carbon out-diffusion or deactivation may lead to subsequent generation of surface defects, reduced oxidation rates, or otherwise adversely impact operations affecting the wafer surface.
- front-end thermal processing operations including oxidation and/or anneal processes, are performed at high temperatures for short durations in order to mitigate out-diffusion of carbon from the carbon-containing region, such that carbon remains to inhibit or reduce dopant diffusion.
- the invention may be employed to provide increased control of dopant location and concentration to thereby facilitate control and repeatability of semiconductor device performance.
- the invention may be used to prevent or mitigate diffusion of carbon to the surface of a wafer, and thus to facilitate expeditious oxidation rates during manufacturing.
- a method of fabricating a semiconductor device comprising forming a carbon-containing region in the wafer, and performing at least one front-end oxidation or anneal process using a high temperature, short duration thermal process to mitigate out-diffusion of carbon from the carbon-containing region during front-end fabrication processing.
- the carbon-containing region may be formed by any technique, including but not limited to implanting carbon or a carbon-containing species in the wafer or growing an epitaxial carbon-containing layer over a semiconductor body, with or without an overlying epitaxial cap layer.
- the short duration, high temperature oxidations may include formation of a pad oxide layer and/or a liner oxide layer during isolation processing (e.g., shallow trench isolation (STI) processing), and/or formation of a gate oxide or gate dielectric layer during front-end processing.
- the elevated temperature oxidations may be performed at temperatures of about 1000 degrees C. or more for a duration of about 60 seconds or less, at a pressure of about 10 Torr or less.
- the front end processing may alternatively or in combination comprise performing an anneal, such as a channel implant damage anneal process at a temperature of about 1050 degrees C. or more for a duration of about 60 seconds or less.
- the front-end thermal processing moreover, may include in-situ steam generation oxidation or anneal processes.
- the invention thus provides for reducing the overall front-end thermal budget of a semiconductor device manufacturing process, which may be employed to inhibit carbon out-diffusion or deactivation, by which the prevention or reduction in the amount of dopant out-diffusion or relocation can be
- FIG. 1 is a flow diagram illustrating an exemplary method of fabricating semiconductor devices in accordance with one or more aspects of the present invention
- FIG. 2 is a partial side elevation view in section illustrating formation of a carbon-containing layer over a silicon substrate in an exemplary semiconductor device
- FIG. 3 is a partial side elevation view in section illustrating formation of a cap layer over the carbon-containing layer in the device of FIG. 2;
- FIG. 4 is a partial side elevation view in section illustrating formation of a pad oxide layer using a high temperature, short duration oxidation process in accordance with an aspect of the invention, as well as formation of an overlying nitride layer in the device of FIGS. 2 and 3;
- FIG. 5 is a partial side elevation view in section illustrating formation of an isolation trench in the device of FIGS. 2-4;
- FIG. 6 is a partial side elevation view in section illustrating formation of a liner oxide layer in the isolation trench using a high temperature, short duration oxidation process in accordance with another aspect of the invention in the device of FIGS. 2-5;
- FIG. 7 is a partial side elevation view in section illustrating formation of an isolation structure in the trench of the device of FIGS. 2-6;
- FIG. 8 is a partial side elevation view in section illustrating performance of one or more channel implants in the device of FIGS. 2-7;
- FIG. 9 is a partial side elevation view in section illustrating performance of a high temperature, short duration channel damage anneal in the device of FIGS. 2-8;
- FIG. 10 is a partial side elevation view in section illustrating formation of a gate oxide layer using a high temperature, short duration oxidation process in accordance with yet another aspect of the invention in the device of FIGS. 2-9;
- FIG. 11 is a partial side elevation view in section illustrating formation of a gate contact layer over the gate oxide layer in the device of FIGS. 2-10;
- FIG. 12 is a partial side elevation view in section illustrating patterning of the gate oxide and gate contact layers to form a gate structure in the device of FIGS. 2-11;
- FIG. 13 is a partial side elevation view in section illustrating performance of one or more LDD implants in the device of FIGS. 2-12;
- FIG. 14 is a partial side elevation view in section illustrating performance of one or more halo or pocket implants in the device of FIGS. 2-13;
- FIG. 15 is a partial side elevation view in section illustrating formation of gate sidewall spacers in the device of FIGS. 2-14;
- FIG. 16 is a partial side elevation view in section illustrating performance of one or more source/drain implants in the device of FIGS. 2-15;
- FIG. 17 is a partial side elevation view in section illustrating formation of silicide contacts at the source/drains and the gate of the device of FIGS. 2 - 16 .
- the invention relates to methods for fabricating semiconductor devices with carbon-containing regions, in which front-end oxidation and/or anneal operations are performed at high temperatures for short durations in order to mitigate out-diffusion of carbon from the carbon-containing region, such that carbon remains to inhibit or mitigate dopant diffusion.
- the invention may also be employed in situations where carbon-containing regions are used to inhibit diffusion or other relocation of any dopant species, n-type and/or p-type, where the carbon-containing region may be located anywhere in a semiconductor device wafer, whether beneath the surface or at the surface thereof.
- the structures illustrated in the various drawing figures are not necessarily drawn to scale.
- an exemplary method 2 is illustrated for fabricating a semiconductor device in a wafer in accordance with one or more aspects of the invention.
- the method 2 is illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention.
- not all illustrated steps may be required to implement a methodology in accordance with the present invention.
- the methods according to the present invention may be implemented in association with the formation and/or processing of structures illustrated and described herein as well as in association with other structures and devices not illustrated.
- the method 2 is illustrated in somewhat simplified form, wherein other steps may be performed, which are not specifically illustrated or described herein.
- the method 2 comprises forming a carbon-containing region in the wafer at 6 , which is a carbon-containing epitaxial silicon layer grown over a semiconductor body in the illustrated example.
- a carbon-containing region may be formed by implanting carbon or a carbon-containing species in the wafer.
- the method 2 may be carried out beginning with a silicon substrate, SOI wafer, or other semiconductor body.
- a carbon layer, a carbon doped silicon layer, or a silicon-germanium-carbon (SiGeC) layer is formed over the wafer surface, for example, having a carbon concentration of about 0.1 atomic percent or more.
- the carbon-containing layer is formed at 6 to a layer thickness between about 10 and 1000 ⁇ , for example, about 100-500 ⁇ .
- concentrations and layer thicknesses are possible within the scope of the invention.
- a silicon epitaxial cap layer may optionally be formed at 8 over the carbon-containing layer.
- the carbon-containing layer and the cap layer may be formed sequentially in a continuous process, for example, in a rapid thermal chemical vapor deposition (CVD) tool.
- the process chemistry may be changed between steps 6 and 8 , for instance, to stop incorporating carbon or carbon-containing species in the process chemistry, such that the cap layer at 8 contains little or no carbon.
- the cap layer is formed at 8 to a thickness of about 400-500 ⁇ .
- the cap layer can be of any appropriate thickness and composition, or may be omitted altogether within the scope of the invention.
- the carbon-containing region can be formed through implantation of carbon or carbon-containing species in the semiconductor body. Any appropriate implantation parameters, such as concentration and implantation energy may be employed in accordance with the invention, wherein the region of interest may be provided with a carbon concentration of about 0.1 atomic percent or more in one example, and wherein the thickness of the carbon-containing region can be about 10-1000 ⁇ , such as about 100-500 ⁇ . For example, where it is desired to control dopant diffusion into a transistor channel region, the carbon-containing region can be situated directly beneath the channel or any desired depth below the channel.
- concentration and implantation energy may be employed in accordance with the invention, wherein the region of interest may be provided with a carbon concentration of about 0.1 atomic percent or more in one example, and wherein the thickness of the carbon-containing region can be about 10-1000 ⁇ , such as about 100-500 ⁇ .
- the carbon-containing region can be situated directly beneath the channel or any desired depth below the channel.
- the carbon-containing region implant can be performed in selective fashion, and may be done at an angle, so as to provide a carbon-containing region anywhere in the wafer to prevent or inhibit dopant diffusion from any doped region to a protected region of interest in accordance with the present invention.
- the carbon-containing region is provided to prevent or inhibit dopant diffusion into the prospective transistor channel region.
- carbon-containing regions may alternatively or in combination be provided via formation of carbon-containing layers and/or implantation of carbon or carbon-containing species to prevent or inhibit dopant diffusion out of any region of a semiconductor device, including but not limited to shallow junction extension regions (e.g., LDD, HDD, etc.), deep source/drain regions, doped gate structures, or other regions within the scope of the invention.
- the invention further contemplates performing at least one front-end oxidation or anneal process using a high temperature, short duration thermal process to mitigate out-diffusion of carbon from the carbon-containing region during front-end fabrication processing.
- a pad oxide layer is formed at 10 using such an oxidation process at a temperature of about 1000 degrees C. or more for a duration of about 60 seconds or less, although other elevated temperatures and short durations are contemplated as falling within the scope of the invention.
- the pad oxide layer is formed through oxidation at about 1050 degrees C. or more, preferably about 1100 degrees C. or more for a duration of less than 60 seconds, such as about 30 seconds or less.
- the pad oxide process at 10 may be performed at a pressure of about 10 Torr or less.
- the process at 10 is an in-situ steam generation (ISSG) oxidation process.
- the pad oxide layer may be grown to any desired thickness at 10 , which functions to relieve stress between the underlying semiconductor body (e.g., the carbon-containing epitaxial layer or the epitaxial cap layer in this example) and a hard mask nitride layer formed thereover for shallow trench isolation (STI) processing.
- STI shallow trench isolation
- a nitride layer may be formed over the pad oxide layer at 10 , wherein the nitride layer operates as a hard mask in subsequent isolation processing, and may be formed using any appropriate deposition techniques and materials, such as Si 3 N 4 deposited by low pressure chemical vapor deposition (LPCVD).
- LPCVD low pressure chemical vapor deposition
- Isolation trenches are then formed at 12 , to be subsequently filled with insulating material as part of the STI processing, wherein the trench formation at 12 may include any appropriate processing.
- a resist layer is formed over the nitride layer and patterned to form a patterned mask exposing isolation regions of the nitride layer, while covering active regions thereof, in which the patterning of the resist mask may be done according to any appropriate photolithography techniques.
- An isolation trench may then be dry etched using the patterned mask using any appropriate etching techniques such as reactive ion etching (RIE).
- RIE reactive ion etching
- a single or multi-step RIE etch process may be performed which removes material in the exposed isolation regions so as to etch through the nitride layer, the underlying pad oxide, and into the epitaxial carbon-containing and cap layers, and which may proceed to etch into the underlying semiconductor body to form a trench.
- a liner oxide layer is formed at 14 using a high temperature, short duration oxidation process in accordance with the invention.
- the liner oxide layer is formed through oxidation of the trench bottom and sidewalls at 14 at a temperature of about 1000 degrees C. or more for a duration of about 60 seconds or less, although other elevated temperatures and short durations are contemplated as falling within the scope of the invention.
- the liner oxide layer is formed through oxidation at about 1050 degrees C. or more, preferably about 1100 degrees C. or more for a duration of less than 60 seconds, such as about 30 seconds or less.
- the liner oxide process at 14 may be performed at a pressure of about 10 Torr or less, wherein the process at 14 may be an in-situ steam generation (ISSG) oxidation process.
- ISSG in-situ steam generation
- the STI trenches are filled with dielectric material such as SiO 2 or other electrically isolating material so as to provide electrical isolation between active regions on either side of the isolation trench.
- the trench filling operation at 16 may comprise forming or depositing dielectric material over the wafer to cover the nitride layer in the active regions and to fill the trenches in the isolation regions thereof.
- the trench fill material may be deposited at 16 using any appropriate deposition techniques, for example, such as high density plasma (HDP) oxide deposition, low pressure chemical vapor deposition (LPCVD) employing a tetraethylorthosilicate (TEOS) gas, or plasma enhanced chemical vapor deposition (PECVD) of silicon dioxide from TEOS and oxygen mixtures (PETEOS).
- HDP high density plasma
- LPCVD low pressure chemical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- the wafer is then planarized at 18 to expose a portion of the nitride layer in the active regions, leaving a generally planar upper surface with portions of the nitride layer and a remaining portion of the fill material in the trenches exposed.
- the remaining nitride material is then stripped or removed at 18 , for example, using a wet etch process selective so as to remove nitride material and to stop on the pad oxide layer without damaging the underlying cap layer material in the active regions of the device.
- the pad oxide layer may be removed using an oxide deglaze or other suitable oxide removal operation at 18 .
- one or more wells may be performed, such as using suitable implantation masks and processes, for example to form p-wells for NMOS transistors and n-wells for PMOS transistors, wherein multiple implants (e.g., channel stop and punch-thru implants) may be used to form retrograde wells.
- suitable implantation masks and processes for example to form p-wells for NMOS transistors and n-wells for PMOS transistors, wherein multiple implants (e.g., channel stop and punch-thru implants) may be used to form retrograde wells.
- One or more channel implants are then performed at 20 to provide dopants to the semiconductor body, the epitaxial carbon-containing silicon layer, and/or to the epitaxial silicon cap layer.
- the channel implants may comprise threshold voltage adjustment (e.g., Vt adjust) implants, and other implantations providing dopants (e.g., n and/or p type) to optimize the channel region of prospective MOS transistors, which may be selectively performed using appropriate masks and dopant types.
- one or more Vtn implants may be performed at 20 to provide p-type dopants (e.g., boron or other p-type species) to prospective NMOS regions of the wafer, with other regions masked.
- Vtp implants may be performed to implant n-type dopants (e.g., phosphorus, arsenic, or other n-type species) to prospective PMOS regions, with the NMOS and other regions masked.
- any suitable channel implants may be performed at 20 , using appropriate implantation doses, energies, and other process parameters within the scope of the invention.
- a channel implant damage anneal process is performed at 22 at high temperature for a short duration.
- the channel implant damage anneal is performed at a temperature of about 1050 degrees C. or more and a pressure of about 10 Torr or less for a duration of about 60 seconds or less to mitigate or inhibit out-diffusion of carbon from the carbon-containing region during front-end fabrication processing.
- the anneal process at 22 is performed at a temperature of about 1100 degrees C. or more for a duration of about 60 seconds or less, preferably for about 30 seconds or less.
- the anneal at 22 may be an in-situ steam generation anneal process according to the present invention.
- a gate oxide or gate dielectric layer is formed using an oxidation process at an elevated temperature for a short duration, for example, using a temperature of about 1000 degrees C. or more for a duration of about 60 seconds or less. Other temperatures and durations are contemplated as falling within the scope of the invention.
- the gate oxide layer may be formed at 24 through oxidation at about 1050 degrees C. or more, preferably about 1100 degrees C. or more for a duration of less than 60 seconds, such as about 30 seconds or less in one implementation.
- the gate oxide process at 24 may be performed at a pressure of about 10 Torr or less.
- the process at 24 is an in-situ steam generation (ISSG) oxidation process.
- ISSG in-situ steam generation
- the gate oxide layer may be grown to any desired thickness at 24 depending upon a given transistor gate design, and may comprise any type of gate oxide material, including but not limited to nitrided oxide materials, or others.
- the gate oxide layer formation at 24 may be part of a multi-step gate dielectric structure formation process flow in accordance with the invention.
- an interface oxide layer may be formed using the high-temperature, short duration oxidation process, with one or more high-k dielectric layers being formed over the interface oxide layer at 24 .
- a gate contact layer is formed over the wafer using conductive metal or polysilicon or other suitable material to any desired thickness.
- the gate contact layer is formed by deposition of polysilicon over the high-k material or the thermally grown gate oxide at 26 .
- the gate contact layer, and the gate oxide layer or layers are patterned to form a transistor gate structure.
- LDD or extension region implants are performed to provide dopants to the prospective source/drain regions on either side of the gate structures, using the patterned gate structures to self align the implanted LDD or extension regions with the gate.
- pocket or halo implants are performed using higher implantation energies than the corresponding LDD implants, to form oppositely doped pockets, preferably between the implanted LDD regions and the device channel.
- sidewall spacers are formed along the gate sidewalls, source/drain implants are performed at 36 using appropriate dose and energy parameters according to the desired transistor design, and interconnect processing is performed at 38 according to any suitable interconnect techniques, before the method 2 ends at 40 .
- a semiconductor device 100 illustrated and described hereinafter at various stages of fabrication The exemplary NMOS transistor device 100 is formed in a wafer comprising a semiconductor body 102 , which is a silicon substrate in the illustrated example. Other implementations of the invention are possible using any type of semiconductor body, such as SOI wafers or other semiconductor substrates.
- a carbon-containing region 104 is formed over the semiconductor body using a deposition process 106 (e.g., step 6 in FIG. 1 ).
- the exemplary process 106 is a rapid thermal chemical vapor deposition (CVD) process providing a carbon-containing epitaxial silicon layer 104 over the semiconductor body 102 to a thickness between about 10 and 1000 ⁇ , for example, about 100-500 ⁇ , although other processes may be performed in accordance with the invention.
- a silicon epitaxial cap layer 108 may optionally be formed over the carbon-containing layer 104 using the same process 106 or a different deposition process 110 (e.g., step 8 above).
- the cap layer 108 is formed to a thickness of about 400-500 ⁇ .
- the cap layer can be of any appropriate thickness and composition, or may be omitted altogether within the scope of the invention.
- a high temperature, short duration thermal process 112 is employed to form a pad oxide layer 114 (e.g., step 10 above), for example, through oxidation at a temperature of about 1000 degrees C. or more for a duration of about 60 seconds or less at a pressure of about 10 Torr or less, and a nitride layer 116 is formed over the pad oxide layer 114 .
- the process at 112 is an in-situ steam generation (ISSG) oxidation process, wherein the pad oxide layer 114 may be grown to any desired thickness.
- ISSG in-situ steam generation
- isolation trenches are then formed using an STI trench formation process 120 , in which a resist layer 122 is formed over the nitride layer 116 and is patterned to form a mask exposing isolation regions of the nitride layer 116 , while covering active regions thereof.
- the isolation trench is then dry etched using the patterned mask 122 using any appropriate etching techniques such as reactive ion etching (RIE), which may be a single or a multi-step RIE etch process 120 .
- RIE reactive ion etching
- the process 120 removes material in the exposed isolation regions so as to etch through the nitride layer 116 , the underlying pad oxide 114 , and into the epitaxial carbon-containing and cap layers 104 and 108 , respectively.
- the trench formation etch process 120 proceeds to etch into the underlying semiconductor body 102 to form the trench.
- a liner oxide layer 124 is formed (e.g., step 14 above) using a high temperature, short duration oxidation process 126 in accordance with the invention.
- the liner oxide layer 124 is formed through oxidation of the trench bottom and sidewalls at a temperature of about 1000 degrees C. or more for a duration of about 60 seconds or less.
- the liner oxide process 126 may be performed at a pressure of about 10 Torr or less, and wherein the process 126 may be an ISSG oxidation process.
- the STI trenches are filled with dielectric material 130 , such as SiO 2 or other electrically isolating material, using a deposition process 128 , such as HDP, LPCVD, PECVD, or other suitable deposition processes. Thereafter, the wafer is planarized, and the remaining nitride material 116 and the pad oxide layer 114 are removed, as illustrated in FIG. 7 .
- one or more wells may be performed, such as using suitable implantation masks and processes, for example to form p-wells for NMOS transistors and n-wells for PMOS transistors, wherein multiple implants (e.g., channel stop and punch-thru implants) may be used to form retrograde wells.
- one or more channel implants adjustment are performed via one or more implantation processes 132 to provide dopants to the semiconductor body 102 , the epitaxial carbon-containing silicon layer 104 , and/or to the epitaxial silicon cap layer 108 .
- a channel implant damage anneal process 134 is performed (e.g., step 22 above) at a high temperature for a short duration.
- the channel implant damage anneal 134 may be performed at a temperature of about 1050 degrees C.
- a gate oxide or gate dielectric layer 136 is formed (e.g., step 24 above) using an oxidation process 138 at an elevated temperature for a short duration, for example, using a temperature of about 1000 degrees C. or more for a duration of about 60 seconds or less.
- a gate contact layer 140 is formed over the wafer using conductive metal or polysilicon or other suitable material to any desired thickness.
- the gate contact layer 140 , and the gate oxide layer 136 are patterned to form a transistor gate structure using a mask 142 and an etch process 144 .
- one or more LDD implants 146 are performed to provide dopants to prospective source/drain regions on either side of the gate structure.
- phosphorus or arsenic dopants are implanted into LDD regions 148 on either side of the NMOS gate structure.
- pocket or halo implantation processes 150 are performed to form oppositely doped (e.g., p-type) pockets 152 between the implanted (e.g., n-type) LDD regions 148 and the device channel underlying the gate oxide 136 .
- sidewall spacers 154 are formed along the gate sidewalls, and in FIG.
- source/drain implantation processes 156 are performed to provide n-type dopants to source/drain regions 158 .
- silicide contacts 60 are formed over the source/drain regions 158 and the gate contact 140 , whereafter further interconnect processing is performed (not shown) to complete the device 100 .
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US10/393,419 US6830980B2 (en) | 2003-03-20 | 2003-03-20 | Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions |
JP2004078423A JP2004289152A (ja) | 2003-03-20 | 2004-03-18 | 炭素含有領域を有するウエハの炭素外方拡散を防止するための半導体デバイスの製造方法 |
EP04101121A EP1463101A3 (en) | 2003-03-20 | 2004-03-18 | Semiconductor device fabrication methods for inhibiting carbon out-diffusion from the semiconductor wafer |
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US10/393,419 US6830980B2 (en) | 2003-03-20 | 2003-03-20 | Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions |
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US20050085055A1 (en) * | 2003-10-17 | 2005-04-21 | Chartered Semiconductor Manufacturing Ltd. | End of range (EOR) secondary defect engineering using substitutional carbon doping |
US20050191816A1 (en) * | 2004-02-26 | 2005-09-01 | Vanderpool Aaron O. | Implanting carbon to form P-type source drain extensions |
US7023068B1 (en) * | 2003-11-17 | 2006-04-04 | National Semiconductor Corporation | Method of etching a lateral trench under a drain junction of a MOS transistor |
US20070117326A1 (en) * | 2004-07-07 | 2007-05-24 | Tan Chung F | Material architecture for the fabrication of low temperature transistor |
US20070284615A1 (en) * | 2006-06-09 | 2007-12-13 | Keh-Chiang Ku | Ultra-shallow and highly activated source/drain extension formation using phosphorus |
US20110147850A1 (en) * | 2009-12-18 | 2011-06-23 | Texas Instruments Incorporated | Carbon and nitrogen doping for selected pmos transistors on an integrated circuit |
US20110147854A1 (en) * | 2009-12-18 | 2011-06-23 | Texas Instruments Incorporated | Indium, carbon and halogen doping for pmos transistors |
US20120091506A1 (en) * | 2010-10-15 | 2012-04-19 | International Business Machines Corporation | Method and Structure for pFET Junction Profile With SiGe Channel |
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US20040185629A1 (en) | 2004-09-23 |
JP2004289152A (ja) | 2004-10-14 |
EP1463101A2 (en) | 2004-09-29 |
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