US6704373B1 - Timing recovery circuit and method in automatic equalizer - Google Patents

Timing recovery circuit and method in automatic equalizer Download PDF

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US6704373B1
US6704373B1 US09/611,484 US61148400A US6704373B1 US 6704373 B1 US6704373 B1 US 6704373B1 US 61148400 A US61148400 A US 61148400A US 6704373 B1 US6704373 B1 US 6704373B1
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response
absolute
signal
signals
precursor
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Yoshikazu Kakura
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0058—Detection of the synchronisation error by features other than the received signal transition detection of error based on equalizer tap values
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation

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  • the present invention relates to a timing recovery circuit in an automatic equalizer or the like and a timing recovery method in the same. More particularly, the present invention concerns a timing recovery performed in an automatic equalizer, in which code decision is performed by sequence estimation.
  • DDFSE Delayed Decision Feedback Sequence Estimation
  • a timing is selected such as to correspond to a maximum value of an evaluation function which is used for precursor component estimation and constituted by a division of total impulse response power level as numerator by truncation error, i.e., sum of the total impulse response power level and thermal noise power level, as denominator.
  • thermal noise power level S tno is first determined according to the intensity of received signal S r (Step 401 ). Then, by using the total power level of 1-st to (i ⁇ 1)-th (i being a natural number) ones of L impulse response signals S ir as truncation power signal level S tpow and the total Power level of i-th to (i+m ⁇ 1)-th (m being a natural number) ones of S ir as precursor power signal level S prpow , a value of that corresponds to the maximum value of
  • step 402 is determined and set as i max.
  • the above timing recovery circuit has a drawback that it is necessary to perform computations concerning the evaluation function including the division as noted above for each timing.
  • the present invention was made in order to overcome the above drawback, and its object is to provide timing recovery circuit in an automatic equalizer and a timing recovery method in the same, which are free from computations concerning any evaluation function.
  • a timing recovery circuit comprising: absolute response value signal generating means for obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; absolute value signal sum generating means for using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set and providing the total sum of the precursor candidate signal set as an absolute value signal sum; weighted absolute value signal sum generating means for multiplying the absolute value signal sum by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal sum; precursor/postcursor response signal set generating means for providing, when the weighted signal sum is greater than all of preceding absolute response value signals as the absolute response value signals higher in response speed than the precursor candidate signal set, m impulse response signals corresponding to the precursor candidate signal set among the L impulse response
  • a timing recovery circuit comprising: absolute response value signal generating means for obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; truncation error signal generating means for using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set, providing the total sum of the precursor candidate signal set as an absolute value signal sum and providing the total sum of the all the absolute response value signals higher in response speed than the maximum absolute response value signal as a truncation error signal; weighted absolute value signal sum generating means for multiplying the absolute value signal sum by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal sum; precursor/postcursor response signal set generating means for providing, when the weighted signal sum is greater than the truncation
  • a timing recovery circuit comprising: absolute response value signal generating means for obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; precursor candidate signal generating means for using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set; weighted absolute value signal generating means for multiplying the maximum absolute response value signal by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal; precursor/postcursor response value signal set generating means for providing, when the weighted signal is greater than all of preceding absolute response value signals as the absolute response value signals higher in response speed than the precursor candidate signal set, m impulse response value signals corresponding to the precursor candidate signal set among the L impulse response signals as a precursor response set and n impulse response signals next in response speed to
  • the timing recovery circuit further comprises shift factor determining means for selecting and determining the shift factor from a detected reception power level of received signal received as input.
  • a timing recovery method comprising steps of: obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set and providing the total sum of the precursor candidate signal set as an absolute value signal sum; multiplying the absolute value signal sum by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal sum; providing, when the weighted signal sum is greater than all of preceding absolute response value signals as the absolute response value signals higher in response speed than the precursor candidate signal set, m impulse response signals corresponding to the precursor candidate signal set among the L impulse response signals as a precursor response set and n impulse response signals next in response speed to the precursor response set as a postcursor response signal set; and updating, when the
  • a timing recovery method comprising steps of: obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set, providing the total sum of the precursor candidate signal set as an absolute value signal sum and providing the total sum of the all the absolute response value signals higher in response speed than the maximum absolute response value signal as a truncation error signal; multiplying the absolute value signal sum by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal sum; providing, when the weighted absolute value signal sum is greater than the truncation error signal, m impulse response signals corresponding to the precursor candidate signal set among the L impulse response signals as a precursor response set and n impulse response signals next in response speed
  • a timing recovery method comprising steps of: obtaining the absolute values of L input impulse response value signals representing as communication channel characteristic and arranged in the order of shorter response times and providing the obtained absolute values as absolute response value signals; using the maximum one of the absolute response value signals as the maximum absolute response value signal and m sequential absolute response value signals, in which the maximum absolute response value signal is highest in response speed, as a precursor candidate signal set; and multiplying the maximum absolute response value signal by a shift factor determined on the basis of the received signal intensity to obtain and provide a weighted absolute value signal; providing, when the weighted signal is greater than all of preceding absolute response value signals as the absolute response value signals higher in response speed than the precursor candidate signal set, m impulse response value signals corresponding to the precursor candidate signal set among the L impulse response signals as a precursor response set and n impulse response signals next in response speed to the precursor response signal set as a postcursor response signal set; and updating, when the weighted signal is less than any one of the preceding absolute response
  • the timing recovery method further comprises step for selecting and determining the shift factor from a detected reception power level of received signal received as input.
  • the timing recovery is executed recursively such that the product of multiplication of the total sum of the absolute values of all impulse responses as signal components by the weight factor as shift factor is greater than the absolute values of impulse responses as noise components.
  • FIG. 1 is a functional block diagram showing a first embodiment of the present invention and also serves as a flow chart illustrating the operation of the embodiment;
  • FIG. 2 is a functional block diagram showing a second embodiment of the present invention and also serves as a flow chart illustrating the operation of the embodiment;
  • FIG. 3 is a functional block diagram showing a third embodiment of the present invention and also serves as a flow chart illustrating the operation of the embodiment;
  • FIG. 4 is a flow chart representing the prior art timing recovery method
  • FIG. 5 is a drawing showing an example of the impulse response.
  • FIG. 1 is a functional block diagram showing a first embodiment of the present invention and also serves as a flow chart illustrating the operation of the embodiment.
  • shift factor determining means 1 determines shift factor ⁇ (also called weight factor) according to the intensity of received signal S r (step 101 ).
  • the shift factor ⁇ is set to a large value in order that the lower the received signal intensity shift is produced the less possibly.
  • storing means such as ROM, in which shift factors corresponding to received signal intensities are stored, is provided, and when a received signal intensity is detected, a shift factor corresponding to the detected received signal intensity is read out from the storing means.
  • the shift factor ⁇ is made the less the higher the received signal intensity, such as 0.7, 0.6 and 0.5 for received signal intensity of below 1 mW, 1 to 5 mW and above 5 mW, respectively.
  • absolute response value signal generating means 2 determines the absolute value signals of L (L being a natural number) impulse response signals S ir as absolute response value signals S ra (step 102 ). Then, denoting the maximum absolute response value signal among S ra by S mra , absolute value signal sum generating means 3 calculates the total sum of precursor candidate signal set S prcan , which is constituted by m sequential signals S ra including S mra as the highest response signal to obtain absolute value signal sum S suma (step 103 ).
  • weighted absolute value signal sum generating means 4 multiplies S suma by the shift factor (or weight factor) ⁇ determined in the step 101 to obtain weighted absolute value signal sum S wsuma (step 104 ).
  • precursor/postcursor response signal set generating means 5 determines m signals S ir corresponding to S prcan to be precursor response signal set S prres , and determines n signals S ir , which are next in response speed to S prres , to be postcursor response signal set (step 106 ).
  • weighted absolute value signal sum updating means 6 updates S prcan to m sequential signals S ra higher in response speed by one each, and updates S suma to the total sum of the result of updating of S prcan (step 107 ).
  • the weighted absolute value signal sum S wsuma is less than S ra ( 3 ) which is higher in response speed than the precursor candidate signal set S prcan .
  • the precursor candidate signal set S prcan is thus less than S ra ( 3 ) which is higher in response speed than the precursor candidate signal set S prcan .
  • the precursor candidate signal set S prcan is updated to m sequential signals S ra higher in response speed by one each, that is, the updated precursor candiate set S prcan is
  • the impulse response signals corresponding to the precursor candidate signal set S prcan are determined to be the precursor response signal set S prcan
  • the impulse response signals corresponding to the two absolute response value signals S ra ( 5 ) and S ra ( 6 ) next in response speed to the precursor signal candiate set S prcan are determined to be the postcursor response signal set S pores .
  • FIG. 2 is a functional block diagram showing a second embodiment of the present invention and also serves as a flow chart illustrating the operation of the embodiment. Parts like those in FIG. 1 are designated by like reference numerals.
  • the shift factor determining means 1 determines the shift factor (or weight factor) ⁇ according to the intensity of the received signal S r (step 101 ).
  • the absolute response value signal generating means 2 determines the absolute value signals of L impulse response signals S ir as absolute response value signals S ra (step 102 ).
  • truncation error generating means 7 calculates the total sum of precursor candidate signal set S prcan , which is constituted by sequential m signals including S mra as the highest response signal to obtain absolute value sum signal S suma , and makes the total sum of S ra higher in response speed than S mra to be truncation error signals S terr (step 201 ).
  • the weighted absolute value signal sum generating means 4 multiplies S suma by the shift factor (or weight factor) ⁇ to obtain weighted absolute value signal sum S wsuma (step 104 ).
  • S wsuma is greater than S terr (step 202 )
  • the precursor/postcursor response signal set generating means 5 determines m signals S ir corresponding to S prcan to be precursor response signal set S prres and also determines n signals S ir , which are next in response speed to S prres , to be post cursor response set (step 106 ).
  • truncation error signal generating means 8 updates S prcan to m signals S ra next in response speed by one each, and also updates S terr to the total sum of S ra higher in response speed than the result of updating of S prcan (step 203 ).
  • the precursor candidate signal set S prcan is updated to m sequential signals S ra higher in response speed by one each, that is, the updated precursor candidate signal set S prcan is
  • the weighted absolute value signal sum S wsuma becomes greater than the truncation error signal S terr .
  • the impulse response signals corresponding to the precursor candidate signal set S prcan are determined to be the precursor response signal set S prres
  • the impulse response signals corresponding to the two absolute response signal value S ra ( 5 ) and S ra ( 6 ) next in response speed to the precursor candidate signal set S prcan are determined to be the postcursor response signal set S pores .
  • FIG. 3 is a functional block diagram showing a third embodiment of the present invention and also serves as a flow chart illustrating the operation of the embodiment. Parts like those in FIGS. 1 and 2 are designated by like reference numerals.
  • the shift factor determining means 1 determines the shift factor ⁇ (or weight factor) according to the intensity of the received signal S r (step 101 ).
  • the absolute response value signal generating means 2 determines the absolute value signals of impulse response signals S ir as absolute response value signals S ra (step 102 ).
  • precursor candidate signal set generating means 9 makes m sequential signals S ra including the highest response speed signal S mra to be precursor candidate signal set S prcan (step 301 ).
  • Weighted signal generating means 10 produces weighted signal S w by multiplying S mra by shift factor ⁇ (step 302 ).
  • precursor/postcursor response signal set generating means 5 determines m signals S ir corresponding to S prcan to be precursor response signal set S prres , and determines n signals S ir next in response speed to S prres to postcursor response signal set S pores (step S 106 ).
  • maximum response value updating means 11 updates S prcan with m sequential signals S ra , in which the lowest response speed one of the signals S era greater than S w is highest in response speed, and updates S mra with the maximum one of the results of updating of S prcan (step 304 ).
  • the precursor signal candidate group S prcan is thus provided.
  • the weighted signal S w is
  • the precursor candidate signal set S prcan is updated to m sequential signals S ra higher in response speed by one each, that is, the updated precursor candidate signal set S prcan is
  • the weighted signal S w is
  • the weighted signal S w is greater than all of the absolute response value signals S ra higher in response speed than the precursor candidate signal set S prcan .
  • the impulse response signals corresponding to the precursor candidate signal set S prcan is determined to be the precursor response signal set S prres
  • the two impulse response signals next in response speed to the precursor candidate signal set S prcan is determined to be the postcursor response signal set S pores .

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Dc Digital Transmission (AREA)
US09/611,484 1999-07-07 2000-07-07 Timing recovery circuit and method in automatic equalizer Expired - Fee Related US6704373B1 (en)

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JP19246899A JP3419349B2 (ja) 1999-07-07 1999-07-07 自動等化器におけるタイミング再生回路及びそのタイミング再生方法

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537419A (en) * 1991-06-27 1996-07-16 Hughes Electronics Receiver sample timing adjustment using channel impulse response
US5809086A (en) * 1996-03-20 1998-09-15 Lucent Technologies Inc. Intelligent timing recovery for a broadband adaptive equalizer
US6314133B1 (en) * 1998-02-04 2001-11-06 Nec Corporation Automatic equalizer capable of surely selecting a suitable sample timing a method for generating sampling clock used for the sample timing and a recording medium usable in control of the automatic equalizer
US6366612B1 (en) * 1997-07-23 2002-04-02 Nec Corporation Automatic equalizer
US6414990B1 (en) * 1998-09-29 2002-07-02 Conexant Systems, Inc. Timing recovery for a high speed digital data communication system based on adaptive equalizer impulse response characteristics

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537419A (en) * 1991-06-27 1996-07-16 Hughes Electronics Receiver sample timing adjustment using channel impulse response
US5809086A (en) * 1996-03-20 1998-09-15 Lucent Technologies Inc. Intelligent timing recovery for a broadband adaptive equalizer
US6366612B1 (en) * 1997-07-23 2002-04-02 Nec Corporation Automatic equalizer
US6314133B1 (en) * 1998-02-04 2001-11-06 Nec Corporation Automatic equalizer capable of surely selecting a suitable sample timing a method for generating sampling clock used for the sample timing and a recording medium usable in control of the automatic equalizer
US6414990B1 (en) * 1998-09-29 2002-07-02 Conexant Systems, Inc. Timing recovery for a high speed digital data communication system based on adaptive equalizer impulse response characteristics

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
S. Ariyavisitakul, et al., "Reduced-Complexity Equalization Techniques for Broadband Wireless Channels", IEEE Journal on Selected Areas in Communications, vol. 15, No. 1, Jan. 1997, pp. 5-15.

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