US6291287B1 - Method for producing a memory cell - Google Patents

Method for producing a memory cell Download PDF

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Publication number
US6291287B1
US6291287B1 US09/020,872 US2087298A US6291287B1 US 6291287 B1 US6291287 B1 US 6291287B1 US 2087298 A US2087298 A US 2087298A US 6291287 B1 US6291287 B1 US 6291287B1
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US
United States
Prior art keywords
polysilicon
layer
oxidation
production method
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
US09/020,872
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English (en)
Inventor
Gunther Plasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Assigned to SIEMENS AKTIENGESELLSCHAFT reassignment SIEMENS AKTIENGESELLSCHAFT ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PLASA, GUNTHER
Application granted granted Critical
Publication of US6291287B1 publication Critical patent/US6291287B1/en
Priority to US11/000,495 priority Critical patent/USRE40275E1/en
Assigned to INFINEON TECHNOLOGIES AG reassignment INFINEON TECHNOLOGIES AG ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SIEMENS AKTIENGESELLSCHAFT
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
US09/020,872 1995-08-07 1998-02-09 Method for producing a memory cell Ceased US6291287B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11/000,495 USRE40275E1 (en) 1995-08-07 2004-11-29 Method for producing a memory cell

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19528991 1995-08-07
DE19528991A DE19528991C2 (de) 1995-08-07 1995-08-07 Herstellungsverfahren für eine nichtflüchtige Speicherzelle
PCT/DE1996/001477 WO1997006559A2 (de) 1995-08-07 1996-08-07 Herstellungsverfahren für eine nichtflüchtige speicherzelle

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
PCT/DE1996/001477 Continuation WO1997006559A2 (de) 1995-08-07 1996-08-07 Herstellungsverfahren für eine nichtflüchtige speicherzelle

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/000,495 Reissue USRE40275E1 (en) 1995-08-07 2004-11-29 Method for producing a memory cell

Publications (1)

Publication Number Publication Date
US6291287B1 true US6291287B1 (en) 2001-09-18

Family

ID=7768896

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/020,872 Ceased US6291287B1 (en) 1995-08-07 1998-02-09 Method for producing a memory cell
US11/000,495 Expired - Lifetime USRE40275E1 (en) 1995-08-07 2004-11-29 Method for producing a memory cell

Family Applications After (1)

Application Number Title Priority Date Filing Date
US11/000,495 Expired - Lifetime USRE40275E1 (en) 1995-08-07 2004-11-29 Method for producing a memory cell

Country Status (6)

Country Link
US (2) US6291287B1 (ja)
EP (1) EP0843891B1 (ja)
JP (1) JPH11510320A (ja)
KR (1) KR100400531B1 (ja)
DE (2) DE19528991C2 (ja)
WO (1) WO1997006559A2 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6432791B1 (en) * 1999-04-14 2002-08-13 Texas Instruments Incorporated Integrated circuit capacitor and method
US6787840B1 (en) * 2000-01-27 2004-09-07 Advanced Micro Devices, Inc. Nitridated tunnel oxide barriers for flash memory technology circuitry
US20050196968A1 (en) * 2002-08-22 2005-09-08 Infineon Technologies Ag Method for generating a structure on a substrate

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2520047A1 (de) 1974-05-17 1975-12-04 Ibm Verfahren zur herstellung von silizium-gate-feldeffekttransistoren
DE2739662A1 (de) 1977-09-02 1979-03-08 Siemens Ag Verfahren zur herstellung von mos-transistoren
JPS5742169A (en) 1980-08-26 1982-03-09 Toshiba Corp Production of semiconductor device
US4400867A (en) 1982-04-26 1983-08-30 Bell Telephone Laboratories, Incorporated High conductivity metallization for semiconductor integrated circuits
US4445266A (en) * 1981-08-07 1984-05-01 Mostek Corporation MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance
US4490193A (en) * 1983-09-29 1984-12-25 International Business Machines Corporation Method for making diffusions into a substrate and electrical connections thereto using rare earth boride materials
EP0294699A2 (en) 1987-06-11 1988-12-14 STMicroelectronics S.r.l. Method for making capacitors in CMOS and NMOS processes
US4837176A (en) * 1987-01-30 1989-06-06 Motorola Inc. Integrated circuit structures having polycrystalline electrode contacts and process
US4927780A (en) * 1989-10-02 1990-05-22 Motorola, Inc. Encapsulation method for localized oxidation of silicon
US5109258A (en) 1980-05-07 1992-04-28 Texas Instruments Incorporated Memory cell made by selective oxidation of polysilicon
US5151378A (en) * 1991-06-18 1992-09-29 National Semiconductor Corporation Self-aligned planar monolithic integrated circuit vertical transistor process
US5393686A (en) * 1994-08-29 1995-02-28 Taiwan Semiconductor Manufacturing Company Method of forming gate oxide by TLC gettering clean
US5786263A (en) * 1995-04-04 1998-07-28 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
US5866453A (en) * 1995-09-14 1999-02-02 Micron Technology, Inc. Etch process for aligning a capacitor structure and an adjacent contact corridor
US5895250A (en) * 1998-06-11 1999-04-20 Vanguard International Semiconductor Corporation Method of forming semicrown-shaped stacked capacitors for dynamic random access memory

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2520047A1 (de) 1974-05-17 1975-12-04 Ibm Verfahren zur herstellung von silizium-gate-feldeffekttransistoren
DE2739662A1 (de) 1977-09-02 1979-03-08 Siemens Ag Verfahren zur herstellung von mos-transistoren
US5109258A (en) 1980-05-07 1992-04-28 Texas Instruments Incorporated Memory cell made by selective oxidation of polysilicon
JPS5742169A (en) 1980-08-26 1982-03-09 Toshiba Corp Production of semiconductor device
US4445266A (en) * 1981-08-07 1984-05-01 Mostek Corporation MOSFET Fabrication process for reducing overlap capacitance and lowering interconnect impedance
US4400867A (en) 1982-04-26 1983-08-30 Bell Telephone Laboratories, Incorporated High conductivity metallization for semiconductor integrated circuits
US4490193A (en) * 1983-09-29 1984-12-25 International Business Machines Corporation Method for making diffusions into a substrate and electrical connections thereto using rare earth boride materials
US4837176A (en) * 1987-01-30 1989-06-06 Motorola Inc. Integrated circuit structures having polycrystalline electrode contacts and process
EP0294699A2 (en) 1987-06-11 1988-12-14 STMicroelectronics S.r.l. Method for making capacitors in CMOS and NMOS processes
US4927780A (en) * 1989-10-02 1990-05-22 Motorola, Inc. Encapsulation method for localized oxidation of silicon
US5151378A (en) * 1991-06-18 1992-09-29 National Semiconductor Corporation Self-aligned planar monolithic integrated circuit vertical transistor process
US5393686A (en) * 1994-08-29 1995-02-28 Taiwan Semiconductor Manufacturing Company Method of forming gate oxide by TLC gettering clean
US5786263A (en) * 1995-04-04 1998-07-28 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
US5866453A (en) * 1995-09-14 1999-02-02 Micron Technology, Inc. Etch process for aligning a capacitor structure and an adjacent contact corridor
US5895250A (en) * 1998-06-11 1999-04-20 Vanguard International Semiconductor Corporation Method of forming semicrown-shaped stacked capacitors for dynamic random access memory

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
"Formation of High Quality Storage Capacitor Dielectrics by in-situ Rapid Thermal Reoxidation of SI3N4 Films in N2O Ambient", IEEE Electron Device Letters, vol. 15, No. 8, Aaugust 1994, pp. 266-268.
IEEE Transactions on Electron Devices, Jan. 1981, vol. ED-28, No. 1.
IEEE Transactions on Electron Devices, Oct. 1984, vol. ED-31, No. 10.
Japanese Patent Abstract No. 61-248532 (Mitsui), dated Nov. 5, 1986.

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6432791B1 (en) * 1999-04-14 2002-08-13 Texas Instruments Incorporated Integrated circuit capacitor and method
US6787840B1 (en) * 2000-01-27 2004-09-07 Advanced Micro Devices, Inc. Nitridated tunnel oxide barriers for flash memory technology circuitry
US20050196968A1 (en) * 2002-08-22 2005-09-08 Infineon Technologies Ag Method for generating a structure on a substrate
US7262118B2 (en) 2002-08-22 2007-08-28 Infineon Technologies Ag Method for generating a structure on a substrate

Also Published As

Publication number Publication date
KR100400531B1 (ko) 2003-11-15
DE19528991A1 (de) 1997-06-19
DE19528991C2 (de) 2002-05-16
JPH11510320A (ja) 1999-09-07
EP0843891B1 (de) 2002-07-10
WO1997006559A3 (de) 1997-03-20
WO1997006559A2 (de) 1997-02-20
EP0843891A2 (de) 1998-05-27
USRE40275E1 (en) 2008-04-29
DE59609433D1 (de) 2002-08-14
KR19990036305A (ko) 1999-05-25

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