US5886578A - Differential amplifier including bias circuit with bias resistor - Google Patents

Differential amplifier including bias circuit with bias resistor Download PDF

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US5886578A
US5886578A US08/883,455 US88345597A US5886578A US 5886578 A US5886578 A US 5886578A US 88345597 A US88345597 A US 88345597A US 5886578 A US5886578 A US 5886578A
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signal
circuit
differential amplifier
source follower
follower circuit
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Miyo Miyashita
Kazuya Yamamoto
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits
    • H03K19/018564—Coupling arrangements; Impedance matching circuits with at least one differential stage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying

Definitions

  • the present invention relates to a differential amplifier and, more particularly, to a differential amplifier that can produce a satisfactory voltage gain in a wide range of operating frequencies exceeding a few GHz, which is suitable for a single end input interface.
  • FIG. 14 is a circuit diagram illustrating a prior art differential amplifier having an input interface, for example, which is described in "Bipolar and MOS Analog Integrated Circuit design" written by Alan B. Grebene.
  • reference numeral 1 designates a first level shift circuit for dropping a DC voltage of an input signal D to a constant level
  • numeral 2 designates a second level shift circuit for dropping an input reference voltage V R by the same amount as in the first level shift circuit 1
  • numeral 3 designates a differential amplifier that is connected directly or cascade-connected to the first and second level shift circuits 1 and 2 and is connected to the next stage through another level shift circuit (not shown).
  • reference numeral 4 designates a source follower field effect transistor (hereinafter referred to as an FET)
  • numeral 5 designates a constant current source FET
  • numeral 6 designates a level shift diode comprising one diode or a plurality of diodes connected in series
  • the anode electrode of the level shift diode 6 is connected to the source electrode of the source follower FET 4.
  • the input signal D is input to the gate terminal of the source follower FET 4.
  • the level shift diode 6 drops the DC voltage of the input signal D by an amount corresponding to a forward voltage that is produced due to a current supplied from the constant current source FET 5.
  • the amount of level shift is about 0.6 V per diode.
  • reference numeral 7 designates a source follower FET
  • numeral 9 designates a constant current source FET
  • numeral 8 designates a level shift diode comprising one diode or a plurality of diodes connected in series.
  • the input reference voltage V R is input to the gate terminal of the source follower FET 7, and it is dropped through the level shift diode 8 to be output.
  • reference numerals 10 and 11 designate FETs serving as a source coupled transistor pair, and a high frequency signal is input to the gate of the FET 10 and a DC voltage is supplied to the gate of the FET 11.
  • Reference numeral 12 designates a level shift diode for dropping a DC voltage of an output signal.
  • Reference numerals 13 and 14 designate load resistors that are respectively connected in series to the drains of the FETs 10 and 11.
  • Reference numeral 15 designates a constant current source that is connected to the sources of the FETs 10 and 11 constituting the source coupled transistor pair.
  • the common-mode component V com and the differential component V dif included in common in two inputs of the differential amplifier 3 are defined as follows:
  • the input signals of the differential amplifier 3 can be expressed as:
  • the output voltage V OUT at the output OUT, a node between the FET 10 and the load resistor 13, and the output voltage V /OUT at the output /OUT, serving as a node between the FET 11 and the load resistor 14, are represented by: ##EQU1## where Ad is the differential gain and Ac is the common-mode gain of the differential amplifier 3. Assuming that the difference ⁇ V OUT between the output voltages at two output ends is an output, ⁇ V OUT becomes: ##EQU2## Therefore, only the gain of the differential component can be obtained.
  • FIGS. 16(a)-16(c) are diagrams showing the relationship among input waveforms (FIG. 16(a)) and output waveforms (FIG. 16(b)) of the level shift circuits 1 and 2 and output waveforms (FIG. 16(c)) of the differential amplifier 3 at the single end input, with the time base as a reference.
  • FIG. 16(b) in the single end input, since the input V R of the second level shift circuit 2 is a constant voltage, its output has a flat waveform reflecting the input.
  • An optical transmitter-receiver comprises a wideband amplifier, a dicision circuit for discriminating H level from L level of an input signal, and a driver for driving a laser diode, or the like.
  • these circuits are often constituted of differential amplifiers or source coupled type FET logics (SCFL), having an advantage of high speed.
  • SCFL source coupled type FET logics
  • differential signals i.e., a data signal and a phase inversion signal
  • the phase difference between the two inputs must be precisely adjusted. For that, it is required to adjust lengths of wirings which connect the signal sources and the inputs of the circuit, or to provide a phase adjusting circuit at one of the input terminals, so that the system design becomes complicated. Therefore, single end input is generally used. Consequently, although the gain should be increased, the gain is reduced by half because of the single end input.
  • the differential gain Ad is in proportion to transconductance gm of the source coupled FETs 10 and 11, and the resistance of the load resistors 13 and 14. Accordingly, in order to increase the gain, the transconductance gm, the resistance, or both of them may be increased. However, when an FET having a determined gate length is employed, the gate width of the FET must be increased in order to increase the transconductance gm, causing an increase in the gate-source capacitance or the gate-drain capacitance of the FET.
  • the increase in the transconductance gm or the resistance value causes band degradation, i.e., a reduction of the band in which a desired gain can be obtained, in a band where the input buffer is used. That is, as shown in FIG. 17, although a desired gain has usually been obtained up to a region of a frequency f, the desired gain is obtained only up to a region of a frequency f' lower than the frequency f.
  • the influence due to the band degradation described above becomes larger as the signal is transmitted from the amplifier of the previous stage to the amplifier of the next stage, whereby the band degradation is promoted and an increase in current is caused.
  • the prior art differential amplifier is constituted as described above, and the gain obtained with a single end input is below half of the gain for a differential input.
  • a differential amplifier inputting a first input signal and a second input signal, respectively, and amplifying the voltage difference between the first and second input signals to output an output signal, includes a first source follower circuit externally inputting a data signal as the first input signal, and having an output node; a second source follower circuit having a constant current source FET, and inputting a signal having a reference voltage as the second input signal; and a bias circuit taking out a signal having the same phase as that of the data signal from the output node of the first source follower circuit and inputting that signal to the gate terminal of the constant current source FET of the second source follower circuit.
  • the differential gain can be improved to a value approximately equal to that which is obtained when the differential inputs are input.
  • the bias circuit comprises a by-pass condenser connecting the output node of the first source follower circuit from which the signal having the same phase as that of the data signal is taken out and the gate terminal of the constant current source FET of the second source follower circuit; and a bias resistor supplying the gate bias of the current source FET of the second source follower circuit. Therefore, by this construction of the bias circuit, the effect of the first aspect is obtained.
  • the bias circuit comprises a reverse-biased diode connecting the output node of the first source follower circuit from which the signal having the same phase as that of the data signal is taken out and the gate terminal of the constant current source FET of the second source follower circuit; and a bias resistor supplying the gate bias of the current source FET of the second source follower circuit. Therefore, the bias circuit can be realized in a relatively small element region, and its fabricating process can be facilitated.
  • an inductor is connected in series with the bias resistor to compensate the phase lag caused by the input capacitance of the current source FET of the second source follower circuit. Therefore, the differential amplifier can be used in a high frequency region, with suppressing the influences by the input capacitance of the current source FET of the second source follower circuit.
  • a resistor is connected in parallel with the by-pass condenser to compensate the phase lead caused by the by-pass condenser constituting the bias circuit. Therefore, the differential amplifier can be used even in a frequency band where the by-pass condenser cannot be regarded as short-circuited.
  • the bias circuit comprises a by-pass resistor connecting the output node of the first source follower circuit from which the signal having the same phase as that of the data signal is taken out and the gate terminal of the constant current source FET of the second source follower circuit; and a bias resistor supplying the gate bias of the current source FET of the second source follower circuit. Therefore, when the differential amplifier is used in a frequency region where the input impedance of the current source FET of the second source follower circuit is seen to be quite large, the structure thereof can be simplified.
  • a condenser is connected in parallel with the bias resistor supplying the gate bias of the current source FET of the second source follower circuit to increase the input capacitance of the current source FET of the second source follower circuit. Therefore, even when the input capacitance of the current source FET of the second source follower circuit is extremely small, the by-pass condenser can be constituted of such as an MIM capacitor with high precision.
  • a variable capacitance condenser is used as the condenser. Therefore, it is possible to absorb variations in fabrication processes when producing integrated circuits.
  • variable capacitance condenser in the differential amplifier of the eighth aspect of the invention, comprises an MIM capacitor obtained by dividing an upper electrode into plural parts and connecting the divided plural parts of the upper electrode with wirings, the wirings being cut as required to form a desired capacitance.
  • a diode is used as the variable capacitance condenser.
  • FIG. 1 is a circuit diagram illustrating a differential amplifier in accordance with a first embodiment of the present invention.
  • FIG. 2 is a diagram illustrating an instance of pattern layout of the differential amplifier according to the first embodiment of the invention.
  • FIGS. 3(a)-3(c) are diagrams showing input waveforms and output waveforms of level shift circuits and output waveforms of the differential amplifier according to the first embodiment of the invention.
  • FIG. 4 is a diagram showing a relationship between frequency and gain of the differential amplifier according to the first embodiment of the invention.
  • FIG. 5 is a circuit diagram illustrating a differential amplifier in accordance with a second embodiment of the present invention.
  • FIG. 6 is a circuit diagram illustrating a differential amplifier in accordance with a third embodiment of the present invention.
  • FIGS. 7(a) and 7(b) are circuit diagrams illustrating a differential amplifier in accordance with a fourth embodiment of the present invention.
  • FIG. 8 is a circuit diagram illustrating a differential amplifier in accordance with a fifth embodiment of the present invention.
  • FIG. 9 is a circuit diagram illustrating a differential amplifier in accordance with a sixth embodiment of the present invention.
  • FIG. 10 is a diagram illustrating an instance of pattern layout of a bias circuit of the differential amplifier according to the sixth embodiment of the invention.
  • FIG. 11 is a circuit diagram illustrating a differential amplifier in accordance with a seventh embodiment of the present invention.
  • FIG. 12 is a diagram illustrating an instance of pattern layout with a variable capacitance condenser as the center, when the variable capacitance condenser is an MIM capacitor in the differential amplifier according to the seventh embodiment of the invention.
  • FIG. 13 is a circuit diagram illustrating a differential amplifier in accordance with an eighth embodiment of the present invention.
  • FIG. 14 is a circuit diagram illustrating a prior art differential amplifier.
  • FIGS. 15(a) and 15(b) are diagrams showing signal waveforms input to two input terminals of the prior art differential amplifier.
  • FIGS. 16(a)-16(c) are diagrams showing input waveforms and output waveforms of level shift circuits and output waveforms of the prior art differential amplifier.
  • FIG. 17 is a diagram showing a relationship between frequency and gain of the prior art differential amplifier.
  • FIG. 1 is a circuit diagram illustrating a differential amplifier according to a first embodiment of the present invention.
  • the same reference numerals as those shown in FIG. 14 designate the same or corresponding parts.
  • Reference numeral 16 designates a bias circuit for taking out a signal from the first level shift circuit 1 and inputting that signal to the gate terminal of the current source FET of the second level shift circuit 2.
  • the bias circuit 16 When a signal having the same phase as that of the input signal is input to the gate terminal of the current source FET 9 of the second level shift circuit 2 by the bias circuit 16, the current of the current source of the second level shift circuit 2 changes.
  • the output of the first level shift circuit 1 is input to a by-pass condenser 17, and only the high-frequency signal is selected and output to the gate of the current source FET 9.
  • a gate bias resistor 18 for compensating the gate bias of the current source FET 9 is disposed between the by-pass condenser 17 and the gate of the current source FET 9.
  • FIG. 2 is a diagram illustrating pattern layout of an input interface circuit with an input phase inversion function comprising the source follower circuits 1 and 2 and the bias circuit 16, when the differential amplifier having the structure shown in FIG. 1 is an IC.
  • an MIM (metal insulator metal) structure is used as the by-pass condenser.
  • the gate voltage of the current source FET 9 of the second level shift circuit 2 is increased, and the current flowing through the current source FET 9 increases. Simultaneously, the current flowing through the source follower FET 7 increases. Since the gate voltage of the source follower FET 7 is fixed to the constant level V R , the source voltage of the source follower FET 7 decreases.
  • the input signal D is at Low level, the gate voltage of the current source FET 9 of the second level shift circuit 2 is decreased, and the current flowing through the current source FET 9 decreases, so that the source voltage of the source follower FET 7 increases.
  • the first and second level shift circuits 1 and 2 output the same output levels representing the DC components.
  • the output signal from the second level shift circuit 2 has a phase opposite to that of the output signal from the first level shift circuit 1. Consequently, when the outputs of the first and second level shift circuits 1 and 2 are input to two input terminals of the differential amplifier 3 at the next stage, these inputs are just like differential inputs, so that the gain of the differential amplifier 3 is improved.
  • FIGS. 3(a)-3(c) are diagrams showing the relationship between input waveforms (FIG. 3(a)) and output waveforms (FIG. 3(b)) of the level shift circuits 1 and 2, and output waveforms (FIG. 3(c)) of the differential amplifier 3 with a the single end input, with the time base as a reference.
  • the input V R of the second level shift circuit 2 while in the single end input the input V R of the second level shift circuit 2 has a constant voltage, it has an output taken out from the first level shift circuit 1 and input to the current source FET 9 by means of the bias circuit 16. Therefore, the output of the second level shift circuit 2 has a waveform similar to the waveform obtained by inverting the output of the first level shift circuit 1.
  • FIG. 4 is a diagram showing simulation results representing the relationship between frequency and voltage gain when the single end input is employed using the differential amplifier according to the first embodiment of the invention. It is found from the figure that a higher gain is obtained than when the single end input is employed using the prior art differential amplifier.
  • the bias circuit 16 takes the output of the first level shift circuit 1 to which the input signal D is input, and inputs the same to the gate of the current source FET 9 of the second level shift circuit 2 to which the reference voltage V R is input. Therefore, the second level shift circuit 2 always outputs a signal which is not a constant voltage but has a waveform having a phase opposite to that of the input signal D. Then, the outputs of the first and second level shift circuits 1 and 2 are input to two input terminals of the differential amplifier 3 of the next stage, directly or via another level shift circuit, whereby the differential amplifier 3 operates as if a differential input is employed, thereby resulting in a higher gain than for a single end input.
  • FIG. 5 is a circuit diagram illustrating a differential amplifier according to a second embodiment of the present invention.
  • the same reference numerals as those shown in FIG. 1 designate the same or corresponding parts.
  • Reference numeral 161 designates a bias circuit for taking out a signal from the first level shift circuit 1 and inputting that signal to the gate terminal of the current source FET 9 of the second level shift circuit 2.
  • the second embodiment of the invention is characterized in that a diode 19 is substituted for the by-pass condenser 17 of the bias circuit according to the first embodiment.
  • reference numeral 19 designates a reverse-biased diode that is used in place of the by-pass condenser 17 of the bias circuit shown in FIG. 1.
  • An equivalent circuit of the reverse-biased diode 19 is represented by a resistance component and a capacitance component connected in series to each other. Therefore, this circuit performs the same operation as that in the first embodiment.
  • the MIM process is not needed as when the MIM capacitor is used as in the first embodiment, thereby the number of process steps for fabrication can be reduced. Further, the area occupied by that element in pattern layout can be reduced, presenting an advantage in the circuit integration.
  • FIG. 6 is a circuit diagram illustrating a differential amplifier according to a third embodiment of the present invention.
  • the same reference numerals as those shown in FIG. 1 designate the same or corresponding parts.
  • Reference numeral 162 designates a bias circuit for taking out a signal from the first level shift circuit 1 and inputting that signal to the gate terminal of the current source FET 9 of the second level shift circuit 2.
  • the third embodiment of the invention is characterized in that a phase compensating inductor 20 is provided between an end of the gate bias resistor 18 of the bias circuit according to the first embodiment and the gate terminal of the current source FET 9.
  • the signal output from the second level shift circuit 2 is a phase inversion signal with respect to the signal output from the first level shift circuit 1.
  • the voltage phase at the gate terminal of the current source FET 9 leads the serial circuit comprising the bias resistor 18 and the inductor 20.
  • the parallel circuit comprising the serial circuit and the condenser 17 decreases the phase changes of the signals output from the first and second level shift circuits 1 and 2 due to the gate parasitic capacitance of the current source FET 9. Consequently, a signal having a phase opposite to that of the signal output from the first level shift circuit 1 is obtained as the output of the second level shift circuit 2.
  • the differential amplifier is employed for a circuit which requires sensitivity at a certain center frequency, such as a clock buffer circuit in a decision circuit, if the inductance of the inductor 20 is adjusted so as to satisfy, at a required center frequency, the condition shown by the following equation:
  • the phase of the gate input signal of the current source FET 9 becomes just the same phase as that of the signal output from the first level shift circuit 1.
  • the signal output from the first level shift circuit 1 has a phase opposite to that of the signal output from the second level shift circuit 2.
  • FIG. 7(a) is a circuit diagram illustrating a differential amplifier according to a fourth embodiment of the present invention.
  • the same reference numerals as those shown in FIG. 1 designate the same or corresponding parts.
  • Reference numeral 163 designates a bias circuit for taking out a signal from the first level shift circuit 1 and inputting that signal to the gate terminal of the current source FET 9 of the second level shift circuit 2.
  • the fourth embodiment of the invention is characterized in that a resistor 21 is connected in parallel with the by-pass condenser 17 of the bias circuit according to the first embodiment.
  • reference numerals 22 and 23 designate resistors constituting a bias circuit for equalizing the gate bias of the constant current source FET 5 of the first level shift circuit 1 to the gate bias of the current source FET 9 of the second level shift circuit 2.
  • Reference numeral 24 designates a resistor for adjusting the gate-source resistance of the current source FET 9. By interposing the resistor 24, the gate-source voltage of the current source FET 9 can be set to 0 V or below.
  • Reference numeral 25 designates a resistor for equalizing the gate-source voltage of the constant current source FET 5 to that of the current source FET 9.
  • the by-pass condenser 17 can be regarded as short-circuited, i.e., the existence of the by-pass condenser can be ignored in view of the high frequency of the signal.
  • the bias circuit 163 according to the fourth embodiment is applicable to a low frequency region where the by-pass condenser 17 cannot be regarded as short-circuited. As the use frequency becomes low, the by-pass condenser 17 produces a phase change, i.e., phase lead, with respect to the (high frequency) output that is output from the first level shift circuit 1.
  • the respective resistors 21 to 25 as shown in FIG. 7(a) are provided so that the bias circuit 163 shown in FIG. 7(b) is equivalently constructed.
  • R 1 represents the resistance of the resistor
  • C 1 represents the capacitance of the by-pass condenser 17
  • R 2 represents the resistance of the bias resistor 18
  • C 2 represents the input capacitance of the gate terminal of the current source FET 9.
  • the resistance of the resistor 24 is ignored assuming a resistance which is much smaller than the resistances of the bias resistor 18 and the resistor 21 is employed.
  • the bias circuit 163 when the voltage input from the first source follower circuit 1 to the bias circuit 163 is V 3 and the voltage generated at the gate terminal of the current source FET 9 is V 4 , the current phase after flowing through the parallel circuit comprising the resistor 21 and the condenser 17 leads with respect to the voltage V 3 , while the voltage V 4 generated when the current flows through the parallel circuit comprising the resistor 18 and the parasitic capacitance of the current source FET 9 lags with respect to the current phase.
  • the resistor 21 is provided in parallel with the by-pass condenser 17 of the bias circuit, and the phase lead due to the condenser 17 is compensated by an adjustment using the parallel circuit comprising the resistor 18 and the parasitic capacitance of the current source FET 9, which is connected in series to the condenser 17. Therefore, even when the bias circuit 163 is employed at a low frequency region at which the by-pass condenser 17 cannot be regarded as short-circuited, the phase difference between the signals output from the first and second level shift circuits 1 and 2 can be made small, resulting in a differential amplifier including a bias circuit having no frequency characteristic.
  • FIG. 8 is a circuit diagram illustrating a differential amplifier according to a fifth embodiment of the present invention.
  • the same reference numerals as those shown in FIG. 1 designate the same or corresponding parts.
  • Reference numeral 164 designates a bias circuit for taking out a signal from the first level shift circuit 1 and inputting that signal to the gate terminal of the current source FET 9 of the second level shift circuit 2.
  • the fifth embodiment of the invention is characterized in that the by-pass condenser 17 of the bias circuit according to the fourth embodiment is removed and only the resistor 21 is provided.
  • the by-pass condenser 17 is unnecessary at a frequency region at which the input impedance of the current source FET 9 is seen to be quite large. Accordingly, the circuit shown in FIG. 8 has the same effects as those of the circuit of the fourth embodiment, in a range at which the input impedance of the current source FET 9 can be ignored.
  • the by-pass condenser since the by-pass condenser is removed, considering that the by-pass condenser of the bias circuit is unnecessary at some frequency band at which the input impedance of the current source FET 9 is seen to be large, a reduction in the chip area is realized to that extent, i.e., by the area of the condenser.
  • FIG. 9 is a circuit diagram illustrating a differential amplifier according to a sixth embodiment of the present invention.
  • the same reference numerals as those shown in FIG. 7(a) designate the same or corresponding parts.
  • Reference numeral 165 designates a bias circuit for taking out a signal from the first level shift circuit 1 and inputting that signal to the gate terminal of the current source FET 9 of the second level shift circuit 2.
  • the sixth embodiment of the invention is characterized in that a condenser 26 is provided in parallel with the gate bias resistor 18 for the current source FET 9 of the bias circuit according to the fourth embodiment.
  • FIG. 10 is a diagram illustrating pattern layout when the by-pass condenser 17 and the condenser 26 are MIM capacitors.
  • the condenser 26 when the input capacitance of the current source FET 9 is small, the condenser 26 is provided in parallel with the gate bias resistor 18 for gate biasing the current source FET 9, at the stage previous to the gate of the current source FET 9, and the input capacitance of the current source FET 9 is compensated to be seen as a large capacitance. Therefore, even when the input capacitance of the current source FET 9 is extremely small, the by-pass condenser 17 can be fabricated easily and with high precision by such as an MIM capacitor.
  • FIG. 11 is a circuit diagram illustrating a differential amplifier according to a seventh embodiment of the present invention.
  • the same reference numerals as those shown in FIG. 9 designate the same or corresponding parts.
  • Reference numeral 166 designates a bias circuit for taking out a signal from the first level shift circuit 1 and inputting that signal to the gate terminal of the current source FET 9 of the second level shift circuit 2.
  • the seventh embodiment of the invention is characterized in that a variable capacitance condenser 27 having a variable capacitance is provided in place of the condenser 26 for compensating the input capacitance of the current source FET 9 of the bias circuit according to the sixth embodiment.
  • variable capacitance condenser 27 is employed as a condenser connected in parallel with the bias resistor 18 correct variations in the input capacitance of the current source FET 9 due to the respective fabricating processes of the current source FET 9.
  • FIG. 12 is a diagram illustrating pattern layout when the variable capacitance condenser 27 described in the seventh embodiment is an MIM capacitor.
  • An upper electrode 28 of the MIM capacitor is divided into portions of sizes each in a range of desired variable capacitance.
  • the respective upper electrodes 28 are connected in parallel with a wiring 29.
  • the wiring 29 may be cut with such as laser as required, whereby the capacitance of the condenser 27 can be adjusted.
  • variable capacitance condenser 27 is employed as a condenser for adjusting the input capacitance of the current source FET 9. Therefore, even when the input capacitance of the current source FET 9 varies with every fabricating process, the variations are properly amended, whereby fabrication yield can be improved.
  • FIG. 13 is a circuit diagram illustrating a differential amplifier according to an eighth embodiment of the present invention.
  • the same reference numerals as those shown in FIG. 11 designate the same or corresponding parts.
  • Reference numeral 167 designates a bias circuit for taking out a signal from the first level shift circuit 1 and inputting that signal to the gate terminal of the current source FET 9 of the second level shift circuit 2.
  • the eighth embodiment of the invention is characterized in that a diode 32 is provided in place of the variable capacitance condenser 27 of the bias circuit according to the seventh embodiment.
  • a diode 32 is provided in place of the variable capacitance condenser 27 of the bias circuit according to the seventh embodiment.
  • V CON supplied to the diode 32 through a resistor 30
  • the capacitance of the diode 32 can be varied.
  • a diode 33 is added so that the gate bias of the current source FET 5 varies with the variation in the gate bias of the current source FET 9, and the voltage V CON is supplied to the diode 33 through a resistor 31.
  • the diode 32 is employed as a capacitance element connected to the gate of the current source FET 9 so that the controlling voltage V CON is applied to the diode 32 through the resistor 30. Therefore, fine adjustment is possible, as compared with the MIM capacitor having used in the seventh embodiment. Further, even when there arises a phase shift between the first and second level shift circuits 1 and 2 due to secular variation during use, the phase shift can be corrected by adjusting the controlling voltage V CON externally.

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Cited By (14)

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US6285256B1 (en) 2000-04-20 2001-09-04 Pericom Semiconductor Corp. Low-power CMOS voltage follower using dual differential amplifiers driving high-current constant-voltage push-pull output buffer
US6342814B1 (en) * 1999-08-10 2002-01-29 Oki Electric Industry Co., Ltd. Operational amplifier
US20040189350A1 (en) * 2003-03-28 2004-09-30 Renesas Technology Corp. Semiconductor device including a differential transistor pair
US6850546B2 (en) * 2001-06-08 2005-02-01 Agilent Technologies, Inc. Driver circuit
US20050151587A1 (en) * 2002-10-08 2005-07-14 Masayuki Ozasa Differential amplifier and calculation amplifier
US20070013410A1 (en) * 2005-07-15 2007-01-18 Hari Dubey Integrated receiver circuit
US20090261905A1 (en) * 2005-10-24 2009-10-22 Niigata Seimitsu Co., Ltd. Open gain adjustment circuit for operational amplifier
CN102075152A (zh) * 2010-12-24 2011-05-25 清华大学 线性源跟随器
US20140240045A1 (en) * 2013-02-22 2014-08-28 Intel Mobile Communications GmbH Amplifier stage
US9276529B1 (en) * 2014-10-03 2016-03-01 Hrl Laboratories, Llc High performance GaN operational amplifier with wide bandwidth and high dynamic range
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US10218322B2 (en) * 2015-09-15 2019-02-26 Firecomms Limited Transconductance current source
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US6617924B2 (en) 1999-08-10 2003-09-09 Oki Electric Industry Co., Ltd. Operational amplifier having large output current with low supply voltage
US6714077B2 (en) 1999-08-10 2004-03-30 Oki Electric Industry Co., Ltd. Operational amplifier having large output current with low supply voltage
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US6285256B1 (en) 2000-04-20 2001-09-04 Pericom Semiconductor Corp. Low-power CMOS voltage follower using dual differential amplifiers driving high-current constant-voltage push-pull output buffer
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US20070182487A1 (en) * 2002-10-08 2007-08-09 Matsushita Electric Industrial Co., Ltd. Differential amplifer and operational amplifier
US7116170B2 (en) * 2002-10-08 2006-10-03 Matsushita Electric Industrial Co., Ltd. Differential amplifier and calculation amplifier
US20070001761A1 (en) * 2002-10-08 2007-01-04 Matsushita Electric Industrial Co., Ltd. Differential amplifier and operational amplifier
US7215195B2 (en) 2002-10-08 2007-05-08 Matsushita Electric Industrial Co., Ltd. Differential amplifier and operational amplifier
US7271652B2 (en) 2002-10-08 2007-09-18 Matsushita Electric Industrial Co., Ltd. Differential amplifier and operational amplifier
US20050151587A1 (en) * 2002-10-08 2005-07-14 Masayuki Ozasa Differential amplifier and calculation amplifier
US6809582B2 (en) * 2003-03-28 2004-10-26 Renesas Technology Corp. Semiconductor device including a differential transistor pair
US20040189350A1 (en) * 2003-03-28 2004-09-30 Renesas Technology Corp. Semiconductor device including a differential transistor pair
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US20070013410A1 (en) * 2005-07-15 2007-01-18 Hari Dubey Integrated receiver circuit
US7368948B2 (en) * 2005-07-15 2008-05-06 Infineon Technologies Ag Integrated receiver circuit
US20090261905A1 (en) * 2005-10-24 2009-10-22 Niigata Seimitsu Co., Ltd. Open gain adjustment circuit for operational amplifier
CN102075152A (zh) * 2010-12-24 2011-05-25 清华大学 线性源跟随器
CN102075152B (zh) * 2010-12-24 2013-04-03 清华大学 线性源跟随器
US20140240045A1 (en) * 2013-02-22 2014-08-28 Intel Mobile Communications GmbH Amplifier stage
US9590575B2 (en) * 2013-02-22 2017-03-07 Intel Deutschland Gmbh Amplifier stage
US9276529B1 (en) * 2014-10-03 2016-03-01 Hrl Laboratories, Llc High performance GaN operational amplifier with wide bandwidth and high dynamic range
US10218322B2 (en) * 2015-09-15 2019-02-26 Firecomms Limited Transconductance current source
EP3404831A1 (en) * 2017-05-16 2018-11-21 Nokia Solutions and Networks Oy Photoreceiver with pre-equalizing differential transimpedance amplifier
CN112106296A (zh) * 2018-05-11 2020-12-18 华为技术有限公司 一种放大器、放大电路及移相器
US11533031B2 (en) 2018-05-11 2022-12-20 Huawei Technologies Co., Ltd. Amplifier, amplification circuit and phase shifter
CN112106296B (zh) * 2018-05-11 2022-12-27 华为技术有限公司 一种放大器、放大电路及移相器
US20210194437A1 (en) * 2019-12-20 2021-06-24 Qorvo Us, Inc. Power amplifier circuitry
US11581855B2 (en) * 2019-12-20 2023-02-14 Qorvo Us, Inc. Power amplifier circuitry

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JPH10163766A (ja) 1998-06-19
JP3545142B2 (ja) 2004-07-21

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