US5537307A - Control device for system interconnection inverter - Google Patents

Control device for system interconnection inverter Download PDF

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Publication number
US5537307A
US5537307A US08/458,017 US45801795A US5537307A US 5537307 A US5537307 A US 5537307A US 45801795 A US45801795 A US 45801795A US 5537307 A US5537307 A US 5537307A
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United States
Prior art keywords
signal
frequency
voltage amplitude
correction
voltage
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Expired - Fee Related
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US08/458,017
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English (en)
Inventor
Syunichi Hirose
Nobukazu Takashima
Susumu Tanaka
Tatsuro Yamaguchi
Hidetaka Sato
Minoru Abe
Masahito Ooyama
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Toshiba Corp
Tokyo Electric Power Co Holdings Inc
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Toshiba Corp
Tokyo Electric Power Co Inc
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Priority claimed from JP00331593A external-priority patent/JP3164678B2/ja
Priority claimed from JP18265493A external-priority patent/JP3164701B2/ja
Application filed by Toshiba Corp, Tokyo Electric Power Co Inc filed Critical Toshiba Corp
Priority to US08/458,017 priority Critical patent/US5537307A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J9/00—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting
    • H02J9/04—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source
    • H02J9/06—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems
    • H02J9/062—Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over, e.g. UPS systems for AC powered loads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M8/00—Fuel cells; Manufacture thereof
    • H01M8/04—Auxiliary arrangements, e.g. for control of pressure or for circulation of fluids
    • H01M8/04298—Processes for controlling fuel cells or fuel cell systems
    • H01M8/04313—Processes for controlling fuel cells or fuel cell systems characterised by the detection or assessment of variables; characterised by the detection or assessment of failure or abnormal function
    • H01M8/04537—Electric variables
    • H01M8/04574—Current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M8/00—Fuel cells; Manufacture thereof
    • H01M8/04—Auxiliary arrangements, e.g. for control of pressure or for circulation of fluids
    • H01M8/04298—Processes for controlling fuel cells or fuel cell systems
    • H01M8/04694—Processes for controlling fuel cells or fuel cell systems characterised by variables to be controlled
    • H01M8/04858—Electric variables
    • H01M8/04895—Current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J3/00—Circuit arrangements for ac mains or ac distribution networks
    • H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
    • H02J3/40—Synchronising a generator for connection to a network or to another generator
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H02M7/53875—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current with analogue control of three-phase output
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
    • H01M8/00—Fuel cells; Manufacture thereof
    • H01M8/04—Auxiliary arrangements, e.g. for control of pressure or for circulation of fluids
    • H01M8/04298—Processes for controlling fuel cells or fuel cell systems
    • H01M8/04694—Processes for controlling fuel cells or fuel cell systems characterised by variables to be controlled
    • H01M8/04858—Electric variables
    • H01M8/04865—Voltage
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02B90/10—Applications of fuel cells in buildings
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/30—Hydrogen technology
    • Y02E60/50—Fuel cells

Definitions

  • This invention relates to a control device for an inverter which operates the supply and reception of power to and from an AC system by interconnecting with the AC system, and more particularly relates to a control device for a system interconnection inverter which can continuously supply power to a load by the inverter alone even if the interconnection with the AC system is interrupted.
  • System interconnection inverters are used for supplying power to loads from DC power sources, such as fuel cells, secondary battery cells and rectifiers. They are also used for receiving and supplying power between these DC power sources and AC systems.
  • DC power sources such as fuel cells, secondary battery cells and rectifiers. They are also used for receiving and supplying power between these DC power sources and AC systems.
  • FIG. 14 is a diagram showing a prior art example of a control device for this type of system interconnection inverter.
  • the prior art control device is composed of a voltage source type self-commutated inverter 10 and an inverter control device 100.
  • Voltage source type self-commutated inverter 10 is composed of an inverter main circuit 1 (described later), a DC capacitor 2 and a transformer 3.
  • Inverter main circuit 1 has power conversion devices (controllable switching devices) GU, GV, GW, GX, GY and GZ and rectifying devices DU, DV, DW, DX, DY and DZ.
  • Power conversion devices having self-turn-off ability such as GTOs (gate turn-off thyristors), power transistors, IGBTs (insulated gate bipolar transistors) and SI (static induction type) thyristors may be used as power conversion devices GU, GV, GW, GX, GY and GZ.
  • Self-commutated inverter 10 is interconnected to a 3-phase AC system 6 via an interconnection circuit breaker 5 and is also connected to a load 7.
  • Inverter control device 100 is composed of an active/reactive current reference generator 101, a phase detector 103, an active/reactive current detector 104, a current control circuit 105, a gate control circuit 106 and also Hall CTs 201,202 and 203.
  • Inverter main circuit 1 can control the 3-phase output voltage of inverter main circuit 1 by altering the conductive periods of power conversion devices GU, GV, GW, GX, GY and GZ. It also controls the current supplied to and received from AC system 6 via the impedance of transformer 3 by adjusting the phase and amplitude of the 3-phase output voltage of inverter main circuit 1 in response to the phase and amplitude of system voltages VR, VS and VT of AC system 6.
  • inverter 10 supplies and receives active power to and from AG system 6 and also supplies reactive power to AC system 6 via interconnection circuit breaker 5 by converting the DC power of a DC power source 4 to active power or converting active power to DC power. Similarly, inverter 10 also supplies active power and reactive power to load 7.
  • inverter control device 100 Current control of inverter 10 is performed by inverter control device 100 as follows.
  • Phase detector 103 detects a phase ⁇ of system voltages VR, VS and VT of 3-phase AC system 6 on the inverter 10 side.
  • Active/reactive current detector 104 detects the active current component and the reactive current component from inverter output AC currents iR, iS and iT which are detected by Hall CTs 201, 202 and 203, as respective active current detected value iq and reactive current detected value id.
  • Current control circuit 105 computes inverter output voltage references VRc, VSc and VTc, which determine the 3-phase output voltage of inverter main circuit 1, so that active current detected value iq and reactive current detected value id from active/reactive current detector 104 equals active current reference value iqc and reactive current reference value idc from active/reactive current reference generator 101.
  • inverter output voltage references VRc, VSc and VTc the phase of the inverter output voltage for that of system voltages VR, VS and VT of AC system 6 are to be determined. Therefore, system voltage phase ⁇ detected by phase detector 103 is used in the calculation.
  • Gate control circuit 106 compares inverter output voltage references VRc, VSc, and VTc with a triangular carrier wave signal produced within gate control circuit 106, and outputs gate signals which determine the conductive periods of power conversion devices GU, GV, GW, GX, GY and GZ composing inverter main circuit 1.
  • gate control circuit 106 is given in the reference B stated below.
  • the prior art system interconnection inverter control device in FIG. 14 has the following problem. That is to say, when interconnection circuit breaker 5 opens due to the occurrence of a fault or the like in AC system 6, inverter 10 cannot execute the supply and reception of power with AC system 6 and, at the same time, the phase of the AC voltage of AC system 6 cannot be detected. Therefore, active current component iq and reactive current component id, which are detected from inverter output AC currents iR, iS and iT, cannot be outputted as active current reference value iqc and reactive current reference value idc from active/reactive current reference generator 101 as they should be. As a result, the output voltage and frequency of inverter 10 increase or decrease so that the desired power cannot be supplied to load 7. Therefore, the problem arises that the operation of inverter 10 has to be stopped.
  • one object of this invention is to provide a control device for a system interconnection inverter which can continue to supply to the load by the inverter alone while the inverter is executing the supply and reception of power with an AC system by interconnection with the AC system, even if interconnection with the AC system is interrupted.
  • Another object of this invention is to provide a control device for a system interconnection inverter which can increase the reliability of a system using a system interconnection inverter and can expand the range of its application, since, whether the interconnection state of the system interconnection inverter and the AC system changes from the interconnected state to the sole state or conversely from the sole state to the interconnected state, it can supply the appropriate power to the load from a system using a system interconnection inverter without taking this state alteration as a state signal for the interconnection circuit breaker or the like, or without temporarily interrupting the operation of the system interconnection inverter.
  • the inverter is connected to an AC system via an interconnection circuit breaker, is connected to a load, converts DC power from a DC power source to AC power, and supplies or receives the AC power to or from the AC system.
  • the load receives the AC power.
  • the control device includes active/reactive current reference generator for generating an active current reference signal and a reactive current reference signal and an active/reactive current detector for detecting an active current component and a reactive current component of an output AC current of the inverter to output as an active current signal and a reactive current signal, respectively.
  • the control device further includes a phase detector for detecting a phase of the AC Voltage to output as a phase signal, a frequency detector for detecting a frequency of the AC voltage to output as a frequency signal and a voltage amplitude detector for detecting an amplitude of the AC voltage to output as a voltage amplitude signal.
  • the control device also includes a frequency reference generator for generating a frequency reference signal and a voltage amplitude reference generator for generating a voltage amplitude reference signal.
  • the control device also includes a frequency correction computing circuit for detecting a frequency deviation between the frequency reference signal and the frequency signal and for generating a frequency correction signal based on the frequency deviation, and a voltage amplitude correction computing circuit for detecting a voltage amplitude deviation between the voltage amplitude reference signal and the voltage amplitude signal and for generating a voltage amplitude correction signal based on the voltage amplitude deviation.
  • the control device further includes an adder for adding the active current reference signal and the voltage amplitude correction signal to output as an active current correction reference signal, and for adding the reactive current reference signal and the frequency correction signal to output as a reactive current correction signal.
  • the control device still further includes a current control circuit connected to receive the phase signal, the active current signal, the reactive current signal, the active current correction reference signal, and the reactive current correction reference signal for generating an output voltage reference signal for the inverter such that the active current signal equals the active current correction reference signal and the reactive current signal equals the reactive current correction reference signal, and a gate control circuit for controlling the output voltage of the inverter based on the output voltage reference signal.
  • a control device for an inverter as described above.
  • the control device is also constructed as described above.
  • the frequency correction computing circuit generates the frequency correction signal only when the frequency deviation exceeds a first specified value
  • the voltage amplitude correction computing circuit generates the voltage amplitude correction signal only when the voltage amplitude deviation exceeds a second specified value.
  • control device for an inverter as described above.
  • the control device is also constructed as described above, and further includes a voltage/frequency monitoring circuit connected to receive the frequency signal and the voltage amplitude signal for generating a switching-OFF signal when the frequency signal is outside a first specified band or the voltage amplitude signal is outside a second specified band.
  • the control device also includes a computing circuit saturation detector connected to receive the frequency correction signal and the voltage amplitude correction signal for generating a switching-OFF cancellation signal only when a state where the frequency correction signal exceeds a first maximum output level has continued for more than a specified period or a state where the voltage correction signal exceeds a second maximum output level has continued for more than the specified period.
  • the frequency correction computing circuit generates the frequency correction signal only when the switching-OFF signal is applied and the switching-OFF cancellation signal is not applied, and the voltage amplitude correction computing circuit generates the voltage amplitude correction signal only when the switching-OFF signal is applied and the switching-OFF cancellation signal is not applied.
  • a deadband-fitted frequency correction computing circuit and a deadband-fitted voltage amplitude correction computing circuit are provided in the control device for the inverter. Therefore, unnecessary control operations which occur due to system fluctuation during system interconnected operation can be suppressed.
  • a voltage/frequency monitoring circuit regards times when the fluctuations of the voltage amplitude and the frequency exceed the specified bands as transferring to sole operation. Also, by operating the switch-fitted voltage amplitude correction computing circuit and the switch-fitted frequency correction computing circuit, the operation of commencing the correction control can be executed. Therefore, the operation of this correction control is suppressed during system fluctuations, and also control with excellent accuracy without deadbands can be executed when transferring to sole operation. Moreover, when transferring from sole operation to interconnected operation, the computing circuit saturation detector monitors the levels of the voltage correction signal and the frequency correction signal. Therefore, the operation of stopping correction control when the output continuously exceeds a specified level can be executed.
  • FIGS. 1a and 1b are block diagrams showing the composition of a first embodiment of a system interconnection inverter control device of this invention
  • FIG. 2 is a diagram showing an example of a practical circuit for a frequency correction computing circuit 131 in FIGS. 1a and 1b;
  • FIG. 3 is a diagram showing an example of a practical circuit for a voltage amplitude correction computing circuit 132 in FIGS. 1a and 1b;
  • FIG. 4 is a diagram to illustrate the operation of the main circuit variables when the inverter 10 in FIGS. 1a and 1b switches from interconnected operation to sole operation;
  • FIG. 5 is a vector diagram to illustrate the load voltage alteration at the time the inverter 10 in FIGS. 1a and 1b switches from interconnected operation to sole operation;
  • FIGS. 6a and 6b are block diagrams showing the composition of a second embodiment of a system interconnection inverter control device of this invention.
  • FIG. 7 is a diagram showing an example of a practical circuit for a deadband-fitted frequency correction computing circuit 131A in FIG. 6;
  • FIG. 8 is a diagram showing an example of a practical circuit for a deadband-fitted voltage amplitude correction computing circuit 132A in FIG. 6;
  • FIG. 9a and 9b are showing the composition of a third embodiment of a system interconnection inverter control device of this invention.
  • FIG. 10 is a diagram showing an example of a practical circuit for a switch-fitted frequency correction computing circuit 141 in FIGS. 9a and 9b;
  • FIG. 11 is a diagram showing an example of a practical circuit for a switch-fitted voltage amplitude correction computing circuit 142 in FIGS. 9a & 9b;
  • FIG. 12 is a diagram showing an example of a practical circuit for a voltage/frequency monitoring circuit 144 in FIGS. 9a and 9b;
  • FIG. 13 is a diagram showing an example of a practical circuit for a computing circuit saturation detector 143 in FIGS. 9a and 9b;
  • FIG. 14 is a diagram to illustrate the composition of an example of a prior art system interconnection inverter and its control device.
  • FIGS. 1a and 1b are showing the composition of a first embodiment of this invention. The following additional features differ from the prior art example of FIG. 14:
  • a frequency detector 107 which composes the frequency detector means
  • a voltage amplitude detector 108 which composes the voltage detector means
  • an adder circuit 110 which composes the adder means
  • a voltage amplitude reference generator 121 which composes the voltage amplitude reference generator means
  • a frequency reference generator 122 which composes the frequency reference generator means
  • a frequency correction computing circuit 131 which composes the frequency correction computing circuit means
  • a voltage amplitude correction computing circuit 132 which composes the voltage amplitude correction computing circuit means.
  • Frequency detector 107 detects the frequency of the AC voltage applied on load 7 from AC system 6 or inverter 10 and outputs a frequency signal F.
  • Voltage amplitude detector 108 detects the amplitude of the AC voltage and outputs a voltage amplitude signal V.
  • Frequency reference generator 122 outputs a frequency reference signal Fc.
  • Voltage amplitude reference generator 121 outputs a voltage amplitude reference signal Vc.
  • Frequency correction computing circuit 131 outputs a frequency correction signal EF from the deviation between frequency reference signal Fc and frequency signal F, as described later.
  • Voltage amplitude correction computing circuit 132 outputs a voltage amplitude correction signal EV from the deviation between voltage amplitude reference signal Vc and voltage amplitude signal V.
  • Adder 111 subtracts voltage amplitude correction signal EV outputted from voltage amplitude correction computing circuit 132 from active current reference iqc outputted from active/reactive current reference generator 101, and outputs an active current correction reference signal iqm to current control circuit 105. Also, adder 112 subtracts frequency correction signal EF outputted from frequency correction computing circuit 131 from reactive current reference idc outputted from active/reactive current reference generator 101, and outputs a reactive current correction reference signal idm to current control circuit 105.
  • FIG. 2 shows a practical circuit example for frequency correction computing circuit 131 in FIG. 1.
  • Circuit 131 is composed of an adder 1311 and a proportional integration computing circuit 1312.
  • Proportional integration computing circuit 1312 is composed of an operational amplifier Aa, resistors R1a, R2a and R3a and a capacitor Ca.
  • FIG. 3 shows a practical circuit example for voltage amplitude correction computing circuit 132 in FIG. 1.
  • Circuit 132 is composed of an adder 1321 and a proportional integration computing circuit 1322.
  • Proportional integration computing circuit 1322 is composed of an operational amplifier Ab, resistors R1b, R2b and R3b and a capacitor Cb.
  • frequency detector 107 detects the frequency of the AC voltage on the inverter 10 side of interconnection circuit breaker 5, and outputs frequency signal F.
  • Voltage amplitude detector 108 detects the amplitude of the AC voltage on the inverter 10 side of interconnection circuit breaker 5 and outputs voltage amplitude signal V.
  • Frequency reference generator 122 outputs frequency reference signal Fc which is equal to the rated frequency of the voltage of AC system 6.
  • Voltage amplitude reference generator 121 outputs voltage amplitude reference signal Vc which is equal to the rated amplitude of the voltage of AC system 6.
  • Frequency correction computing circuit 131 inputs frequency reference signal Fc from frequency reference generator 122 and frequency signal F from frequency detector 107. After taking the difference by adder 1311, it outputs frequency correction signal EF via proportional integration computing circuit 1312.
  • Voltage amplitude correction computing circuit 132 inputs voltage reference signal Vc from voltage amplitude reference generator 121 and voltage amplitude signal V from voltage amplitude detector 108. After taking the difference by adder 1321, it outputs voltage amplitude correction signal EV via proportional integration computing circuit 1322.
  • Adding circuit 110 subtracts frequency correction signal EF outputted from frequency correction computing circuit 131 from reactive current reference idc outputted from active/reactive current reference generator 101 using adder 112, and outputs reactive current correction reference signal idm. At the same time, it subtracts voltage amplitude correction signal EV outputted from voltage amplitude correction computing circuit 132 from active current reference iqc outputted from active/reactive current reference generator 101 using adder 111, and outputs active current correction reference signal iqm.
  • Current control circuit 105 inputs reactive current reference signal idm outputted from adding circuit 110, in place of reactive current reference idc which was inputted in the prior art example of FIG. 14. At the same time, it inputs active current reference signal iqm outputted from adding circuit 110, in place of active current reference iqc which was inputted in the prior art example of FIG. 14. It then calculates inverter output voltage references VRc, VSc and VTc which determine the 3-phase output voltage of inverter main circuit 1, so that active current detected value iq and reactive current detected value id from active/reactive current detector 104 are equal to active current correction reference signal iqm and reative current correction reference signal idm.
  • frequency detector 107 detects the frequency of the AC voltage of AC system 6 as frequency signal F
  • voltage amplitude detector 108 detects the amplitude of the AC voltage of AC system 6 as voltage amplitude signal V. Therefore, frequency signal F and frequency reference signal Fc are equal and also, voltage amplitude signal V and voltage amplitude reference signal Vc are equal.
  • frequency correction signal EF outputted by frequency correction computing circuit 131
  • voltage amplitude correction signal EV outputted by voltage amplitude correction computing circuit 132
  • active current correction reference signal iqm and reactive current correction reference signal idm respectively become equal to active current reference iqc and reactive current reference idc. Therefore, inverter 10 supplies active current and reactive current to AC system 6 and load 7 according to active current reference signal iqc and reactive current reference singal idc from active/reactive current reference generator 101.
  • frequency signal F detected by frequency detector 107 differs from the frequency of the AC voltage of AC system 6.
  • voltage amplitude signal V detected by voltage amplitude detector 108 differs from the amplitude of the AC voltage of AC system 6. Therefore, there is then a difference between frequency signal F and frequency reference signal Fc. Also, there is then a difference between voltage amplitude signal V and voltage amplitude reference signal Vc.
  • frequency correction signal EF outputted from frequency correction computing circuit 131 and voltage amplitude correction signal EV outputted from voltage amplitude correction computing circuit 132 will not become zero.
  • Adding circuit 110 respectively corrects reactive current reference idc and active current reference iqc by frequency correction signal EF and voltage amplitude correction singal EV, and outputs reactive current correction reference signal idm and active current correction reference signal iqm to current control circuit 105.
  • Inverter 10 supplies active current and reactive current to load 7 in response to active current reference signal iqm and reactive current reference signal idm from adding circuit 110.
  • the frequency and amplitude of the inverter output voltage are made equal to frequency reference Fc and voltage amplitude reference Vc.
  • the same control circuit can be used both when interconnection circuit breaker 5 is closed and inverter 10 and AC system 6 are interconnected and when interconnection circuit breaker 5 is open and inverter 10 alone supplies power to load 7. Also, the oscillation which occurs when inverter 10 switches from interconnected operation to sole operation or, conversely switches from sole operation to interconnected operation can be reduced.
  • FIG. 4 expresses the embodiment of FIGS. 1a and 1b as a single line diagram, and is a diagram illustrating the operation of the main circuit variables when inverter 10 has switched from interconnected operation to sole operation.
  • FIG. 5 is a vector diagram illustrating the fluctuation of the load voltage at the time when inverter 10 switches from interconnected operation to sole operation.
  • inverter output current outputted by inverter 10 is shown as Ic, the load current flowing in load 7 as Is, and the system current flowing in AC system 6 via interconnection circuit breaker 5 as Ig.
  • the load voltage generated by load 7 is shown as Vs and the system voltage of AC system 6 as Vg.
  • the load impedance is shown as Z.
  • AC system 6 is taken as an infinite bus-line.
  • Inverter 10 is outputting inverter output current Ic equal to the current reference of inverter control device 100.
  • Equation (1) can be established for load voltage Vs and system voltage Vg.
  • Equation (2) can be established for inverter output current Ic, load current Is and system current Ig.
  • Equation (3) can be established for load voltage Vs and load current Is.
  • FIG. 5 illustrates this state by vectors.
  • inverter 10 corrects the active current reference value Iqc of current value Ic by the deviation between the AC system voltage rated amplitude and the AC voltage amplitude, and also corrects the reactive current reference value idc by the deviation between the AC system voltage rated frequency and the AC voltage frequency, at the point when it shifts from interconnected operation to sole operation.
  • inverter 10 can control the output voltage so that it becomes equal to the rated amplitude and the rated frequency of the AC system voltage.
  • composition of the embodiment in FIG. 1b achieves adding circuit 110, frequency correction computing circuit 131 and voltage amplitude correction computing circuit 132 by electronic circuits.
  • these may also be achieved by software using microcomputers, etc.
  • current control circuit 105 and active/reactive current detector 104 are achieved by microcomputer software in the prior art example of FIG. 14, this embodiment has the advantage of being able to be readily incorporated into the prior art control device by adding the functions of adding circuit 110, frequency correction computing circuit 131 and voltage amplitude correction computing circuit 132 as software.
  • FIGS. 6a and 6b are block diagrams showing the composition of the second embodiment of this invention. Points which differ from the first embodiment of FIGS. 1a and 1b are the following:
  • a deadband-fitted frequency correction computing circuit 131A provided in place of frequency correction computing circuit 131, which composes the frequency correction computing circuit means;
  • a deadband-fitted voltage amplitude correction computing circuit 132A provided in place of voltage amplitude correction computing circuit 132, which composes the voltage amplitude correction computing circuit means.
  • Deadband-fitted frequency correction computing circuit 131A inputs frequency reference signal Fc from frequency reference generator 122 and frequency signal F from frequency detector 107. After taking the difference by an adder 1311A in FIG. 7, it outputs frequency correction signal EF via a deadband generating circuit 1313A and a proportional integration computing circuit 1312A as described later.
  • Deadband-fitted voltage amplitude correction computing circuit 132A inputs voltage amplitude reference signal Vc from voltage amplitude reference generator 121 and voltage amplitude signal V from voltage amplitude detector 108. After taking the difference by an adder 1321A in FIG. 8, it outputs voltage amplitude correction signal EV via a deadband generating circuit 1323A and a proportional integration computing circuit 1322A.
  • Adding circuit 110 has adders 111 and 112.
  • Adder 111 subtracts voltage amplitude correction signal EV outputted from deadband-fitted voltage amplitude correction computing circuit 132A from active current reference iqc outputted from active/reactive current reference generator 101, and outputs active current correction reference signal iqm to current control circuit 105.
  • adder 112 subtracts frequency correction signal EF outputted from deadband-fitted frequency correction computing circuit 131A from reactive current reference idc outputted from active/reactive current reference generator 101, and outputs reactive current correction reference signal idm to current control circuit 105.
  • FIG. 7 shows a practical circuit example for deadband-fitted frequency correction computing circuit 131A in FIG. 6b.
  • This is composed of an adder 1311A, a deadband generating circuit 1313A and a proportional integration computing circuit 1312A.
  • Proportional integration computing circuit 1312A is composed of an operational amplifier Ac, resistors R1c, R2c and R3c and a capacitor Cc.
  • Deadband generating circuit 1313A is composed of Zener diodes ZD1c, ZD2c and a resistor R4c, and receives the difference outputted from adder 1311A and applies the difference to proportional integration computing circuit 1312A only when the difference exceeds a first specified value, for example 0.5 Hz.
  • FIG. 8 shows a practical circuit example for deadband-fitted voltage amplitude correction computing circuit 132A in FIG. 6b.
  • This is composed of an adder 1321A, a proportional integration computing circuit 1322A and a deadband generating circuit 1323A.
  • Proportional integration computing circuit 1322A is composed of an operational amplifier Ad, resistors R1d, R2d and R3d and a capacitor Cd.
  • Deadband generating circuit 1323A is composed of Zener diodes ZD1d, ZD2d and a resistor R4d, and receives the difference outputted from adder 1321A and applies the difference to proportional integration computing circuit 1322A only when the difference exceeds a second specified value, for example 5% of voltage Vc.
  • deadband-fitted frequency correction computing circuit 131A inputs frequency reference signal Fc from frequency reference generator 122 and frequency signal F from frequency detector 107. After taking the difference by adder 1311A in FIG. 7, it outputs frequency correction signal EF via deadband generating circuit 1313A and proportional integration computing circuit 1312A.
  • Deadband-fitted voltage amplitude correction computing circuit 132A inputs voltage reference signal Vc from voltage amplitude reference generator 121 and voltage amplitude signal V from voltage amplitude detector 108. After taking the difference by adder 1321A in FIG. 8, it outputs voltage amplitude correction signal EV via deadband generating circuit 1323A and proportional integration computing circuit 1322A.
  • Adding circuit 110 subtracts frequency correction signal EF outputted from deadband-fitted frequency correction computing circuit 131A from reactive current reference idc outputted from active/reactive current reference generator 101 using adder 112, and outputs reactive current correction reference signal idm. At the same time, it subtracts voltage amplitude correction signal EV outputted from deadband-fitted voltage amplitude correction computing circuit 132A from active current reference iqc outputted from active/reactive current reference generator 101 using adder 111, and outputs active current correction reference signal iqm.
  • Current control circuit 105 inputs reactive current reference signal idm outputted from adding circuit 110, and active current reference signal iqm outputted from adding circuit 110. It then calculates inverter output voltage references VRc, VSc and VTc which determine the 3-phase output voltage of inverter main circuit 1, so that active current detected value iq and reactive current detected value id from active/reactive current detector 104 are equal to active current correction reference signal iqm and reactive current correction reference signal idm.
  • frequency detector 107 detects the AC voltage frequency of AC system 6 as frequency signal F
  • voltage amplitude detector 108 detects the AC voltage amplitude of AC system 6 as voltage amplitude signal V. Therefore, frequency signal F and frequency reference signal Fc are equal and also, voltage amplitude signal V and voltage amplitude reference signal Vc are equal.
  • frequency correction signal EF outputted by deadband-fitted frequency correction computing circuit 131A and voltage amplitude correction signal EV outputted by deadband-fitted voltage amplitude correction computing circuit 132A become zero.
  • active current correction reference signal iqm and reactive current correction reference signal idm respectively become equal to active current reference iqc and reactive current reference idc. Therefore, inverter 10 supplies active current and reactive current to AC system 6 and load 7 according to active current reference signal iqc and reactive current reference signal idc from active/reactive current reference generator 101.
  • frequency correction signal EF and voltage amplitude correction signal EV due to fluctuations in the system conditions during interconnected operation are suppressed by causing the deviation between frequency signal F and frequency reference signal Fc and the deviation between voltage amplitude signal V and voltage reference signal Vc to be within the deadbands of deadband generating circuits 1313A and 1323A.
  • frequency signal F detected by frequency detector 107 differs from the frequency of the AC voltage of AC system 6.
  • voltage amplitude signal V detected by voltage amplitude detector 108 differs from the amplitude of the AC voltage of AC system 6. Therefore, there will be a deviation between frequency signal F and frequency reference signal Fc which exceeds the first specified value corresponding to a first deadband. Also, there will be a deviation between voltage amplitude signal V and voltage amplitude reference signal Vc which exceeds the second specified value corresponding to a second deadband.
  • frequency correction signal EF outputted from deadband-fitted frequency correction computing circuit 131A and voltage amplitude correction signal EV outputted from deadband-fitted voltage amplitude correction computing circuit 132A will not become zero.
  • Adding circuit 110 respectively corrects reactive current reference idc and active current reference iqc by frequency correction signal EF and voltage amplitude correction signal EV, and outputs reactive current correction reference signal idm and active current correction reference signal iqm to current control circuit 105.
  • Inverter 10 supplies active current and reactive current to load 7 in response to active current reference signal iqm and reactive current reference signal idm from adding circuit 110.
  • the frequency and amplitude of the inverter output voltage can be controlled in the vicinity of frequency reference signal Fc and voltage amplitude reference Vc, respectively.
  • the same control circuit can be used both when interconnection circuit breaker 5 is closed and inverter 10 and AC system 6 are interconnected and when interconnection circuit breaker 5 is open and inverter 10 alone supplies power to load 7. Also, the disturbance which occurs when inverter 10 switches from interconnected operation to sole operation or, conversely switches from sole operation to interconnected operation can be reduced.
  • the capability of suppressing unnecessary control operations which occur due to system fluctuations during interconnected operation is added to the basic operation of the embodiment in FIG. 1 by the use of deadband-fitted frequency correction computing circuit 131A and deadband-fitted voltage amplitude correction computing circuit 132A.
  • FIGS. 9a and 9b are block diagrams showing the schematic composition. Here, parts which are the same as in FIG. 1 have been given the same symbols and their descriptions have been omitted. Points which differ from FIG. 1 are the provision of:
  • FIG. 10 shows a practical circuit example for switch-fitted frequency correction computing circuit 141.
  • Circuit 141 is composed of an adder 1311B, a switch circuit 1314B which is composed of a field effect transistor SWe, a resistor R21e and a NAND circuit D3e, and a proportional integration circuit 1312B which is composed of resistors R1e, R2e and R3e, a capacitor Ce and an operational amplifier Ae.
  • FIG. 11 shows a practical circuit example for switch-fitted voltage amplitude correction computing circuit 142.
  • Circuit 142 is composed of an adder 1321B, a switch circuit 1324B which is composed of a field effect transistor SWf, a resistor R21f and a NAND circuit D3f, and a proportional integration circuit 1322B which is composed of resistors R1f, R2f and R3f, a capacitor Cf and an operational amplifier Af.
  • FIG. 12 shows a practical circuit example of voltage/frequency monitoring circuit 144.
  • Circuit 144 is composed of reference voltage sources E1, E2, E3 and E4, operational amplifiers A1, A2, A3 and A4, NAND circuits D1 and D3 and an OR circuit D2.
  • FIG. 13 shows a practical circuit example for computing circuit saturation detector 143. This is composed of absolute value circuits AB1 and AB2, reference voltage sources E5 and E6, operational amplifiers A5 and A6, an OR circuit D4, a resistor R11, a capacitor C11 and an inverse logic circuit D5.
  • voltage/frequency monitoring circuit 144 monitors the various output quantities of frequency detector 107 and voltage amplitude detector 108. When these exceed or fall below the set upper and lower limit values, it outputs a switching-OFF signal S to switch OFF the switches in switch-fitted frequency correction computing circuit 141 and switch-fitted voltage amplitude correction computing circuit 142.
  • computing circuit saturation detector 143 executes the operation of switching ON the relevant switch by outputting a switching-OFF cancellation signal CLS.
  • voltage/frequency monitoring circuit 144 regards as transferring to sole operation the time when the fluctuations of the voltage amplitude and the frequency exceed the specified bands. Also, by operating switch-fitted frequency correction computing circuit 141 and switch-fitted voltage amplitude correction computing circuit 142, inverter control device 100 executes the operation of commencing the above-described correction control. Therefore, the operation of this correction control is suppressed during system fluctuations when the fluctuations of the voltage amplitude and the frequency do not exceed the specified bands. And also control with excellent accuracy without deadbands can be executed when transferring to sole operation.
  • the levels of voltage correction signal EV and frequency correction signal EF are monitored by computing circuit saturation detector 143. Therefore, the operation of stopping correction control when the output continuously exceeds a specified level can be executed.
  • FIGS. 9a and 9b the alteration of the frequency or the voltage occurring when inverter 10 is disconnected from AC system 6 is detected by voltage/frequency monitoring circuit 144.
  • the correction control is commenced by switching OFF the switches in switch-fitted frequency correction computing circuit 141 and switch-fitted voltage amplitude correction computing circuit 142.
  • switching-OFF operation is executed when switching-OFF signal S becomes logic 1 and a switching-OFF cancellation signal CLS is logic 1.
  • switching-OFF signal S becomes logic 1 when frequency signal F is greater than the value of reference voltage source E1 which indicates the upper limit value for frequency signal F
  • NAND circuits D3e and D3f in FIGS. 10 and 11 output logic 0 and field effect transistors SWe and SWf become non-conductive.
  • inverter 10 has transferred form sole operation to interconnected operation is as follows.
  • voltage amplitude signal V and frequency signal F are respectively equal to voltage reference signal Vc outputted from voltage amplitude reference generator 121 and frequency reference signal Fc outputted from frequency reference generator 122, the values of frequency correction signal EF outputted from switch-fitted frequency correction computing circuit 141 and voltage amplitude correction singal EV outputted from switch-fitted voltage amplitude correction computing circuit 142 are zero. Therefore, operation continues unchanged.
  • the switching ON operation is executed when the switching-OFF cancellation signal CLS becomes logic 0.
  • NAND circuits D3e and D3f in FIGS. 10 and 11 output logic 1 and field effect transistors SWe and SWf become conductive.
  • the signal delay time is provided commonly for signals EF and EV. But according to this invention, it is possible that a first delay time and a second delay time are provided for signals EF and EV, separately.
  • this embodiment When using this embodiment, highly accurate operation becomes possible since there is no deadband in the control system when transferring to sole operation. Also this embodiment can use the same control circuit both when interconnection circuit breaker 5 is closed and inverter 10 and AC system 6 are interconnected and when interconnection circuit breaker 5 is open and inverter 10 supplies power to load 7 by itself. The disturbance which occurs when inverter 10 switches from interconnected operation to sole operation or, conversely, from sole operation to interconnected operation can be reduced.
  • This invention is not limited to the embodiments described above.
  • the embodiment in FIG. 6b achieves adding circuit 110, deadband-fitted frequency correction computing circuit 131A and deadband-fitted voltage amplitude correction computing circuit 132A by electronic circuits.
  • these may also be achieved by software using microcomputers, etc.
  • current control circuit 105 and active/reactive current detector 104 are achieved by microcomputer software in the prior art example of FIG. 14, this invention has the advantage of being able to be readily incorporated into the control device by adding the functions of adding circuit 110, deadband-fitted frequency correction computing circuit 131A and deadband-fitted voltage amplitude correction computing circuit 132A as software.
  • switch-fitted frequency correction computing circuit 141 switch-fitted voltage amplitude correction computing circuit 142, voltage/frequency monitoring circuit 144 and computing circuit saturation detector 143 can be achieved by software.
  • a system interconnection inverter control device can be provided which increases the reliability of the system which uses a system interconnection inverter, and which can expand the range of its application.

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US5703768A (en) * 1995-03-24 1997-12-30 Seikon Epson Corporation Motor control apparatus
US5798633A (en) * 1996-07-26 1998-08-25 General Electric Company Battery energy storage power conditioning system
US5808880A (en) * 1996-08-30 1998-09-15 Otis Elevator Company Power factor controller for active converter
US20050057948A1 (en) * 2003-09-17 2005-03-17 Carlson Douglas S. Auxiliary power generation in a motor transformer
US6919712B1 (en) * 2000-06-19 2005-07-19 Mitsubishi Denki Kabushiki Kaisha Excitation control device and excitation control method
US20060202556A1 (en) * 2002-11-12 2006-09-14 Michiharu Tanaka Control device for automatic machine
US20070223261A1 (en) * 2006-03-22 2007-09-27 Toshiba Mitsubishi-Electric Industrial Systems Corporation Power conversion circuit control apparatus
FR2919768A1 (fr) * 2007-08-03 2009-02-06 Alstom Transport Sa Procede d'alimentation de charges auxiliaires de secours, convertisseur auxiliaire et vehicule ferroviaire pour ce procede.
US20100034003A1 (en) * 2008-08-06 2010-02-11 Hamilton Sundstrand Corporation Electric Power Generation and Conversion with Controlled Magnetics
CN112103967A (zh) * 2013-07-09 2020-12-18 香港大学 自适应ac和/或dc电源

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EP1748542B1 (de) 2005-07-29 2009-09-02 Siemens Aktiengesellschaft Steuerverfahren für ein Brennstoffzellensystem sowie Brennstoffzellensystem
CN103715763B (zh) * 2014-01-20 2016-02-03 中塔新兴通讯技术集团有限公司 提供idc机房节能供电的系统
EP3073599A1 (de) * 2015-03-26 2016-09-28 ABB Technology AG Verfahren zum prüfen eines elektrischen systems und elektrisches system

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Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703768A (en) * 1995-03-24 1997-12-30 Seikon Epson Corporation Motor control apparatus
US5798633A (en) * 1996-07-26 1998-08-25 General Electric Company Battery energy storage power conditioning system
US5808880A (en) * 1996-08-30 1998-09-15 Otis Elevator Company Power factor controller for active converter
US6919712B1 (en) * 2000-06-19 2005-07-19 Mitsubishi Denki Kabushiki Kaisha Excitation control device and excitation control method
US20060202556A1 (en) * 2002-11-12 2006-09-14 Michiharu Tanaka Control device for automatic machine
US20050057948A1 (en) * 2003-09-17 2005-03-17 Carlson Douglas S. Auxiliary power generation in a motor transformer
US7092267B2 (en) * 2003-09-17 2006-08-15 General Motors Corporation Auxiliary power generation in a motor transformer
US20070223261A1 (en) * 2006-03-22 2007-09-27 Toshiba Mitsubishi-Electric Industrial Systems Corporation Power conversion circuit control apparatus
US7310253B2 (en) * 2006-03-22 2007-12-18 Toshiba Mitsubishi-Electric Industrial Systems Corporation Power conversion circuit control apparatus
FR2919768A1 (fr) * 2007-08-03 2009-02-06 Alstom Transport Sa Procede d'alimentation de charges auxiliaires de secours, convertisseur auxiliaire et vehicule ferroviaire pour ce procede.
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US20100034003A1 (en) * 2008-08-06 2010-02-11 Hamilton Sundstrand Corporation Electric Power Generation and Conversion with Controlled Magnetics
US7885089B2 (en) * 2008-08-06 2011-02-08 Hamilton Sundstrand Corporation Electric power generation and conversion with controlled magnetics
CN112103967A (zh) * 2013-07-09 2020-12-18 香港大学 自适应ac和/或dc电源

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EP0607011A3 (en) 1995-09-20
CA2113328C (en) 1998-06-16
DE69411599D1 (de) 1998-08-20

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